FR2681746A1 - RDS identification signal coder/generator for a radio transmission station - Google Patents

Abstract

The invention relates to an RDS identification signal coder/generator for radio transmission. The coder comprises a circuit (1) generating identification information in the form of digital data, intended to constitute the RDS message, and a digital/analog conversion circuit (2) followed by a filtering circuit (3) delivering, from the identification information, a filtered analog signal (saf) on the central frequency of the subcarrier. A circuit (4) allows multiplexing of the audio-multiplexed signal and of the filtered analog signal (saf). Application to stations for transmitting and broadcasting mono- or stereophonic radio messages according to the RDS standard.

Description

RDS IDENTIFICATION SIGNAL ENCODER-GENERATOR
FOR RADIO TRANSMISSION STATION
The invention relates to an encoder-generator of RDS identification signals, in the form of an RDS message modulated on a transmission subcarrier for a radio transmission station.

The European Broadcasting Union, EBU, has studied and developed a data broadcasting system compatible with radio, monophonic or stereophonic programs, broadcast in frequency modulation in band II (87.5 MHZ at 108 MHz in France) and called RDS (acronym of the expression of Anglo-Saxon origin
Radio Data System). This system is currently in use in a number of EEC countries such as the
Republic of Germany, Switzerland, the United Kingdom and the
France or from non-EEC countries, such as the
Sweden, has been the subject of a European standard EN 50067
CENELEC entitled "Specifications of the RDS data broadcasting system" to which or may usefully refer.

 Among the many applications defined for the RDS system, the main ones relate to the identification of transmitting stations and the dissemination of information to assist receiver tuning, which will be considered by way of illustrative example.

 Currently, some frequency modulation receivers such as receivers on board motor vehicles make it possible to decode the amplitude modulated RDS subcarrier, and to exploit some of the information transmitted, in particular by displaying the name of the station clearly. program listened to.

The use of such a type of receiver is expected to become widespread, although these currently constitute high-end equipment and, consequently, a majority of private broadcast stations, even the most modest, will be tempted to offer system services
RDS.

 At present, the equipment constituted by the RDS coders is expensive and delicate equipment to implement, in particular to configure, according to the specifications specific to the transmitting station considered.

In general, it will be recalled that the RDS coders available on the market, as represented in FIG. 1, make it possible to exploit the possibilities of the system more or less completely by means of a fairly heavy human-machine interface. This type of encoder comprises connected in cascade, as defined by the aforementioned European standard, a source of broadcast data messages, a differential encoder, a two-phase symbol generator successively constituted by an NRZ converter, a subtractor circuit whose subtraction channel comprises a delay circuit, and by a shaping filter and an amplitude modulator such as a suppressed carrier modulator delivering the amplitude modulated subcarrier to a multiplexer attacking the frequency modulated transmitter.

 A reference constituted by a pilot signal at 19 kHz is delivered by the stereo encoder of the transmitting station to an oscillator delivering the subcarrier at frequency fsp, generally equal to 57 kHz, to the suppressed carrier modulator, this same sub- carrier being frequency divided to deliver a clock signal of 2,375 Hz to the two-phase symbol generator and 1,187.5 Hz to the differential encoder and the source of the broadcast data message.

The present invention relates to the implementation of an encoder-generator of identification signals
RDS for radio broadcasting station with a significantly simplified structure and implementation.

 Another object of the present invention is the implementation of a coder-generator of RDS identification signals conforming to the aforementioned European standard and the broadcast information of which includes at least one code identifying the transmitting station, called the PI code. , a code delivering in clear the designation of the transmitting station, code PS, a code, code AF, designating in clear a list of alternative frequencies on which it is possible to receive the same program in the zones of coverage of stations of 'different show.

The coder-generator of identification signals
RDS in the form of an RDS message modulated on a transmission subcarrier for a mono or stereo radio transmission station object of the present invention is remarkable in that it includes generator circuits, in the form of digital data, from parameters of the radio transmission station, of identification information to be broadcast periodically and intended to constitute RDS messages, and digital / analog conversion circuits sequentially receiving, according to a determined law, the information to be broadcast and delivering a analog signal filtered on the transmission subcarrier frequency. A multiplexing circuit makes it possible to multiplex the audio-multiplexed signal and the filtered analog signal.

The coder-generator of identification signals
RDS object of the present invention finds application to the equipment of mono and / or stereophonic radio transmission stations.

The coder-generator object of the present invention will be better understood on reading the description and the observation of the drawings below in which, in addition to FIG. 1 relating to the prior art, - FIG. 2 represents a general diagram of the encoder
RDS identification signal generator conforming to
the object of the present invention, FIG. 3a represents the general flow diagram of a program making it possible to generate the digital information intended to be broadcast in the form of an RDS message, FIG. 3 b represents a variant of the general flow diagram of the figure 3a in which a digital modulation of the signal is carried out, FIG. 3c represents, in a synoptic manner, an embodiment of differential coding and of addition of a group in the sequence of the groups of the RDS message, FIG. 4 represents a block diagram of a coder-generator object of the present invention in an industrially optimized embodiment, that is to say structurally simplified, FIG. 5a represents an alternative embodiment of the coder-generator object of the invention in which an analog modulator with suppressed carrier is used to generate the subcarrier modulated by the message
FIG. 5b represents an alternative embodiment of the coder-generator object of the invention in which a logic modulator is used, the digital data intended to form the RDS message being processed by said logic modulator before their digital / analog conversion, FIG. 5c represents the frequency diagrams obtained in a particular embodiment of sampling with a view to digital type modulation making it possible then to generate the subcarrier modulated by the RDS message, FIG. 6 represents a detail of embodiment nonlimiting of a synchronization circuit usable in the embodiment of the coder object of the invention represented in FIG. 4 and following, FIG. 7 represents a detail of nonlimiting embodiment of a logic circuit making it possible from the signal reference clock to perform a reading
sequential data memory, this logic circuit
being more particularly used in the mode of
realization of the coder object of the invention represented in
Figure 4 and following.

The coder-generator of identification signals
RDS, object of the present invention, will first be described in conjunction with FIG. 2.

 Note that in all of the drawings appended to this description, the same references designate the same elements.

 First of all, the essential elements of the RDS identification messages will be recalled as described by the European standard previously cited in the description.

 In general, an RDS message comprises a PI code of the transmitting station, this code generally being an encrypted code coded on 4 hexadecimal characters, making it possible to uniquely identify either a transmitting station or a RDS network, a PS designation code for the station, this code consisting of an identifier displayed in clear on any receiver equipped with an RDS reception system, and, if applicable, a list of alternative frequencies, denoted AF, on which it is possible to receive the same program in different coverage areas.

 All the aforementioned information constituting the attributes of a station are contained in groups of type "O", these groups being therefore a priori the only ones broadcast, other groups being able however to be broadcast insofar as the information contained in these groups are frozen.

 It will be noted that the sequence constituting the identification signals carrying the RDS message is divided into Ng group, this number of groups being at least equal to 4.

 As will be observed in FIG. 2 above, the coder-generator of RDS identification signals, object of the present invention, comprises a generator circuit, denoted 1, in the form of digital data, of identification information. to broadcast periodically intended to constitute the RDS message. The identification information to be disseminated is produced in the form of digital data. In addition, the coder-generator according to the invention comprises a digital / analog conversion circuit, denoted 2, receiving the aforementioned digital data, this data being delivered to the digital / analog conversion circuit 2 sequentially, according to a determined law. The digital / analog conversion circuit 2 delivers an analog signal, denoted sa in FIG. 2. A filtering circuit 3 is provided, which delivers from the analog signal, sa, a filtered analog signal, saf, the filtering being carried out on the central frequency of the transmitting subcarrier, ie at the frequency fsp = 57 kHz.

 Finally, a multiplexing circuit is also provided for the audio-multiplexed signal and the filtered analog signal saf, the multiplexing circuit, denoted 4, being able to consist of an adder amplifier delivering at its output a multiplex signal to which the filtered analog signal has been added. saf constituting the RDS message.

 As has also been shown in FIG. 2, the circuits 1 generating identification information to be broadcast in the form of digital data may advantageously include a calculation processor 10 and a memory 100 of program for calculating and storing the digital data.

 In a nonlimiting manner, it will be understood that the memory 100 can be constituted by a RAM type RAM, of which a first part, 1100, receives in operation the above-mentioned calculation program, and of which a second part, 1110, allows storage digital data intended to constitute the RDS message.

 It will be noted that in a nonlimiting manner, the calculation processor can be constituted in a simplest embodiment by a processor of the 8086 type marketed by the company INTEL, the memory 11 being constituted by a memory of size 64 kb, for example . It will of course be noted that, to the calculation processor, peripheral elements can advantageously be added such as, for example, an alpha-numeric data input keyboard in order to allow a user to enter the identification parameters of the station. corresponding program.

 A detailed description of a particularly advantageous embodiment of the calculation program stored in the random access memory 100, this calculation program making it possible to develop the digital data intended to constitute the RDS message, will be given in connection with FIG. 3a.

 According to the aforementioned figure, the calculation program advantageously comprises a step 1000 of start or initialization, which comprises at least one routine making it possible to establish an interactive dialogue between the calculation processor 10 and the user, so that the latter can enter the appropriate parameters of the transmitting station.

 Following the aforementioned start step 1000, the program includes a subroutine 1001 for inputting the parameters of the transmitting station, this input being advantageously possible by means of the keyboard associated with the aforementioned calculation processor. In addition, a subroutine 1002 for calculating the flow of digital data is provided, this subroutine being intended to constitute the RDS message itself.

 The aforementioned subroutine 1002 is followed by a differential coding subroutine 1003, the latter subroutine forming a loopback with a loopback validity test program 1004 and an addition subroutine 1005 in the flow of digital data of an RDS data group, as will be described in more detail later in the description. The validity test program 1004 is followed by a two-phase coding subroutine 1006, following a positive response to the aforementioned test program 1004, then by a subroutine, denoted 1007a, 1007b, of corrective filtering and setting in the form of the data delivered by the two-phase coding subroutine 1006.

 The two routines 1007a, 1007b, constituting the previously mentioned filtering subroutine are followed by a subroutine for creating a digital data file to be broadcast, denoted 1008, this latter subroutine allowing the storage of the digital data to be broadcast at the level, for example, of the random access memory or of the part 1110 thereof.

 In an alternative embodiment of the flowchart previously described, a step 1006a of digital modulation of the signal is provided, see FIG. 3b. This modulation step, which will be described later in the description, can also be provided downstream of the filtering steps 1007a and 1007b previously described.

 By way of nonlimiting example, the subroutine 1002 for calculating digital flow data comprises a routine for determining and constituting the number of groups necessary for coding the alternative frequencies AF on which it is possible to receive the same program in different coverage areas. This routine delivers the resulting RDS digital data stream. It will be noted that the determination of the RDS groups by the aforementioned routine is carried out with calculation of the control word and of offset for each block.

The resulting bit stream is coded according to a differential coding verifying the relation
Xngi = bngi (+) Xngi-1, (+) = OU-Exclusive.

In the above-mentioned relation, it will be noted that for a group of order ng given, this group consisting of a determined number of bits constituting several words, each bit of value bngi, where i denotes the rank of the bit in the group and ng denotes the rank of the group in the set of groups considered, is coded by the operation
OR-Exclusive with the coded value obtained by previous differential coding Xngi-1 to give the coded value obtained by current differential coding Xngi. Of course, the coding is carried out by taking an arbitrary starting value, this value being denoted Uo in FIG. 3c.

Because of this coding, the coded value, that is to say the value of a bit obtained after coding, depends on the previous value and the loopback reacts on the value of all the bits so that the sub -program adds, if necessary, a group allowing correct looping.

The flow diagram of the group addition routine is as follows - the value of each bit depends on the previous one, so the
value of a sequence depends on that of the last bit of
the previous sequence; if it is reversed, any
the sequence is reversed.

- The RDS sequence is divided into Ng groups, at least 4
groups are required, and for each index group
ng = k, the calculation is only performed from the value
Uk of the last bit after coding, ie Uk = Xngk.

The looping procedure as represented in FIG. 3a by steps 1003, 1004, 1005 and return then consists, as represented in FIG. 3c, in searching among the existing groups, that is to say all the groups of index ng = k, of that of the groups which, added at the end of the sequence, will ensure the condition
UNg + l = Uo, where Uo is the entered arbitrary starting value corresponding to a coded bit value.

- the corresponding algorithm, that is to say the algorithm of
test, is expressed as follows: research and
memorization of the value k of the index group ng = k such
that - Uk-l = UNg AND Uk = Uo,
or - Uk-l = UNg * AND Uk = Uo *
relation in which * corresponds to the binary complement
of the value of the coded bit considered.

It will be noted that the aforementioned test is carried out on one or the other relation previously indicated, a positive response to the aforementioned test allowing the call of the subroutine 1006, that is to say the continuation of the progress of the program , while a negative response to the same test represented in FIG. 3c makes it possible to call the group addition subroutine 1005, which allows the creation of an additional group represented symbolically by the relation
Ng = Ng + 1, then the return to the initial phase of the test, i.e. research among the existing groups of the one added at the end of the sequence makes it possible to ensure the relationship
UNg + 1 = Uo, where Uo is the arbitrary starting value among all the groups increased by the added group. Note that after adding a group, that is to say after running the subroutine according to the loop represented in figure 3c, the response to the test represented on this same figure is necessarily positive, and the subroutine can then calculate the memory size necessary according to the number of groups effectively retained equal to Ng + 1 and the structure retained .

 Following the operations previously described, the subroutine 1006 makes it possible to perform biphase coding.

The biphase coding is carried out according to a conventional method, and, as such, will not be described, as known to those skilled in the art. Note, however, that while the previous differential coding operations were carried out at the bit frequency, that is to say at the frequency of the RDS bit stream, the two-phase coding operation is carried out at an arbitrary frequency, this frequency being preferably chosen equal to the clock frequency fe or sampling frequency.

 The aforementioned biphase coding subroutine 1006 is then followed by a corrective filtering subroutine 1007a, and a formatting filtering subroutine 1007b, which include corresponding filtering routines defined in frequency, either from templates, amplitude-frequency for example.

These routines are followed by a transform routine of
Fast Fourier calculating the resulting impulse response. The actual filtering is thus carried out by convolution on the looped signal, that is to say on the signal obtained by biphase coding, and the result, constituting the digital data intended to constitute the RDS message, can then be constituted in the form file, by means of a corresponding subroutine 1008, which then makes it possible to store the aforementioned digital values in a memory or part of random access memory 111 playing the role of buffer memory for example.

This memory is used to power the digital / analog converter 2. The above-mentioned subroutine 1008 is followed by an end program 1009.

 The embodiment previously described in connection with FIG. 2 is particularly advantageous insofar as this allows a very great versatility in use, the coding of the RDS messages being able to be carried out instantaneously or being able to be modified as desired. user.

 Another embodiment of the coder-generator object of the invention having a simplified structure compared to the embodiment of Figure 2 and whose application can be advantageously reserved for applications mainly consumer will be described in connection with Figure 4.

 In the aforementioned embodiment, it will be noted that the degree of simplification obtained allows an optimization of the structure of the corresponding coder-generator, which allows, of course, a very significant reduction in the costs of implementation and implementation, and which thereby authorizes consumer applications.

 In the embodiment of FIG. 4, the circuit 1 generating identification information to be broadcast in the form of digital data advantageously comprises a synchronization circuit 11 making it possible to deliver a reference clock signal, denoted CLK, this signal d the clock being, of course, a signal at the sampling frequency fe.

 In addition, the coder-generator as shown in FIG. 4 according to the object of the invention comprises a storage circuit 12 of programmable read-only memory type, PROM, this storage circuit making it possible to store the information to be broadcast after loading thereof, this information being constituted by the digitized data obtained by means of the coder-generator 1 represented in FIG. 2, the data stored in the part 1110 of the random access memory in the case of FIG. 2 being, on the contrary, loaded in the programmable memory 12, which can then be permanently installed for a station for transmitting corresponding attributes.

 In addition, as shown in FIG. 4, a logic circuit 13 makes it possible, from the reference clock signal CLK, to carry out a sequential reading of the storage circuit 12, which delivers to the digital / analog conversion circuit 2, the identification information to be broadcast intended to constitute the RDS message.

 Thus, for a given transmitting station, the attributes of the latter having been defined by the user, the PROM memory 12 can then be loaded or programmed by the system manufacturer in accordance with the operating mode described in conjunction with FIG. 2 , the memory 12 PROM then being installed on the coder-generator as shown in FIG. 4.

 In general, it will be understood that the coder-generator object of the present invention further comprises a system for generating a signal corresponding to the amplitude modulated subcarrier, in order to constitute the RDS signal in its entirety. . In all of the figures, and in particular the figures below, 5a, 5b, and in accordance with the embodiment, either of FIG. 2 or of FIG. 4, the system previously mentioned bears the reference 20, 21 or 121 .

 In particular, as shown in FIG. 5a, the system making it possible to generate the signal corresponding to the amplitude modulated subcarrier carries the reference 20 and can advantageously be constituted by an analog modulator, a balanced modulator, for example, interconnects by digital / analog conversion circuit 2 output. Of course, the analog modulator 20 receives the subcarrier signal at frequency fsp, and the signal delivered by the digital / analog conversion circuit 2 and delivers the amplitude modulated subcarrier, which, after filtering by the filter 3 centered on the frequency of the sub-carrier fsp, delivers the amplitude-modulated component of the RDS signal to the amplifier-summator 4.

 Of course, the amplitude modulator 20 as shown in Figure 5a, can be used in the embodiment as shown in Figure 2 without any disadvantage. It will also be noted that, in general, the suppressed carrier amplitude modulation carried out by the balanced modulator 20 has the effect of moving the initial spectrum in baseband around the subcarrier frequency fsp.

 In addition, in accordance with a particularly advantageous aspect of the coder-generator which is the subject of the present invention, and in order to avoid carrying out the modulation function in analog technique, as shown for example in FIG. 5b, such a technique being able to prove to be delicate. as regards, on the one hand its implementation and, on the other hand, if good stable performance over time is sought at low cost, a modulation technique corresponding in fact to a logical modulation can be envisaged in particular in accordance with FIG. 5b, and following.

 In accordance with FIG. 5b above, the system making it possible to generate the signal corresponding to the amplitude modulated subcarrier is formed by a plurality of logic gates of the OU-Exclusive type, a logic gate of the OU-Exclusive type denoted 21i being inserted on each digital / analog conversion circuit input 2.

As shown in Figure 5b, each door
OU-Exclusive 21i has one of its inputs connected to a data bus and in particular to the conductor of rank i of the same bus delivering the data coded on N bits, while the second input of the same OR-Exclusive gate 21i is connected to a periodic signal at the modulation frequency fmod, this modulation frequency being equal, in the case of FIG. 5b, to the subcarrier frequency fsp.

It will be noted that in the case where the digitized data is coded on 8 bits, the logic modulation circuit 21 comprises as many OR-Exclusive gates as described above, whereas in the case where these values are signed values, and that the digital / analog conversion circuit 2 includes a sign bit, circuit 21 can advantageously be replaced by a single door
OR-Exclusive interposed so as to modulate the aforementioned sign bit.

 It will of course be noted that the embodiment of FIG. 5b can be used without drawback, either in the embodiment of FIG. 2 of the coder-generator object of the present invention, or in the embodiment as shown in FIG. 4.

In addition, and in order to avoid the introduction of either an analog modulator or a logic modulator, as shown in FIGS. 5a and 5b respectively, and in accordance with a particularly advantageous aspect of the coder-generator object of the present invention, it is possible to realize the system making it possible to generate a signal corresponding to the subcarrier by an oversampling of the stored values of the bit stream
RDS, oversampling being performed in a report
K, the bit stream being subjected to sampling at a sampling frequency fe, as will be described below. In such a case, it will of course be understood that the values resulting from biphase coding, digitized values, are subjected to a bit level product, by the value + 1, at a relative modulation frequency equal to the sampling frequency fe = 2.fsp where fsp denotes the frequency of the subcarrier. By relative modulation is meant the fact that, each bit in the RDS bit stream, after coding, having a given value 0 or 1, this value, normally transmitted at the bit frequency, is previously subjected to a multiplication according to a number of chosen gives values equal to + 1 at the sampling frequency fe, i.e. in the case described above, fe = 2.fsp. Thus, for a bit value, and for each of the bits considered, after biphase coding, we obtain in does 1 / fie, i.e. 1 / 2.fsp, corresponding signed alternative values. The relative modulation performed by oversampling, as described above, is justified in the following way: although the condition fe = 2.fsp does not respect the Shannon condition, such an operating mode works perfectly because, then, the original spectrum and its second replica overlap exactly and therefore do not cause alteration of the useful signal by aliasing the spectra. The aforementioned operating mode makes it possible to significantly reduce the memory space required to store the values thus modulated, the values thus modulated being of course stored at the level either of the part 1110 of the memory 100 of the embodiment of FIG. 2, or at the level of the memory 12 of the embodiment of FIG. 4. The synthesis of the sampling frequency fe remains very simple, this being equal to twice the value of the frequency of the subcarrier.

 In addition, the system 121 making it possible to generate the signal corresponding to the subcarrier can be constituted by the values of the bit stream RDS, the values resulting from the biphase coding being subjected to a product at bit level by the value + 1 to a relative modulation frequency fmod taken equal to fsp / 3, one third of the frequency of the subcarrier fsp.

Indeed, if the sampling frequency fe, that is to say the clock frequency CLK, is a submultiple of the subcarrier frequency fsp, the transposed spectrum is in fact directly obtained after digital / analog conversion by bandpass filtering, as shown in point I of Figure 5c. This sampling frequency fe must be between the maximum frequency of the baseband spectrum, fmaxt, ie 2.4 kHz, and the frequency of the subcarrier fsp according to the formula:
fmax * 2 ç fe ç fsp, and
n * fe = fsp, with n integer.

 The higher the sampling frequency, or clock frequency, CLK, and the easier the bandpass filtering will be, but the more memory space necessary for memorizing the corresponding digitized values, which then constitute the system making it possible to generate the signal corresponding to the subcarrier will be important.

 In practice, the digital / analog conversion operation, which includes a holding operation for the duration of the sampling period, performs amplitude filtering of the form sin (X) / X called "cardinal sine". Such a filtering function includes transmission zeros for all the multiples of the sampling frequency fe, or frequency of the clock signal CLK, which strongly alters the replicas of the spectrum, as shown in point II of FIG. 5c.

 In accordance with the embodiment of the oversampling of the present invention, this then consists in taking into account the frequency response of the digital / analog converter 2, by placing itself at a favorable location on the spectrum, that is to say at maximum of the secondary lobe of the aforementioned cardinal sinus function.

 The relative modulation operation is then carried out by calculation with a sampling frequency fe double the modulation frequency as in the preceding case, but the modulation frequency fmod is taken equal to fsp / 3 as represented in point III of Figure 5c. The original spectrum of the signal is therefore not recovered, but its second replica, that is to say the replica transmitted by the secondary lobe of the cardinal sinus function. As shown in point III of FIG. 5c, the response around the frequency of the sub-carrier fsp, that is to say corresponding to the secondary lobe of the cardinal sinus, is taken into account to perform a pre-correction around of the modulation frequency fmod.

Downstream of the digital / analog conversion circuit 2, the elimination of the first spectrum can also be carried out by filtering, the first spectrum being situated only at 9.5 dB above the useful spectrum, center on fsp.

 The last two solutions proposed, the modulation operation being carried out in this case, as shown in block 1006a of FIG. 3b, in order to carry out the amplitude modulation of the subcarrier, make it possible to obtain a very simple structure for the coder-generator object of the invention, which then boils down to the elements represented, either in the embodiment of FIG. 2, or in the embodiment of FIG. 4, any physical modulator then being deleted.

 In order to send a continuous stream of RDS messages from the stored digital data, either to the part 1110 of the random access memory 100 of the embodiment of FIG. 2, or to the memory 12 of the programmable memory type of the embodiment of FIG. 4, the data then constituting a database for the transmitting station considered, it is necessary to ensure looping in reading of the corresponding memories.

 In the case of the embodiment of FIG. 2, the read loopback can be carried out by software, by means of a program of conventional type, which will not be described.

 In the case of the embodiment in FIG. 4, an address counter with test logic is preferably used, on the contrary, in order to carry out the above-mentioned looping.

 For this purpose, the circuit 13 forming the logic circuit of the embodiment of FIG. 4 allowing, from the reference clock signal CLK, to carry out a sequential reading of the memory circuit 12, can advantageously include, as shown in FIG. 7, a first counting circuit 130 on N bits, where N denotes the number of bits on which each word of the RDS message is coded, this first counting circuit being clocked at the frequency of the clock signal CLK. A second counting circuit 131 on N bits is coupled to a transfer output of the first counting circuit 130. The first and second counting circuits 130 and 131 deliver a 2N bit reading address to the programmable memory 12.

 In addition, a circuit 132 generating an end of file address on 2N bits is provided, this circuit 132 can be constituted for example by a battery of switches of the DIL type.

 A logic circuit 134 is provided, this circuit comprising on the one hand 2N Exclusive-OR gates 134i with two inputs. Each door of rank i comprises a first entry receiving the corresponding address bit at the end of file of rank i and a second entry receiving the address bit of rank i generated by the first and second counting means 130, 131. The logic circuit 134 comprises, on the other hand, an AND gate 1341 with 2N inputs, each input of rank i being connected to the output of the corresponding OR-Exclusive gate of rank i. Finally, the output of the AND gate 1341 is connected to a reset input, RESET, of the first and second counting circuits 130, 131. As regards the operation of the logic circuit 13 represented in FIG. 7, it will be understood that , for a given end-of-file address delivered by the circuit 132, reaching the aforementioned address delivered by the counting circuits 130 and 131 to the memory 12 and reading the corresponding successive addresses being thus carried out and the data digitized being read and transmitted for digital / analog conversion by the conversion circuit 2, the AND gate 1341 of the circuit 134 delivers a reset signal, which has the effect of resetting the first and second counting circuits 130, 131, which makes it possible to reset the counting via the clock signal CLK. The periodic reading of the memory 12 is thus carried out permanently.

 Finally, some indications will be given, on the one hand as regards an advantageous embodiment of the synchronization circuit 11, on the other hand as regards the dimensioning of the memory size necessary for the realization, namely of the random access memory 111 , or programmable memory 12, the latter being the most useful case.

 As shown in FIG. 6, the synchronization circuit 11 comprises an amplifier device 110 receiving the pilot frequency signal 19 kHz delivered by the stereo encoder of the transmitting station, as well as an autonomous system of the quartz oscillator type forming generator internal at 19 kHz, switching can be performed between one or the other signal. A bandpass filter 112 is provided, which delivers the filtered pilot signal, to a phase lock loop circuit, PLL, formed by a phase comparator 113, a loop filter 114, a summator 115, and a controlled oscillator. in voltage 116, with which a first divider 117 is associated, then at the loop output a second divider 118 delivering the clock signal CLK at the sampling frequency fe. It will be noted that the dividers inside the loop, 117 , and outside the loop, 118, make it possible to obtain the frequency of the clock signal CLK or sampling frequency fe.

With regard to the dimensioning of the memory making it possible to store the digitized data intended to constitute the RDS message, it will be noted that the size of the abovementioned memory is determined by the following parameters: - the sampling frequency fe, the number of bits NOT
to ensure quantification, that is to say the
number of bits making up each word of the RDS message, - the number of AF alternative frequencies to be broadcast.

 It will of course be noted that in the case of the embodiment of FIG. 2, the memory size of the calculation processor is generally sufficient to ensure the storage of the digitized data. Consequently, the problem of determining the required memory size does not arise directly, since the corresponding RAM sizes can easily reach 640 kb without difficulty, which is more than enough to ensure the storage of the most recent versions. developed from a microcomputer for example.

 In the case of the embodiment of FIG. 4 on the contrary, the modulation process can be carried out in digital form for example, according to the versions 1, 2 and 3 previously described in the description, according to the parameters below - Version 1 (logic OU-Exclusive): fe = 19 kHz, - Version 2: fe = 2.fsp = 114 kHz, fmod = fsp, - Version 3: fe = 2.fsp / 3 = 38 kHz, fmod = 19 kHz.

The number of quantization bits, that is to say of coding of the words of the RDS message, which does not in any way prejudge the precision of the filtering performed by calculation, determines the ratio signal to carrier frequency / quantization noise, expressed in dB, depending on the relationship
S / Bq = 6 * N + 1.76, where
N represents the number of quantization bits. The number of bits can advantageously be chosen equal to 6 or 8.

 The number of RDS groups to be broadcast is determined by the corresponding coding rules, either according to the number of alternative frequencies AF - 7 AF or less 4 groups, - 15 AF 8 groups, - 23 AF 12 groups.

Under these conditions, the memory size can be defined by the values in the table below.
Version AF number Number Memory size
N = 8 bits group zero k bytes 1: fe = 19 kHz 7 4 6.6
15 8 13.3
23 12 19.9 2: fe = 114 kHz 7 4 39.9
15 8 79.8
23 12 119.8 3: fe = 38 kHz 7 4 13.3
15 8 26.6
23 12 39.9
We have thus described a coder-generator of RDS identification signals which is particularly efficient, and particularly advantageous because of the simplicity of construction of the coder finally implemented. Such simplicity is due to the particular structure of it, but also to the process of processing the signals intended to produce and constitute the RDS messages to be broadcast periodically.

 It will be noted in particular that the coder-generator, object of the present invention, can only be summed up, in its simplest structure, with the embodiment of FIG. 2 or 4 in which both the differential coder and the biphase symbol generator , and that finally the carrier balance modulator deleted from the generator coders of the prior art, as shown in FIG. 1, are deleted.

 Finally, it will be noted that in the industrially optimized embodiment, as shown in FIG. 4, and in particular due to the choice of the sampling and relative modulation frequencies of the bit values of the bit stream RDS, the memory size of the programmable memory 12 required could be reduced to 39.9 kb for a particularly complete version of RDS systems in which 23 alternative frequencies are provided.

Claims (13)

 1) Coder-generator of identification signals RDS, in the form of an RDS message modulated on a transmission subcarrier for a mono- or stereophonic radio transmission station, characterized in that it comprises - generator means (1) in the form of data  numerical, from station parameters  radio broadcast, identification information  to broadcast periodically intended to constitute the  RDS message, - digital-analog conversion means (2) and  filtering (3) receiving sequentially, according to a law  determined, said identifying information to  broadcast and deliver a filtered analog signal on the  center frequency of the transmission subcarrier, means for multiplexing the audio-multiplexed signal and  filtered analog signal.  2) Encoder-generator according to claim 1,  characterized in that said means (1) for generating  identification information to be disseminated in the form of  digital data, comprising - a calculation processor (10), and, - a memory (11) of calculation and memorization program  tion of digital data.  3) Encoder-generator according to claim 2,  characterized in that said program memory of  calculation includes a stored calculation program, said calculation  program comprising - a subroutine (1001) for entering the parameters of the  transmitting station, - a subroutine (1002) for calculating the data flow  digital, intended to constitute the RDS message, - a subroutine (1003) of differential coding and,  forming a loop with said subroutine, a test  (1004) of loopback validity and a subroutine  (1005) of addition, in the digital data stream,  an RDS data group, - a two-phase coding subroutine (1006), - a corrective filtering subroutine (1007a, 1007b) and  formatting, - a subroutine for creating data files  digital to broadcast, allowing memorization  said digital data to be broadcast at said level  means of memorization.  4) Encoder-generator according to claim 3, characterized in that said differential coding subroutine and the corresponding loop comprising the subroutine for adding an RDS data group comprises from an arbitrary bit value starting Uo - a routine for determining the Uk value of the last  bit, after differential coding, of each RDS group  of order k, - a search routine, among the existing groups, of  the one which, added at the end of the starting RDS sequence  allows to reconstitute the arbitrary starting value Uo,  Ung + 1 = Uo.  5) Encoder-generator according to claim 3, characterized in that the bi-phase coding subroutine performs coding at the sampling frequency.  6) Encoder-generator according to claim 3, characterized in that the corrective filtering and shaping subroutine includes filtering routines, defined in frequency, followed by a fast Fourier transform routine calculating the impulse response , the result of the calculation constituting the digital data to be broadcast stored at the storage means.  7) Encoder-generator according to claim 1, characterized in that said generating means (1) of identification information to be broadcast, in the form of digital data, comprise - synchronization means (11) for delivering  a reference clock signal, - read-only memory type memory means (12)  programmable (PROM), said storage means  allowing the memorization of said  information to be broadcast, - logical means (13) allowing, from the signal  reference clock, take a reading  sequential of said storage means,  said storage means delivering to said means of  digital-analog conversion of said information  of identification to distribute.  8) Encoder-generator according to one of the preceding claims 1 to 4, characterized in that it further comprises means (20, 21, 121) making it possible to generate a signal corresponding to the subcarrier modulated in amplitude.  9) Encoder-generator according to claims 1 and 8, characterized in that said means (20) for generating the signal corresponding to the amplitude modulated subcarrier are formed by an analog modulator, interconnected at the output of the conversion means digital-analog.  10) Encoder-generator according to claims I and 8, characterized in that said means (21) making it possible to generate the signal corresponding to the amplitude modulated subcarrier are formed by a plurality of logic gates (21i) of the OR type -Exclusive, an OR-Exclusive type logic gate being inserted on each input of the digital-analog conversion means.  11) Encoder-generator according to claims 1 and 7 or 8, characterized in that said means (121) for generating the signal corresponding to the subcarrier are formed by the stored values of the RDS bit stream subjected to oversampling of ratio K, the values resulting from the biphase coding being subjected to a product at bit level by the value + 1 at a relative modulation frequency fmod = fsp, where fsp denotes the frequency of the subcarrier, the frequency of the signal CLK clock or sampling frequency, fe being equal to fe = 2.fmod = 2.fsp.  12) Encoder-generator according to revevdications 1 and 7 or 8, characterized in that said means (121) making it possible to generate the signal corresponding to the subcarrier are formed by the stored values of the bit stream RDS, the frequency d 'clock being a submultiple of the frequency of subcarrier fsp, the values resulting from the biphase coding being subjected to a product at the bit level by the value + 1 at a relative modulation frequency fmod taken equal to fsp, third of the subcarrier frequency, 3 the frequency of the clock signal CLK or sampling frequency fe being equal to fe = 2.fmod = 2.fsp.  3  13) Encoder-generator according to one of claims 7, 11 or 12, characterized in that said logic means allowing, from the reference clock signal to carry out a sequential reading of the storage means comprise - first means counting (130) on N bits where N  denotes the number of bits on which each word is coded  of the RDS message, these first counting means being  rates at the frequency of the clock signal, and - second counting means (131) on N coupled bits  to a postponement output of said first means of  counting; said first and second means of  count delivering a read address on 2N bits,  to said storage means, - means (132) generating an end of address  file, on 2N bits, - a logic circuit (134) comprising, on the one hand, 2N  Exclusive-OR doors (134i) with two inputs, each door of rank i comprising a first entry receiving the corresponding end of file address bit of rank i and a second entry receiving the address bit of rank i generated by the first and second counting means, and, on the other hand, an AND gate (1341) with 2N inputs, each input of rank i being connected to the output of the corresponding OR-Exclusive gate of rank i, the output of said gate AND being connected to a reset input of said first and second counting means.