FR2678401A1 - INFORMATION PROCESSING DEVICE MORE PARTICULARLY ADAPTED TO A CHAIN LANGUAGE, OF THE FORTH TYPE IN PARTICULAR. - Google Patents

Abstract

This information processing device more particularly suited to a chained computer language of the FORTH type in particular, comprises: a main memory (10) for containing an execution program with its instruction data constituted by a plurality of instructions directly or not directly executable which are grouped into at least one subroutine, - a first memory (30) of stack type to contain the address following the call address to a subroutine (return address), - one or several operation units (40) for executing the directly executable instructions, which may contain:. a second stack-type memory (20) for containing parameters used by said program,. an instruction decoding member (70) for decoding each instruction data item coming from the main memory. Application: information processing.

Description

"Information processing device more particularly adapted to

  a chained language, of the FORTH type in particular ".

Description

  The present invention relates to an information processing device more particularly adapted to a chained computer language of the FORTH type in particular, a device comprising among others: a main memory for containing an execution program with its instruction data constituted by a plurality of directly or indirectly executable instructions which are grouped into at least one subroutine, a first stack memory for containing the address following the subroutine call address (return address), one or more units of operation for executing directly executable instructions 1 each of which may include: a second stack memory for holding parameters used by said program, an instruction decoding device for decoding each

  instruction data from the main memory.

  Such a device is described in the document

  European patent published under number O 185 215.

  To design an execution program, the programmer, or the language compiler, must know the hardware resources with which the device works. Thus he must know if each instruction is a directly executable instruction or if one must connect to a sub-program. -program performing the function using directly executable instructions For example if a multiplier is provided in the environment of the device, the multiplication operation is directly executable and if this organ is absent must be connected to a multiplication subroutine which will perform it by additions and successive offsets This choice is fixed by means of a binary element incorporated in the instruction that the programmer positions to indicate that the instruction is directly or not directly executable. other words, one must compile with an indicator to provide either directly executable instructions or a call to a e

  library emulating the missing instruction.

  The fact that the user needs to know the

  resources is a first disadvantage.

  A second disadvantage that follows is that the established program can only work on the device with the environment for which the program was designed the addition of other hardware resources imposes a

  rewriting or recompiling the program.

  The invention proposes a device of the type mentioned in the preamble which avoids, to a large extent,

the aforementioned drawbacks.

  For this, such a device is remarkable in that it is provided with means for considering as subroutine addresses instructions that it can not execute directly. So the idea of the invention is to consider that any instruction data is a procedure address It

  There are therefore no more instructions in the true sense of the word.

  The following description with drawings

  annexed, all given as a non-restrictive example will be

  understand how the invention can be realized.

  Figure 1 shows the diagram of a first information processing device according to the invention. Figure 2 shows the data implementation

  instructions in the main memory.

  Figure 3 shows in more detail the decoding unit. FIG. 4 shows the diagram of another embodiment of an information processing device,

  including means for executing program loops.

  FIG. 5 shows in more detail the decoding unit that is suitable for the device of the invention shown in FIG.

Figure 4.

  Figure 6 shows the implementation in memory for

  running a program loop.

  The information processing device shown in FIG. 1 consists firstly of a main memory containing the instruction data. In FIG. 2, a series of such data showing, by way of example, is shown. a program P 4 calculating the fourth power of a number "a", that is to say calculating at 4 in FIG. 2, the item @ indicates the address and D the data present at this address. Thus the program P 4 is called at the address @APPEL and implies other subroutines which will be explained in detail in the remainder of this presentation. This instruction structure is specific to the so-called "linked" languages. The instructions that have been discussed, as well as that *, DUP are

  consistent with Forth notation.

  The device of FIG. 1 further comprises a first memory 20 of the stack type (last data input, first output data) intended to contain parameters and, in the example described, in particular the number has a second memory 30 also of type stack, is intended to contain the subroutine addresses and cooperates with an instruction data address register with the reference 32 Through a switch SW 1 the contents of the register 32 can be increased by one unit by means of an adder 34 or not, before being transmitted to another switch SW 2 whose output is in relation to the input of the memory 30 The last information input is set to the position marked by TOR while that the penultimate is marked by NOR A switch SW 3 selects the data contained in the position NOR or TOR before routing it towards

  the register 32 via another switch SW 4.

  In a similar manner, TOP and NOP were respectively marked last and last to the positions at which the parameters are selected. 40 is equipped with two (A is connected to the position 'input B is connected to the <inputs E1 and E2 Input I have stored in the memory positions SW 5 can stack in memory 20 These memory 10 The output of the switch SW 3 This operand inputs A and B The TOP input of the memory 20 while netting a SW switch with two E 1 is connected to the NOP position of the memory And the input E 2 is connected to the external port 50 via an input-output unit 55. This unit also provides output information, from the operation unit 40, to the 50 The switch SW 2 makes it possible to select, besides the data coming from the r 32, data from the output of the switch SW 3 and those contained at the TOP position of the memory 20 A switch SW 4 is used to load the register 32 data from either the memory 10 or data present at the output switch SW 3 and another switch SW 8 which preselects the data contained in the positions NOP and TOP

of memory 20.

  The different switches SW 1 to SW 6 and SW 8 are respectively provided with position commands KW 1 to KWG and

KW 8.

  The operation unit 40 is provided with a control input K which receives the control information of an instruction decoding unit 70 whose input DK is connected to the output of the memory 10 and supplies the different signals

  KW 1 to KW 6, KW 8 according to the instructions to be made.

  According to the invention, the instruction decoding unit is advantageously produced from an associative memory whose schematic diagram is

shown in Figure 3.

  This associative memory is constituted from a memory block 100 provided with an output 50 can provide a code, so that the operations to be performed by the unit 40 can take place However, the input code connected to the DK access is compared with all the execution codes that can be executed directly by the unit 40 All these execution codes are contained in registers R1 to RN and comparators C1 to CN compare with the contents of these registers and the input code present at the input DK A decoder 102 uses the results of these comparisons to generate the address of the memory 100, so that the latter delivers to the unit 40 the corresponding instruction A referenced OR gate 110, for example, collects the result of these comparisons If the input code is recognized, the output of the memory block is recognized and its code (or codes) output is (are) validated (s) and out (out) from block 100 to the K input of the unit 40 If the input code is not recognized, a non-operative code (nop) is then applied to the command K, the non-decoding address generates the nop The various information from the gate 110 and the output 50 of the memory 100 are applied to a switching control unit 120 which provides the signals

KW 1 to KW 6 and KW 8.

  The decoding of instructions can be done by

  any other method of decoding, programmable or not.

  The set R1 ,, RN, Cl ,, CN can be realized by any associative memory structure For the invention, the

  decoding method will be advantageously programmable.

  Indeed, for any modification of the material, it is enough to modify only the contents of the associative memory A program is thus composed: of a list of instructions', independent of the processor used (in the limit or this one has some common elementary instructions), and a table, loaded into the associative memory that reflects the characteristics of the machine This is advantageous when selling turnkey programs The modification of the material does not result in a recompilation of the application, but only the modification of the content of

  associative memory (a few bytes).

  The operation of the device of the invention is now explained in the context of the example program shown in FIG. 2, that is to say the setting to the power 4

of a number "a", to be evaluated at 4.

  Firstly, the basic operation of the device of the invention is explained. By default, the device considers that any data output from (10) is a subroutine call address. The basic operations are as follows: in the operations explained below, (32) indicates the contents of the register 32, l @ (32) llo indicates the contents of the memory 10 at the address indicated by the content.

from the register 32.

  (32) + 1 TOR: stack the following address l @ (32) llo: is analyzed by 70 to determine if it is an instruction or a subroutine call. If it is a subroutine call (not recognized by associative memory as an instruction executable by the hardware): l @ (32) llo 32 and the cycle starts again If it is an instruction, it can have two forms

return or no return.

  non-return form: the operations are executed in sequence l @ (32) lil is executed by the unit 40 TOR c 32 the register 32 is loaded with the address of

  of the following instruction (we unpile a single data).

  return form: in this case, you perform at the same time as

  the coded operation, a subroutine return.

l @ (32) llo is executed by 40

  NOR 32: unstacking of two data in the memory 30.

  We return to the call address of the subroutine.

  We will see this mechanism as part of the program

example.

  Further information can be found in

Appendix I of this memo.

  It is assumed that initially the contents of the register 32 are CALL-2, which is an address code denoted @ CALL-2 for an instruction datum contained in the memory 10. At this address a symbol, for example CONST, means that the following data is a constant and that it must be stored at the

  TOP position within the memory 20.

  The steps of operation are explained below by comments on steps of

  described in more detail in Appendix II.

  No progress Comments 1 The value @ CALL-2 incremented by one unit is transferred to the digital position of the memory 30 Then a stacking is carried out at the TOR position, we have the

code lAPPEL-1 i.

  2 The contents of memory 10 at @ APPEL-2 is

  analyzed as the prerequisite of a constant.

  The value EAPPEL-1 now points to the value "a" contained in the memory 10. An unstacking is then performed. 4 The value @ CALL-1 incremented by one unit is

  transferred to the digital position of the memory 30 (stacking).

  The constant "a" is set to the TOP position of the memory 20 (the previous step 2 has switched the

SW switches 3).

  6 The content of the register 32 is @APPEL which corresponds to the execution of the fourth power of "a", the content code corresponds to an address of

  subroutine @P 4 (continuous primitive).

  7 The @APPEL address, incremented by one unit, is set

at the TOR position.

  8 The contents of the memory 10 at the address @APPEL are analyzed; since this code is not recognized as directly executable, it is considered to be an address.

  9 The address @P 4 is set in the register 32.

  The incremented @P 4 address of one unit is stacked.

  The contents of memory 10 at address @P 4 are

analyzed as an address.

  The @ square address is set in the register 32.

  13 The @ square address, incremented by one unit, is stacked. The DUP instruction is analyzed.

  primitive This statement is executed.

We go on to the next instruction.

  The return address is stacked in the memory 10.

  17 The examination of instruction involves a sub-program. The address of this routine is set in the register 32 so that at the output of the memory 10 there is

  the first INM instruction 1 multiplication.

  The execution of the multiplication is carried out by means of successive additions and decodings according to the manners

well known to those skilled in the art.

  Then we come to the instruction of the form of return.

This form is examined.

  After 2 depilages, the return of the

subroutine.

  22 The IR return instruction is made available.

23 She is examined.

  26 The nested subprogram is used.

It starts with the DUP instruction.

  The program then continues as from step 13

  and following until the call of a new square.

  28 So we find the return of subroutine.

  29 Examination of instruction, return of subprogram.

Two elements are removed.

  31 Then we get the return instruction 32 and we proceed to its examination

33 Continuation of the program.

The program ends up unfolding.

  It should be noted that each instruction consists of the following cycles: (32) + 1 - + TOR which is a stacking cycle of the contents of the

register 31 increased by one unit.

  l @ (32) llo which is the examination and analysis of instruction.

  Then connecting and loading a new

value in the register 32.

  For this, we distinguish three cases a) l @ (32) lla defines a subprogram call b) (TOR) 32 implies the execution in sequence of

  the next statement with unstacking.

  c) (NOR) 32 relating to the subroutine return with an unstacking of two elements of the return memory 30. Other operations can be performed by the device of the invention shown in FIG. 1 This is shown in FIG. Appendix I. The operation of a device having means for executing a minimum of instructions is explained here. It should then be noted that the program presented here, with the same instructions, can be executed with a device in accordance with FIG. invention and having additional means; for example, the operation unit 40 may comprise means enabling it to

to perform multiplications.

  The program will then be executed in the following way: 1 to 16 identical 17 l @ (32) llo is then analyzed as a directly executable instruction, the symbol n * n is not considered as an address, the operation

is executed.

  The code of the application remains unchanged, only the contents of the instruction decoder 70 are modified when a hardware resource is added to the device (in

  this case a cable multiplier).

  In Figure 4, there is shown another variant

  embodiment of another device according to the invention.

  In this figure, the elements common to those of Figure 1 bear the same references This device of Figure 4 is provided with means that allow it to perform program loops. This device of FIG. 4 differs from that of FIG. 1, first of all in that the inputs of the adder 34 are connected to the outputs of two switches SW 10 and SW 12. The switch SW 10 is provided with four inputs which receive the signals representing the numbers + 1, 0, 1 and the contents of the memory 20 defined by the position TOP respectively The switch SW 12 is provided with two inputs The first is connected to the output of the register 32 and the second, at the output of an index register whose input is in relation with the digital position of the

memory-stack 30.

  The device of FIG. 4 differs from that of FIG. 1, in addition, in that a code comparator 155 is provided. Its inputs are related to the NOR and TOR positions of the memory 30 and its output. at the input of the instruction decoding unit 70 This unit will provide the control signals KW 10 and KW 12 towards the

  switches SW 10 and SW 12 respectively.

  The unit 70 of FIG. 4 is shown in more detail in FIG. 5. The signal coming from the comparator 155 is

  applied to the switching control unit 120.

  The loop index is in TOR, the loop limit in NOR (loaded by 2 instructions> R), so we have a memory layout as shown in FIG. 6, in which LIM is the loopback limit and INDX the initialization of register 150, LIM and INDX being announced

by CONST.

  A program loop is then performed as follows, when the loop limit in NOR is set, the loop index

(32) + 1 C

l @ (32) l 10 (TOR)

(TOR) -

(150) + 1

  in TOR TOR TOR) R:: Stacking of (32) + 1 connection address

: The "loop" instruction is de-

  : Discrete unloading: Unstacking of the loop index: Incrementation of 1 of the inde, loop tapped x of or (150) + (TOP) Discrete: Incrementation of the index of loop

of the value contained in TOP.

  Note: TOR must not be removed

during this operation.

  l (155) l: One tests the equality of the contents in the NOR and TOR locations If there is equality (32) + 1 TOR: End of the loop (one skips the address of connection) (TOR) 32: instruction next otherwise (32) -1 - + TOR: we restore the address of the instruction of "loop" 32: call of the subrogramme l (32) llo - + At the exit, it is necessary to transfer TOR and NOR in NOP

and TOP to be able to erase them.

  A loop instruction behaves as follows: "limit", "index", "> R", "> R", "Loop", "<call address>",

"R>", "R>", "DROP", "DROP".

A N N E X E I

  Executable instructions In what follows PC represents the contents of the

register 32.

  The normal cycle is PC + 1 TOR with stacking in (30) see figure 1 By default any data output from the memory 10

  is considered a subroutine address.

  NORMAL (subroutine call): Basic instruction if discrete 4 PC unstacking of 1 element in memory (30) if NOR 4 PC unstacking of 2 elements in (30) 1 PC + 1 TOR (stacking)

  2 M (PC) analyzed as NORMAL by the decoder 70.

3M (PC) * PC

PRIMITIVE RETURN:

  Basic instruction recognized by the operation unit

  with subroutine return included in the instruction.

  1 PC + 1 + TOR (stacking) 2 M (PC) analyzed as PRIMITIVE RETURN 3 NOR 4 PC (unstacking of 2 elements)

PRIMITIVE CONTINUES:

  Elementary instruction The statement executed after is

the following instruction in memory.

  1 PC + 1 TOR (stacking) 2 M (PC analyzed as PRIMITIVE CONTINUOUS 3 TOR-PC (unstacking) CONSTANT (the value of the constant is just after): 1 PC + 1-TOR (stacking) 2 M (PC) analyzed as CONSTANT, the next instruction

will be forced as primitive.

  3 TOR 4 PC (unstacking) 4 PC + 1 ITOR (stacking)

M (PC) -TOP

  6 TOR or NOR + PC (if CONSTANT RETURN or CONTINUE),

(unstacking 1 or 2).

  TEST: Several options are possible: choice TOR or NOR (form BACK or CONTINUE) to inhibit the + 1 during the second phase of reading,

  choice M (PC) or TOR in the second reading phase.

  We will see some possible options: 1 PC + 1 * TOR (stacking) 2 M (PC) analyzed as BACK CONDITIONAL 3 TOR or NOR 4 PC according to condition (unstacking 1 or 2) or again: 1 PC + 1 VTOR (stacking) 2M (PC) analised as IF 3 TOR 4 PC (unstacking) 4 PC + 1-TOR (stacking) 5 TOR 4 PC (unstacking) (no jumping) or M (PC) 4 PC (jumping) to subroutine or else 1 PC + 1-TOR (stacking) 2 M (PC) analyzed as IF 3 TOR + PC (unstacking) 4 TOR PC (return) or M (PC) 4 PC (jump) (no return) FETCH or STORE IMMEDIATE: The data is in TOP and the address is in the program code. 1 PC + 1-TOR (stacking) 2 M (PC) analyzed in FETCH or STORE IMMEDIATE 3 TOR> PC (unstacking) 4 PC + 1-TOR (stacking)

M (PC) - PC +

  6 M (PC) -TOP (following fetch or store) 7 TOR or NOR-PC (return or continuous form of the instruction), (1 or 2 unstacking) FETCE or STORE: Here the address is in TOP and the data (in STORE) is in

NOP.

  1 PC + 1 TOR (stacking) 2M (PC) analyzed in FETCH or STORE 3 TOP-PC (unstacking) 4M (PC) -TOP (following fetch or blind) 5 TOR or NOR- + PC (return or continuous form) of the instruction) R> or> R: Data exchange between parameter stack (20) and stack of

back (30).

  R> transfer from the top of the return stack (30) to the

top of the stack (20).

  > R transfer from the top of the stack (20) to the top of the

stack of retou (30).

  1 PC + 14 TOR (stacking) 2 M (PC) analyzed in R> or> R 3 TOR-PC (unstacking) 4 TOR-TOP (following> R or R>)

ANNEX II

  Execution of the sample program Step Instruction (32) l @ (32) lol Return stack Prg

(32) + 14 TOR

l @ (32) l 10

(TOR) - + 32

(32) + 14 TOR

l @ (32) l 1 o-TOP

(TOR) 432

(32) + 1- + TOR

l @ (32) l 10 l l 8 (32) l 10 * 32

@ CALL-2

_APPEL-1

@ APPEL-1

@CALL

@CALL

  @P 4 CONST aa @P 4 @P 4 @ square l @ CALL-1 ll @ CALL-1 lSAPPELl l @ CALL + 1 l (32) + 1-TOR @P 4 @ square l @ P 4 + 1 llSAPPEL + 1 l 11 l @ (32) l 1 io @ P 4 @ square 12 l 8 (32) l 10 o-32 @ square DUP l @ P 4 + 1 ll @ CALL + 11 13 (32) + 14 TOR @ square DUP l @ square + lll @ P 4 + 1 ll @ CALL + 1 l 14 l @ (32) l 1 o @ square DUP (TOR) 432 @ square @ * l @ P 4 + 1 llSAPPEL + 1 l 16 (32) + 1- TOR8 square + 1 @ * l @ square + 2 ll @ P 4 + 1 ll @ CALL + 1 l 17 l @ (32) l 10 @ square + 1 @ * 18 l 8 (32) l 1 o- + 32 @ * INM 1 l @ square + 2 ll @ P 4 + 1 ll @ CALL + 1 l Execution of multiplication by addition and shift j

19 (32) + 1-TOR

l @ (32) l 1 o

21 (NOR) 432

22 (32) + 1 TOR

23 l @ (32) l O

24 (NOR) -32

(32) + 1 TOR

  26 l @ (32) l 10 @ square + 2 @ square + 2

@P 4 + 1

@P 4 + 1

  IR @ square @ square l @ * F + 1 ll @ square + 1 ll @ P 4 + 1 ll @ CALL + 1 ll @ P 4 + 1 ll @ CALL + 1 ll @ square + 3 ll @ P 4 + 1 ll @ CALL + 1 11 @ CALL + 1 ll @ P 4 + 2 ll @ CALL + 1 l 27 l @ (32) l 1 o-32 @ square DUP l @ P 4 + 2 ll @ CALL + 1 l As not 13 and following 28 (32) + 14 TOP @ square + 2; l @ square + 3 ll @ P 4 + 2 l I I ll @ CALL + 1 l l @ (32) 1 Io

(NOR) - + 32

(32) + 14 TOR

l @ (32) l 1 o

(NOR) + 32

@P 4 + 2

@P 4 + 2

@ CALL + 1

  l @ CALL + I 1 l l @ P 4 + 3 ll @ CALL + 1 l

Claims (3)

Claim   1 device for processing information more particularly adapted to a computer language chained of the FORTH type in particular, device comprising inter alia a main memory for containing an execution program with its instruction data constituted by a plurality of instructions directly or not directly executable which are grouped into at least one subroutine, a first stack memory for containing the address following the subroutine call address (return address), one or more operation units for executing the directly executable instructions, which may contain a second stack memory for containing parameters used by said program, an instruction decoding device for decoding each instruction data from the main memory, characterized in that it is provided with means for considering as subprogram addresses the instructions that it does not can not run directly.   2 information processing device according to claim 1, characterized in that said means are constituted by the decoding member formed from a associative memory.   3 information processing device according to claim 1 or 2, characterized in that for performing program loops it comprises the following means: a register incrementer-decrementor for incrementing an index register, a decoder for decoding the end of the writing of the loop, coupled on the one hand to one of the stacks containing the loop limit and on the other hand to the index register, and to act on the instruction decoding member so as to   to ensure the proper execution of the loop.