FR2672759A1 - Image sensor with semiconductors, with charge storage - Google Patents

Abstract

An image sensor with semiconductors comprises a charge storage part which includes a first network of capacitors (14) intended for storing signal charges which are read in a pixels part (4), control means (16) intended to control the transfer of signal charges stored in the first network of capacitors, these control means being incorporated into a stage which is placed following the first network of capacitors (14), and a second network of capacitors (15) which is intended for storing the signal charges which are transferred by the control means. In this structure, charges which are stored by the first network of capacitors (14) during a horizontal period are read in the second network of capacitors (15) during the following horizontal period, which makes it possible to have sufficient time available for the storage of charges.

Description

 SEMICONDUCTOR IMAGE SENSOR ,.

LOAD STORAGE
The present invention relates to semiconductor image sensors, and it relates more particularly to a MOS type semiconductor image sensor.

 A semiconductor image sensor converts visible light or Invisible light such as infrared light, ultraviolet light, or X-rays, into electrical signals that represent an image of a material object, and the sensor is widely used in various fields, such as television cameras or for reading data in facsimile apparatuses. More particularly called MOS type semiconductor image sensor a semiconductor image sensor in which an element of conversion of light to electricity, which converts light signals into electrical signals, and a switching element which selectively reads the electrical signals from the light-to-electricity conversion element, are formed on a semiconductor substrate by the use of the technique of manufacturing complex MOS integrated circuits.

Figure 5 is a block diagram showing an image sensor
Prior art MOS infrared, which converts infrared light into electrical signals. In FIG. 5, the reference 1 designates a photodiode the anode of which is connected to ground. The photodiode 1 is connected to a vertical switching MOS transistor 2, by means of an indium bump 3. A pixel 4 comprises the photodiode 1, the vertical MOS transistor 2 and the indium bump 3. A network of pixels 5 comprises a set of pixels 4 arranged in the directions of the rows and columns, that is to say in a matrix. The reference 6 designates a horizontal switching MOS transistor. A network of horizontal MOS transistor transistors 7 comprises a set of horizontal MOS transistors 6 arranged in the direction of the columns. Grid signal conductors 81 to 8m are arranged in the corresponding lines and are connected to the pixel grid electrodes 4. Signal conductors 91 to 9n are arranged in the corresponding columns and are connected to the drain regions of pixels 4 and to the source regions of the horizontal MOS transistors 6. Gate signal conductors 101 to 10n are arranged in the corresponding columns and are connected to the gate electrodes of the horizontal MOS transistors. The drain regions of the horizontal MOS transistors 6 are connected to an image output 11. A vertical shift register 12 applies signals to the respective gate electrodes of the vertical MOS transistors 2 via the gate signal conductors 81 to 8m.

A horizontal shift register 13 applies signals to the respective gate electrodes of the horizontal MOS transistors 6 through the gate signal conductors 101 to 10n. The reference 20 designates a semiconductor chip in which the components described above, going from the photodiode 1 to the horizontal shift register 13, are formed on the same semiconductor substrate.

 FIG. 6 is a section showing the pixel and the horizontal MOS transistor which constitute the infrared image sensor of the MOS type of FIG. 5. In FIG. 6, the reference 21 designates a semiconductor substrate of p-type silicon. Field oxide layers 22 are disposed on a main surface of the p-type silicon substrate 21, to divide the surface of the substrate 21 into a set of regions consisting of islands. A source region of type n 23 and a drain region of type n 24 are arranged in an island, while a source region of type n + 25 and a drain region of type n 26 are arranged in l another island region. A gate oxide layer is formed between the source region 23 and the drain region 24, and a gate electrode 29 is formed on the gate oxide layer 27. A layer of gate oxide 28 is formed between the source region 25 and the drain region 26, and a gate electrode 30 is formed on the gate oxide layer 28. A vertical MOS transistor 2 includes the source and n-type drain 23 and 24, the gate oxide layer 27 and the gate electrode 29, while a horizontal MOS transistor 6 includes the n-type source and drain regions 25 and 26, the layer d gate oxide 28 and gate electrode 30.

 We will now describe the operation. When infrared light falling on the photodiode 1 is converted into electrical signals having an amount of charges proportional to the amount of infrared light, the vertical shift register 12 successively selects the gate signal conductors 81 to 8m. For example, when the gate signal conductor 81 is selected, a voltage of 10 V is applied to the gate electrode 29 of the vertical MOS transistor 2 which is connected to the gate signal conductor 81, and the threshold value is low, which causes the vertical MOS transistor 2 to be turned on. At this time, charges coming from photodiode 1 enter the vertical signal conductors 91 to 9n via the vertical MOS transistor 2.

 Then, the horizontal shift register 13 successively selects the vertical signal conductors 101 to IOn. When the vertical signal conductor 101 is selected, a voltage of 10 V is applied to the gate electrode 30 of the horizontal MOS transistor 6 which is connected to the vertical signal conductor 101 and the threshold value is low, which means that the horizontal MOS transistor 6 is turned on.

At this time, charges stored in the vertical signal conductor 91 are transferred to the image output 11 via the horizontal MOS transistor 6, and they are read as output signals. Next, loads corresponding to the vertical signal conductors 102 to 10n, which are selected in order, are successively read as output signals. In this way, the charges of the photodiode 1 are read and presented at the output via all the vertical MOS transistors 2 which are connected to the gate signal conductor 81.

 Next, the vertical shift register 12 successively selects the gate signal conductors 82 to 8m, and charges corresponding to the vertical signal conductors 101 to 10n are successively read as an output signal. Thus, the signals of all the pixels 4 constituting the array of pixels 5 are transmitted successively for each pixel.

 FIG. 7 is a time diagram in the case where the array of pixels 5 successively transmits signals. In FIG. 7, a frame period is a period during which all the pixels 4 transmit signals once. This period is equal to the time necessary to roughly scan alternating horizontal lines (a frame period = 1/60 second) in an NTSC system, which is a system of chrominance signal transmission in television, used for example in Japan and the USA In addition, a horizontal period (H) corresponds to the time during which all the pixels 4, which are connected to one of the gate signal conductors 81 to 8 m, transmit signals once. This duration is equal to the time necessary to read n pixels 4.

 In the MOS type infrared image sensor described above, noise appears during the conversion of infrared light into electrical signals, and during the transfer of electrical signals for reading.

 More precisely, in the conversion of light into electricity, noise of shot is caused by the natural fluctuation of the current which is due to independent and random movements of charged particles, i.e. electrons and holes, in a desertion layer of photodiode 1. In signal transfer, free electrons, which are present in resistive components of vertical signal conductors 91 to 9n, perform random thermal movements under temperature dependence and they generate a alternating voltage, which causes an alternating current to flow between the resistive components and the parasitic capacitive components of the vertical signal conductors 91 to 9n, which produces thermal noise.

 The shot noise and the thermal noise which are thus produced are applied to the image output 11 together with the electrical signals, which produces a scintillation of the images when this output is connected to a television receiver.

 To solve this problem, an improved MOS type infrared image sensor has been developed, which comprises a capacitor storing charges which are transferred from pixel 4 to the vertical signal conductors 91 to 9n.

 FIG. 8 is a block diagram showing the overall structure of the MOS type infrared image sensor which is described for example in the document SPIE Vol. 819, Infrared Technology XIII (1987), page 224. In FIG. 8, a charge storage capacitor 14 is placed between the vertical signal conductors 91 to 9n and the network of horizontal MOS transistors 7. A reference voltage input 37 applies a constant voltage (4 V) to the charge storage capacitor 14.

FIG. 9 is a section of the infrared image sensor of the type
MOS which is shown in Figure 8. In Figure 9, n + 31 and 32 type diffusion regions are formed in an island region which is isolated by the field oxide layers 22. An oxide layer of gate 33 is formed between the n + 31 and 32 type diffusion regions, and a gate electrode 34 is formed on the gate oxide layer 33.

The charge storage capacitor 14 comprises the p-type silicon semiconductor substrate 21, the gate oxide layer 33 and the gate electrode 34.

 We will now describe the operation. As in the case of the MOS type infrared image sensor which is represented in FIGS. 5 and 6, the gate signal conductor 81 is selected and charges from pixel 4 which is connected to the gate signal conductor 81 flow towards the vertical signal conductors 91 to 9n.

 Because a voltage of 4 V is applied to the reference voltage input 37, a desertion layer extends in the surface region of the p-type silicon substrate 21, below the electrode. grid 34 of the charge storage capacitor 14, and a potential well is formed. Under these conditions, the charges which have entered the vertical signal conductors 91 to 9n flow towards the potential well and they are stored in the charge storage capacitor 14.

 In this state, when the vertical signal conductors 101 to 10n are successively selected, the charges which are stored in the charge storage capacitor 14 are transferred to the image output 11 via the respective horizontal MOS transistors 6, which are in the conductive state, and these charges are read in the form of output signals. Then, the gate signal conductors 82 to 8m are successively selected, and the charges which correspond to the vertical signal conductors 101 to 10n are read in the form of output signals.

 FIG. 10 is a time diagram showing the condition under which signals are transmitted successively by the array of pixels 5.

In FIG. 10, a horizontal period is equal to the sum of a duration for the storage in the charge storage capacitor 14 of the charges of all the pixels 4 (the number of n), which are connected to one of the gate signal conductors 81 to 8m, and of a duration for reading the stored charges. Figure 11 is a diagram showing clock pulses which are applied at that time to the respective electrodes. It can be seen that signals from the pixels selected by the respective shift registers during a horizontal period are read in the same horizontal period.

In this MOS type infrared image sensor, the charges which have entered the vertical signal conductors 91 to 9n are stored in the charge storage capacitor 14 before being read in the form of output signals. As the amount of charge stored for the output signals increases in proportion to the storage time, shot noise and thermal noise increase in proportion to the square root of the storage time. More precisely, when the duration of storage increases, the quantity of charges corresponding to the noises decreases compared to the quantity of charges of the output signals, so that the signal to noise ratio (ratio
S / B) increases. Therefore, the level of shot noise and thermal noise which are read in conjunction with the output signals is lowered, which improves the output characteristics.

 However, in the MOS type infrared image sensor described above, it is necessary to carry out separately the operations of storage of the charges and reading of the charges, during a horizontal period. Therefore, in the NTSC system in which a frame period is 1/60 second, the time required to read loads in a horizontal period increases with the increase in the number of pixels, and the time available for storing the charges decreases relatively. Thus, the charge storage time is limited by the charge read time, which makes it difficult to obtain a sufficient amount of stored charge, which leads to poor output characteristics. infrared images is connected to a television receiver, you do not get separate images.

 An object of the invention is to provide a semiconductor image sensor which makes it possible to obtain a sufficient quantity of stored charges and which has better output characteristics.

 According to one aspect of the invention, a semiconductor image sensor comprises a charge storage part comprising a first capacitor, for storing signal charges which are read in a part of pixels, control means which are intended for controlling the transfer of signal charges stored in the first capacitor, which are located in the stage which follows the first capacitor, and a second capacitor which is intended to store the signal charges transferred by the control means. In this structure, charges stored by the first capacitor during a horizontal period are read from the second capacitor during the next horizontal period, therefore the charge storage and charge reading operations are performed simultaneously and in a manner mutually parallel during a horizontal period, which means that the charge storage time is not restricted by the charge read time, which makes it possible to obtain a sufficient quantity of stored charges.

Other objects and advantages of the invention will emerge from the detailed description which follows, given by way of nonlimiting example. The following description refers to the accompanying drawings in which
FIG. 1 is a block diagram showing an MOS type infrared image sensor according to an embodiment of the present invention
Figure 2 is a section of the type infrared image sensor
Figure 1 MOS
Figure 3 is a diagram showing a potential transition according to the embodiment of the present invention
FIG. 4 is a time diagram relating to the exit operation in accordance with the embodiment of the present invention
Figure 5 is a block diagram showing a prior art MOS type infrared image sensor
Figure 6 is a section of the type infrared image sensor
MOS of the prior art which is shown in Figure 5
FIG. 7 is a time diagram relating to the output operation of the infrared image sensor of the MOS type of the prior art which is represented in FIG. 5
FIG. 8 is a block diagram showing another prior art MOS type infrared image sensor
Figure 9 is a section of the type infrared image sensor
MOS of the prior art which is shown in Figure 8
FIG. 10 is a time diagram relating to the output operation of the MOS type infrared image sensor of the prior art which is represented in FIG. 8
FIG. 11 is a diagram showing clock pulses in the operation of the prior art MOS type infrared image sensor, shown in FIG. 8; and
FIG. 12 is a diagram showing clock pulses in the operation of the MOS type infrared image sensor according to the present invention.

FIG. 1 is a block diagram showing the overall structure of an MOS type infrared image sensor according to an embodiment of the present invention. In FIG. 1, a network of charge read capacitors 15 is placed between the above-mentioned network of charge storage capacitors 14 and the network of transistors
Horizontal MOS 7. A network of charge transfer control capacitors 16, fulfilling the function of a control gate, is placed between the network of charge storage capacitors 14 and the network of charge read capacitors 15.A clock input XST1 17 applies a pulse voltage to electrodes of the charge storage capacitor array 14, a clock input # ST2 18 applies a pulse voltage to electrodes of the charge read capacitor array 15, and a clock input #SC 19 applies a pulse voltage to electrodes of the charge transfer control capacitor network 16.

Figure 2 is a section of the type infrared image sensor
MOS which is shown in Figure 1. In Figure 2, a gate electrode 35, to which a signal from clock input # ST2 is applied is formed on the gate oxide layer 33. The width of the gate electrode 35 is approximately equal to that of the gate electrode 34. A gate electrode 36, to which a signal from the clock input Xsc is applied, is formed between the gate electrodes 34 and 35 .

The width of the gate electrode 36 is less than that of the gate electrode 35. The charge reading capacitor 15 comprises the p-type silicon substrate 21, the gate oxide layer 33 and 1. gate electrode 35. The charge transfer control capacitor 16 comprises the p-type silicon substrate 21, the gate oxide layer 33 and the gate electrode 36.

 More specifically, the charge storage capacitor 14, the charge transfer control capacitor 16 and the charge read capacitor 15 in the same column are formed in the same island region surrounded by the field oxide layer. 22. In addition, the gate electrode 34 of the charge storage capacitor 14, the gate electrode 36 of the charge transfer control capacitor 16 and the gate electrode 35 of the charge read capacitor 15 , are formed in this order from the side of the n-type diffusion region 31 which is connected to the drain region 24 of the vertical MOS transistor 2, towards the side of the n + 32-type diffusion region which is connected at the source region 25 of the horizontal MOS transistor 6, on the gate oxide layer 33 which is formed on the surface of the semiconductor substrate 21 between the diffusion regions n 31 and 32.

These electrodes are electrically separated from each other.

 This structure achieves an integrated circuit having a simple structure, without significantly reducing the integration density.

 Parts (a) - (d) of Figure 3 are diagrams which show a transition of the potentials of the charge storage capacitor 14, the charge read capacitor 15 and the charge transfer control capacitor 16 at times. tl to t4.

 The operation of the infrared image sensor of FIG. 1 will be described with reference to parts (a) - (d) of FIG. 3.

 First, as in the case of the MOS type infrared image sensor which is shown in FIGS. 5 and 6, the gate signal conductor 81 is selected, and charges of pixel 4 connected to the gate signal conductor 81 circulate towards the vertical signal conductors 91 to 9n. In this state, when a voltage of 4 V is applied to the clock input s6ST1 17, a desertion layer extends in the surface region of the p-type silicon semiconductor substrate 21, below the the gate electrode 34 of the charge storage capacitor 14, and a potential well is formed, as shown in part (a) of FIG. 3. The charges which enter the vertical signal conductors 91 to 9n are transferred to the potential well and they are stored in the charge storage capacitor 14.

 When a voltage of 4 V is applied to clock input # ST2 18 and to clock input BSC 19, a desertion layer extends in the surface region of the p-type silicon semiconductor substrate , below the gate electrode 35 of the charge read capacitor 15 and the gate electrode 36 of the charge transfer control capacitor 16, and a potential well is formed, as shown in part ( b) of FIG. 3. At this time, no potential barrier is formed between the charge storage capacitor 14 and the charge transfer control capacitor 16, so that part of the charges which are stored in the charge storage capacitor 14 are transferred to the charge transfer control capacitor 16 and the charge read capacitor 15, and they are stored therein. The potentials of the charge storage capacitor 14, the charge transfer control capacitor 16 and the charge read capacitor 15 are in the same state.

 When a voltage of 0 V is applied to the clock input ~ ST1 17 and to the clock input Xsc 19, the desertion layer which is located under the gate electrode 34 of the charge storage capacitor 14 and the gate electrode 36 of the charge transfer control capacitor 16 is reduced, and the potential well disappears, as shown in part (c) of Figure 3. At this time, a potential barrier is formed between the charge read capacitor 15 and the charge transfer control capacitor 16, and the charges which are stored in the charge storage capacitor 14 and the charge transfer control capacitor 16 are transferred to the read capacitor 15 and are stored therein.

 When a voltage of 4 V is applied to the clock input XST1 17, a desertion layer extends under the gate electrode 34 of the charge storage capacitor 14 and a potential well is formed as shown part (d) of FIG. 3. At this moment, a potential barrier is formed between the charge storage capacitor 14 and the charge transfer control capacitor 16, and the charge storage capacitor 14 and the capacitor load reading 15 are mutually separate, with the charge transfer control capacitor 16 therebetween.

 In this state, the vertical signal conductors 101 to 10n are successively selected. When the vertical signal conductor 101 is selected, the horizontal MOS transistor 6 which is connected to the vertical signal conductor 101 is turned on. Consequently, the charges which are stored in the charge reading capacitor 15 corresponding to the horizontal MOS transistor 6, are transferred to the image output 11 via the horizontal transistor 6, and they are read in the form of signals. Release. When the vertical signal conductors 102 to 10n are successively selected, the charges stored in the load read capacitors 15 corresponding to the vertical signal conductors 102 to 10n are successively read as output signals. all the pixels connected to the gate signal conductor 81 are stored in the charge storage capacitor 14, and they are then read from the charge read capacitor 15.

 In addition, when the gate signal conductor 82 is selected simultaneously with the reading of charges in the charge read capacitor 15, the charges of the pixel 4 connected to the gate signal conductor 82 are transferred to the charge storage capacitor 14, via the vertical signal conductors 91 to 9n, and they are stored in this capacitor. The quantity of stored charges increases in proportion to the time spent reading, as output signals, all the charges which are stored in the charge reading capacitor 15.

 When a voltage of 4 V is applied to the clock input BSC 19, a desertion layer extends in the surface region of the p-type silicon substrate 21, below the gate electrode 34 charge storage capacitor 14, and a potential well is formed.

At this time, part of the charges which are stored in the charge storage capacitor 14 is transferred to the charge transfer control capacitor 16, and the charge read capacitor 15. Next, the operations which are represented in the parts (b) to (d) of Figure 3 are repeated. In this way, the gate signal conductors 83 to 8m are successively selected and the charges corresponding to the vertical signal conductors 101 to 10n are successively read as output signals.

 FIG. 4 is a time diagram for the condition in which signals are transmitted successively by the array of pixels 5.

In FIG. 4, a horizontal period is equal to the time necessary to store in the charge storage capacitor 14 the charges of all the pixels 4 (the number of n) which are connected to one of the signal conductors grid 81 to 8m. In addition, a horizontal period is also equal to the time necessary to successively read the charges which are stored in the charge reading capacitor 15.

Figure 12 shows clock pulses which are applied to the respective electrodes at this time. During a horizontal period (1H), when the drive signal of the vertical shift register 12 and the clock input #STl are at the high level, charges are stored in the charge storage capacitor 14, and when l the clock input Xsc is at a low level, the charges are transferred to the charge reading capacitor 16. During the following horizontal period (2H), charges are stored in the charge storage capacitor 14 in an identical manner to that described above, and the charges which are stored in the charge reading capacitor 15 until the clock input XST2 goes low, are successively read under the time conditions established by the signal d attack of the horizontal shift register 13, in the order of the respective pixels (81, 101), (81, 102), ... (81, 10n).

 In the MOS type infrared image sensor having the structure described above, the storage of charges and the reading of charges are performed simultaneously and in parallel for a single horizontal period, so that the charge storage time n is not restricted by the charging reading time. It is therefore possible to extend the charge storage duration up to a horizontal period, by increasing the number of pixels, and it is thus possible to obtain a sufficient quantity of stored charges, which leads to an infrared image sensor of MOS type with better output characteristics, which provides clear images when connected to a television receiver.

Although in the embodiment which is described above, the charge storage capacitor 14 and the charge read capacitor 15 are incorporated in an infrared image sensor of the type
MOS which converts infrared light into electrical signals, capacitors 14 and 15 can be incorporated into a semiconductor image sensor which converts invisible light, such as ultraviolet light, or X-rays, into electrical signals, or in a semiconductor image sensor that converts visible light into electrical signals. In both cases, effects identical to those described above can be obtained.

 As is evident from the foregoing description, and in accordance with the present invention, a semiconductor image sensor comprises a charge storage part comprising a first capacitor for storing signal charges which are read in a part of pixels, control means for controlling the transfer of signal charges stored in the first capacitor, and located in the stage which follows the first capacitor, and a second capacitor for storing the signal charges which are transferred by the means control. In this structure, charges which are stored by the first capacitor during a horizontal period are read from the second capacitor during the next horizontal period. Therefore, charge storage and charge reading: are performed simultaneously and in parallel for a horizontal period, which makes the charge storage time is not restricted by the charge reading time, and can be obtained sufficient charge storage time. As a result, a semiconductor image sensor can be made having better output characteristics.

 It goes without saying that numerous modifications can be made to the device described and shown, without departing from the scope of the invention.

Claims (3)

 1. A semiconductor image sensor comprising a part of pixels (4) which comprises a part for converting light into electricity (1) and a part for reading a charge which reads charges of optical origin coming from the part of conversion of light into electricity (1), a charge storage part (14, 15, 16) which stores signal charges which are read in the pixel part (4), and a stored charge reading part (6, 13) which reads the signal charges in the charge storage part (14, 15, 16), characterized in that the charge storage part comprises: first charge storage means (14) which are intended to store the signal charges which are read in the pixel part (4); control means (16) for controlling the transfer of charge from the first charge storage means (14), which are incorporated in a stage placed after the first charge storage means (14); and second charge storage means (15) which are intended to store the charges transferred by the control means (16).  2. Semiconductor image sensor according to claim 1, characterized in that the respective components are formed on the same substrate (21) and the charge storage part (14, 15, 16) is formed so that a set of electrodes (34, 35, 36) are placed on the same insulating layer (33) formed on the substrate (21) between the light to electricity conversion part (1) and the charge reading part (6) of the pixel part (4).  3. Semiconductor image sensor according to claim 1, characterized in that the charges which are stored for a horizontal period by the first charge storage means (14) are read in the second charge storage means (15) during the next horizontal period.