FR2667961A1 - DEVICE FOR TRANSFERRING DIGITAL DATA USING DIRECT ACCESS IN MEMORY. - Google Patents

Abstract

Techniques for transferring data in computer systems are disclosed. A direct memory access (DMA) control unit and an input / output (I / O) processor are associated to perform digital data transfer. The processor first identifies a start command word (302) under the action of which it initializes (304) the DMA control unit. The latter generates an interrupt (310) following the transfer of all the intermediate words of the data record. The processor performs a final error checking procedure (312) under the effect of the interrupt, which allows it to perform other tasks while the DMA control unit performs each record transfer. data. Application to avionics.

Description

The present invention generally relates to a transfer system

digital information, and she

  more particularly relates to a method and system for the transfer of digital data between elements of an aircraft avionics system by the use of direct memory access operations.

  Various structures have been employed for the transfer of digital data between aircraft avionics system components. Such structures are typically in accordance with the standards specified in ARINC Specification 429-11 entitled "Mark 33 Digital". Information Transfer System (DITS) ", published August 29, 1988 by Aeronautical Radio, Inc. The ARINC Specification 429 facilitates the compatible association of equipment15 that can be realized by various manufacturers The ARINC Specification 429 specifies general numerical data word formats predefined, and coding examples. In the ARINC data system 429, the bit rate for high speed operation is set to be 100 kilobits per second + 1%, while a bit rate selected for low speed operation is set within a range of 12.0 to 14.5 kilobits per second In addition, the rate selected for low speed operation should be kept to within 1%. US Patent 4,280,221 discloses a digital data transmission system including a

  data source, a source interface and a digital data bus for transferring encoded information from the data source to one or more receivers, each of which has a receiver interface. The source interface can be adapted to control

  der the rise and fall times of the signals on the data bus at a different set of frequencies. The source interface and the receiver interface can operate at both a high data rate of

  kilobits per second, and at a low data rate of 12 to 14, 5 kilobits per second.

  US Patent No. 4,298,959 discloses a receiver of a digital information transfer system which is intended to allow direct memory access (DMA) for a signal processor. The receiver of the digital information transfer system records directly

  in a data RAM of the digital information transfer system, data received asynchronously on a set of input channels, the recorded data being such that they are received.

  The first byte indicator of the data word information field, which identifies the data source, is used as the address pointer, to define the position in the random access memory at which the signal bits are to be recorded. Subsequent data word A common sampling network samples the data that is received on each input channel, to form samples having a duration less than that of a bit cell. The sampling network produces at least one sample high velocity signals and low speed signals during the period corresponding to the signal velocity of each. The sampled data is multiplexed into a serial data stream and is

  directed either to a first multi-address register or directly to the data RAM.

  U.S. Patent No. 4,646,324 discloses an emitter of a digital information transfer system, which is intended to transmit serial words of predetermined length at selected speeds for transmission on Parallel channel set The digital transmitter is designed to present to the digital information transfer system receiver which is described in US Pat. No. 4,298,959, flight parameter simulation data, from The 3 words that are selected for serial transmission on the parallel output channels are sequentially and repeatedly applied to a multiplexer that directs selected bits from these words, with fixed speeds. and settable variables to a selected combination of a shift register and a latch network for transmission The systems which are described in FIG. The US patents 4,298,959 and 4,646,324 are designed for broadcasting data consisting of 32-bit words, which are transmitted at periodic intervals, and which generally contain discrete signals and state signals. instruments. The traditional ARINC 429 file data transfer protocol uses ARINC 429 interface logic that operates in response to interrupts or polls, and requires significant processing overhead for an input processor / output (I / O) common in the system With an interrupt-dependent structure, the processor

  I / O is interrupted for each data word in the transfer Each interrupt adds a system time -

  noticeable and therefore has a significant workload for the I / O processor An even higher processing time is required for the polling inter-face logic, in which a protocol

  Continuous "handshake" between two terminals requires constant monitoring of the status of a transmitter.

  Interface receiver The I / O processor suspends important tasks for file transfers.30 The frequency and duration of these interrupts are particularly troublesome in a network management system.

  data. An object of the present invention is to provide a method and a control unit for direct access to

  Advanced type (DMA), allowing a transfer

  effective, efficient and reliable data.

  Another object of the invention is to provide a method and a direct memory access control unit.

  used in a digital information transfer system

  The implementation of the ARINC file data transfer protocol 429 is substantially independent of an input / output (I / O) processor. Another object of the invention is to provide a method and a receiver control unit ARINC 429 which

  eliminate disadvantages of structures of the prior art.

  In summary, the objects and advantages of the invention are achieved by means of a method and a control unit.

  direct memory access for digital data transfer in a digital information transfer system having an input / output (I / O) processor.

  First, the I / O processor identifies a starting slur. Under the effect of the starting slur that is identified, the I / O processor initializes and validates an access control unit. directly in memory (DMA) The DMA control unit generates an interrupt and applies it

  the I / O processor following the transfer of all intermediate data words from the data record. Due to the effect of the pulse that is received during a data reception function, the data processor I / O executes a final error checking procedure.

  The I / O terminator thus has the ability to perform other tasks while the DMA controller performs each data record transfer, and the I / O processor is terminated after receiving or transmitting each complete data record.

  Other features and advantages of the invention will be better understood on reading the description.

  The following description of an embodiment, given by way of nonlimiting example.

  Referring to the accompanying drawings in which Fig. 1 is a schematic block diagram representation of an ARINC 429 digital information transfer system which is used for file transfer based on the direct memory access technique, in accordance with the invention; Fig. 2 is a more detailed block diagram representation of a data management unit of the ARINC digital information transfer system 429 of Fig. 1; Fig. 3 is a flowchart illustrating logic steps performed by an ARINC 429 input / output processor (I / O) of Fig. 1 for receiving a file; and FIG. 4 is a flow chart that illustrates the logical steps that an I / O processor performs

  (I / O) of the ARINC digital information transfer system 429 of FIG. 1 for issuing a file.

  Referring now to the drawing, FIG. 1 shows a synoptic representation of a digital information transfer system.

  ARINC 429 which is generally designated by reference 10 and which is designed in accordance with the invention The main components of the ARINC system 429 as reference 10, include an ARINC transceiver 429, 12, a data management unit subsystem

  14, operably connected to the transceiver 12, a memory 16, such as a static random access memory (SRAM) for recording data and status information, and a data bus 18 for establishing two-way communication between the transceiver 12, the

  data management unit subsystem 14 and static RAM 16 The data management unit subsystem 14 comprises an input / output (I / O) processor 20,35 a control unit d interrupt 22, a communication unit

  DMA 24, DMA control logic 26, error management logic 28 and ARINC transceiver 429, 12, associated The main function of the subsystem The data management system 14 is to collect and control various data that are generated in an aircraft. The architecture of the data management unit subsystem 14 is based on the use of multiple processing elements that reside. on a single system bus, with communications provided by the I / O processor 20 The I / O processor 20 uses standard ARINC 429 serial data links with other systems of the aircraft, such as for example, an input / output device 30 which is shown. The format for the transfer of digital file data that is defined by the ARINC 429 standard is divided into data records. Each data record contains from 1 to 126 intermediate data words that follow an initial word having the meaning of "data". next "Each record in the file is transferred consecutively using the ARINC file data transfer protocol 429, as follows. An issuer which is to transmit the data to a receiver, transmits an initial broadcast request word ( or RTS) on the bus which connects it to the receiver in question The receiver reacts by transmitting a transmission authorization (or CTS) response on the separate bus which is intended to

  the return data stream The issuer then sends the initial word having the meaning "data follow". The initial word having the meaning of "data following" indicates to the receiver the number of intermediate data words which will be transmitted during the transmission of recordings.

  Following the transmission of the initial command / response words between the transmitter and the receiver, the transfer of the recording continues with the transfer of the intermediate data words, which are followed by a Final error control word The receiver processes

  the final error control word, and if no error is detected, it terminates the transaction by sending to the receiver a word (ACK) indicating that the received data5 were correct. When errors are detected, the receiver transmits to the transmitter a word (NAK)

  as long as the received data were incorrect The ACK or NAK acknowledgment from the receiver is expected for a predefined time interval of 50 millisecon-10 after the final error check word.

  In accordance with the present invention, the processing requirements of the I / O processor 20 are minimized for the transfer of large data files between the data management unit subsystem 14 and other data storage systems. an aircraft, such as the disk memory unit 30, while using the data transfer protocol of

  ARINC file 429 The conventional protocol based on interrupts or polling requests is used between the I / O processor 20 and the ARINC transceiver 429,20 12, during the transmission of the initial command / response words. , before the transfer of the intermediate data words

  After a predefined password has been transmitted, such as the initial word having the meaning of "data following," the I / O processor 20 validates the control unit of the data. direct memory access (DMA) 24 to support the transmission of

  Each of the data words is transmitted sequentially, under conditions in which the DMA controller 24 performs the transfer of the data record independently of the I / O processor. DMA control 24 draws the attention of the I / O processor 20, with an interrupt applied through the interrupt control unit 22, upon completion of the transfer of the record. The I / O processor 20 then performs the final error control steps that complete the transfer. The DMA control unit 24 performs both data transmission and reception. For the transceiver 22, a conventional ARINC 429 transceiver IC chip may be used, including a transmitter and at least one receiver. The ARINC transceiver 429, 12, which is incorporated in the subsystem The data management unit 14 has only one 810 bit read / write access for the I / O processor.

  429 is 32 bits long, the DMA control logic 26 allows the completion of four

  8-bit DMA actions for each 32-bit ARINC 429 data word transfer The complexity of DMA control logic 26 required for a transceiver having 16-bit access can be reduced. or this logic can be eliminated by using a transceiver with 32-bit access A receiver logic signal corresponding to a logical "OR" combination of the "frame ready" bits of all receivers of the transmitter receiver 12, is applied to the control logic of

  DMA 26, and the interrupt control unit 22, as indicated by a line labeled RCVR HIT An emitter logic signal which returns to the "" state when the first byte of the next frame is loaded in a first-in, first-out register of the issuer

  receiver 12, is applied to the DMA control logic 26 and the interrupt control unit 22, as indicated by a line labeled XMIT MT. The DMA control logic 26 applies transfer requests. data to the DMA 24 control unit as indicated by a line marked DMA REQ (S). The error control is performed by the error management logic 28, in association with the logic of

  DMA control 26 The error management logic 28

  An error condition is set when the number of intermediate data words that are transferred is less than a number erroneously indicated by the initial word having the meaning of "data following". interrupting error to avoid blocking the DMA control unit 24 while the I / O processor 20 performs other tasks

  The DMA control logic 26 may apply to the error management logic 28 a control signal indicated by the dashed line marked SSM VALID, to enable sampling of the SSM bits on the data bus.

  The error management logic 28 controls the SSM sign / state matrix data bits, 30 and 31, which are set to unambiguously identify a word of data among the initial command / response words (FIG. the bits are for example fixed at (01) 1 and the final error control word (the bits are for example fixed at (10)) While the data transfer of DMA is in progress, if the data bits SSM are different from a predefined value, such as if they have a low logic level (00), the error management logic 28 generates an error interrupt The error interrupt generated, which corresponds to a line labeled INT ERROR, is applied by the interrupt control unit 22 to the I / O processor 20 The I / O processor 20 applies an error acknowledgment signal to the I / O processor 20. management logic

  26, as indicated by a line marked ACK ERROR The I / O processor 20 may further perform all the conventional error checks on the received data record.

  Referring also to FIG. 2, there are two disk memory units 30 which are connected to the

  Two sets of differential signal lines ARINC 429 with the terms MDDU IN, PDL IN and MDDU OUT, PDL OUT, allow

  bidirectional data transfer through the

  The ARAM random access memory 16 comprises an assigned XMIT transmit data buffer 5 and an RCVR receive data buffer.

  for buffering sequential data words

  Tiels in data records that are received or transmitted ARINC 429 read, write and command signals are applied by the DMA 24 control unit

  to the transceiver 12, as indicated by a line carrying the SIGNAUX XCVR RD / WR / CS 429

  of a bus control logic 31 of conventional type. Various commercially available microprocessors with conventional capabilities can be used for the DMA control unit 24, such as the high-integration 16-bit 16-chip microprocessor 80 C that is manufactured and marketed by Intel Corp. Santa Clara, California, as shown in FIG. 2 The integrated functions of the microprocessor 80 C 186 comprise two direct memory access channels (DMA) O and 1, which are fast and independent programmable interrupt, 3 timers

  16-bit programmable logic controllers, a bus interface unit, a programmable memory and peripheral chip selection logic, including control registers

  Although only one DMA channel can be programmed for the reception or data transmission functions of the control unit of DMA 24, it is possible to program for reception one of the DMA channels O or 1 of the DMA control unit 80186 24, while

  The other is programmed for data transmission. The DMA channels O or 1 enable full duplex operation. Each of the DMA channels O and 1 includes a set of registers. SOURCE ADDRESS, DESIRED ADDRESS

  it NATION, NUMBER OF TRANSFERS and REGISTER OF COMMAND, which

  are generally designated by the respective references

36 and 38.

  Error protection logic 39 includes command word recognition logic, which identifies the condition in which the number of data words that are received is less than the number programmed into the DMA command register NUMBER OF TRANSFERS register. The command word recognition logic 40 controls the sign / status matrix data bits SSM, 30 and 31, which unambiguously identify a data word forming part of the initial command / response words and the final word of the command word. error check While the transfer of a data record with DMA is in progress, when the data bits SSM have a value other than the predefined low logic value (00),

  the control word recognition logic 40 generates an error interrupt The generated error interrupt, which is indicated on a line labeled ERREUR20 RECORDING, is applied to the I / O processor 20, via of the interruption control unit 22.

  An ARINC read counter 429, 42, and an ARINC write counter 429, 44 perform the function of

  the DMA control logic 26 of FIG. 1, to auto-eliminate four 8-bit DMA transactions for each 32-bit ARINC 429 data word transfer by the transmitter.

  The ARINC read counter 429, 42, may apply a signal to the control word recognition logic 40, to sample

  SSM bits 30 and 31 of the last byte of each data word transfer.

  A receiver logic signal corresponding to a logical "OR" combination of the "ready frame" bits of all the receivers in the transceiver 12 is applied to the error protection logic 39, as indicated by a line carrying the ANY indication RCVR HIT Individual "frame ready" bits from each of two receivers of the transceiver 12 are applied to the interrupt control unit 22, as indicated by a pair of lines labeled MDDU. HIT and PDL HIT. An emitter output signal that changes logic level when the first byte of the next frame is loaded into a "first-in first-out" register of the transceiver 12, is applied to the pro-detection logic against errors 39 and interrupt control unit 22, as indicated by a line bearing the

  XMIT EMPTY The byte read and write counters 42 and 44 apply data transfer requests to the DMA control unit 24, as indicated by the lines labeled DMA RQO and DMA RQ. 1.

  When the ARINC transceiver 429, 12, of the data management unit subsystem 14 is to be used to transmit a file, the DMA channel 1 of the DMA control unit 24 is initialized by the process. 20 I / O 20, to transfer data from the memory 16 to the transceiver 12 Initialization of the channel 1

  The DMA control unit comprises the setting of appropriate values in the DMA registers. The DMA source pointer is set to the address of the first data record in the memory 16, and the pointer destination is fixed to designate the issuer

  ARINC receiver 429, 12 The size of the record is set in the appropriate register of the DMA control unit (number of transfers), and a checksum word30 is placed at the end of the data record, for

  be issued after the words of the data record. The transmission of the data file record

  Then, under conditions in which the DMA control unit 24 is disabled, and the I / O processor transmitter and receiver interrupts are validated. The initial commands / responses, such as the words

  RTS, CTS and "data follow" are issued.

  which is directed from the transceiver 12 to the

  I / O processor 20 is then disabled, and an interrupt

  DMA 24 control unit is validated The DMA data transfer process is then enabled to proceed, with the DMA 24 control unit synchronized by the transmitter of the transmitter. When the XMIT transmitter buffer of the transceiver 12 is empty, the next 32-bit word is transferred by the DMA control unit 24 to the XMIT transmitter buffer, for transmission. While this DMA data transfer is in progress, the I / O processor 20 is free to perform other tasks. When the transfer of the data record by DMA is complete, the I / O processor 20 is free to perform other tasks. The DMA control unit 24 interrupts the I / O processor 20, which then verifies the appropriate ACK / NAK response, from the receiver during a 50 millilitececond interval. This process is repeated until the transfer is complete. the data file is finished The ARINC 429 receiver remains valid during the whole

  transmission, and the I / O processor 20 can capture any error messages from the receiver, such as the final ACK / NAK message, after each data record.

  When the ARINC transceiver 429, 12, of the data management unit subsystem 14 is used

  to receive a file, the DMA channel O of the DMA control unit 24 is initialized by the I / O processor 20 to transfer data to the memory 16, from the transceiver 12. includes fixing

  appropriate values in the registers 36, with the source pointer of DMA designating the transceiver 12, and the destination pointer designating the memory 16.

  The record size is placed in the appropriate register of the DMA control unit, after this information has been received in the initial word having the meaning of "following data". Receiving the record file data begins with the word RTS pro-5 from the transmitter of the transceiver 12 The control unit of DMA 24 is initially disabled, while

  the emitter and receiver interrupts are validated. The use of this interrupt interface with the transceiver 12 makes it possible to process the initial order / response transactions, such as the RTS / CTS words and the initial word having the meaning of "following data".

  The interrupt for the I / O processor 20 from the transceiver 12 is then enabled, and an interrupt from the DMA control unit 24 is enabled. The data transfer process by DMA is then validated to unfold with the control unit of

  For example, when the RCVR receiver buffer of the transceiver 12 is full, the 32-bit word is transferred by direct memory access to the random access memory. static 16, by the control unit of DMA 24.

  During the receive function, the SSM information is sampled by the error detection logic

  39, to determine whether a word that is not a word of

  was received using the DMA function An error is identified when the number of words originally supplied by the source of the file and programmed into the DMA receive word counter, 42, does not match. - string not with the actual number of received words, or when an unexpected end of record (other than data) is received It is noted that this error function is only applicable when the control unit I / O 24 receives a file The protection against the detection of error during the transmission of a file is provided by the control of the receiver ARINC 429 In the case where the receiving device finds an error in the transmitted data, an acknowledgment signal NAK signaling an error is returned for recording. While the transfer of the data record by DMA is in progress, the I / O processor 20 is free to perform other tasks. When the transfer of the data record by DMA is completed, the unit DMA 24 interrupts the I / O processor 20. Thereafter, the I / O processor 20 restores the interrupt protocol with the transceiver receiver 12, and executes the final control procedure. error. The I / O processor 20 then transmits or receives the response

  ACK / NAK appropriate, within 50 milliseconds This process is repeated for each data record until the file transfer is complete.

  Referring now to FIG. 3, there is shown a flowchart illustrating logic steps that the I / O processor 20 performs for a file receiving function. The sequential steps begin, as indicated by a box 300, by the identification. a slogan of

  The control unit of DMA 24 is initialized and validated by the I / O processor 20 as indicated by the I / O processor 20 as indicated in block 302. box 304, under the effect of a starting slogan identified in box 302 Then, when the process

  I / O receiver 20 receives an error interrupt, as indicated by a box 306, the I / O processor 20 transmits an error acknowledgment signal NAK, as indicated by a box 308.30. Otherwise, when the I / O processor 20 does not receive an error interrupt at block 306, the DMA control unit 24 applies a full data logging interrupt to the processor. I / O 20, following the transfer of all intermediate data words from the complete data record, as indicated by a box 310. Next, the I / O processor 20 executes the final procedure. error control, as indicated by a box 312, under the effect of receiving the complete data recording interrupt, at box 310 Ensui-5 te, as indicated by a box 314, a ACK or NAK message is issued by the IE / S processor 20, in correspondence with the particular operation for the data file transfer. Now looking at Figure 4, we see a

  a flowchart that illustrates the logical steps that the I / O processor 20 performs for a data transmission function.

  The sequential steps begin, as indicated by a box 400, by the identification of a transmit authorization password received by the I / O processor 20 as indicated by a box 402 The control unit of DMA 24 is initialized and validated, and the starting order and the record

  are transferred by the I / O processor 20, as indicated by a box 404, under the effect of a transmission authorization order which has been identified in box 402. I / O processor 20 receives an unexpected interrupt, as indicated by a box 406, the I / O processor 20 executes an error handling procedure, as indicated by a box 408 Next, the sequential operations return in box 402 to reissue the registration In the opposite case, when the I / O processor 20 does not receive an unexpected interrupt at block 406, the I / O processor 20 identifies an interrupt of complete data record from the DMA control unit 24, following the transfer of all intermediate data words from the complete data record, as indicated by a box 410. Then, the processor of I / O 20 checks the receipt of an ACK message, as indicated by a box 412, dependent the complete data log interrupt emitted, at box 410 When an ACK message is not received during

  predefined time interval, such as 50 milliseconds

  sequential operations return to box 402 to reissue the record. Otherwise,

  under the effect of an ACK message checked in box 412, the uni-

  DMA control station 24 is conditioned for issuing the next record The sequential steps are then repeated to issue the next record,

with return to box 402.

  It goes without saying that many modifications

  can be made to the device and method described and shown, without departing from the scope of the invention.

Claims (5)

  1 digital data transfer device in a digital information transfer system, characterized in that it comprises: a direct memory access control unit (DMA) (24); an input / output (I / O) processor (20) connected to the DMA control unit (24), said I / O processor (20) including means for identifying a word the starting order that is received by the I / O processor (20), and means responsive to the identified start word by initializing the DMA control unit (24); the control unit of DMA (24)   comprising means responsive to the initialization performed by the I / O processor (20) by transferring a data record, said data record having a predetermined number of intermediate words, and means (22) for generating an interruption and to   interrupt the I / O processor; and the I / O processor (20) including means for performing a final error checking procedure for the transferred data record, in dependence on the received interrupt.   2 Device according to claim 1, characterized in that it further comprises logic means of   error detection (28) for sampling at least one predetermined data bit in the intermediate data words to identify an error condition.   Apparatus according to claim 2, characterized in that the error detection logic means (28) performing sampling sample predetermined sign / state matrix (SSM) bits; and the device further comprises means for generating   an error signal dependent on a predetermined sampled value of the sampled SSM bits, and means for applying an error signal generated to the I / O processor (20).   4 Device according to claim 1, characterized   in that the DMA control unit (24) comprises a microprocessor. Device according to claim 1, characterized in that the means of the DMA control unit   (24) for transferring a data record include an ARINC 429 transceiver (12).   Device according to claim 1, characterized   in that it further comprises control logic means (26) for sequentially transferring a predetermined number of data bytes which are part of   of each intermediate data word.