FR2665968A1 - Multiple-layer neural network and its method of design - Google Patents

Abstract

The multiple-layer neural network receiving an input with m bits and generating an output with n bits includes a neuron linking, in cascade, a pair of CMOS inverters possessing an output node with inversion and an output node without inversion, an input layer (L0) of m neurons for m-bit input generation, an output layer (L3) of n neurons with n-bit output, at least one inaccessible layer (L1, L2) of n neurons for transfer from the input layer (L0) to the upper inaccessible layer or to the output layer (L3), an input synapsis group (S1) for linking the input layer (L0) to the output layer (L3) and to at least one inaccessible layer, at least one transfer synapsis group (S1, S2) so as to connect an inaccessible layer to the higher inaccessible layer or to the output layer (L3), and a polarisation synapsis group (S4) for each input node of neurons of the inaccessible layers (L1, L2) and of the output layer (L3).

Description

Multi-layered neural network and its design process. The

  The present invention relates to a multi-layer neural network and its method of design, and more particularly to a multi-layered neural network.

  ples and the design process that can be carried out

  easily read an integrated circuit on a very large scale

  of integration p Q Ur a multi-layered neural network.

  Recently, in the field of pattern recognition, neural networks that can perform large-scale parallel processing in real time were introduced. In 1988, Hans P Graf et al of Bell Labs presented a neural recognition network. forms in which amplifiers having their inputs and outputs interconnected via a

  resistive connection device in a matrix, constituting

  kill the synapses and neurons of the neural network, and a pair of switches that switch according to the data in a pair of random access memory cells,

  for an interconnection of neurons.

  The present applicant has filed numerous

  an adder (US Application No. 07 / 473,653), a multiplier (07 / 473,633), an analog / digital converter (07 / 473,631, 07 / 47,634), a

  models (07 / 473,464), etc., which use a neutral network

  ral having PMOS or NMOS transistor synapses, and buffer circuit neurons in the form of pairs

  Cascading CMOS Inverters Classical Neural Circuits

  The above-mentioned methods use a single-layer neural network model and can solve only linearly separable problems, and not those that are linearly inseparable problems (nonlinear problems).

  therefore, the range of application is extremely limited.

  For example, an exclusive OR circuit can not get the

  solution using a single layer neural network.

  Limiting a single layer neural network can

  overcome by a multi-layer neural network.

  It is known that a neural network can learn by a counter propagation algorithm (cf IEEE ASSP MAGAZINE,

Pages 4 to 22, April 1987).

  There are more restrictions in the

  This is because the realization of the multi-layered neural circuit depends on the current very large-scale integration technology, and that the realization of circuit of values of connection weight of a neural circuit and non-linear functions is not free as in the case of a software simulation Although real-number operations using a floating point, and an increase in the number of neural network connections and nodes can be accomplished by software, several problems remain- to achieve this in technology

  integration on a very large scale.

  It is an object of the present invention to provide a multi-layered neural network having entire connection weight values and a function

  step to solve the problem of the classical technique

  than. It is another object of the present invention to provide a multi-layer neural network circuit design method for designing the multi-layered neural network according to the new learning rule. In order to achieve this goal, the multi-layered neural network of the present invention receiving an m-bit input and generating an N-bit output comprises

  a neuron to cascade a pair of invert-

  CMOS inverters and having an output node of the preceding CMOS inverter among the pair of CMOS inverters as an inverting output node and an output node of the next CMOS inverter as an output node without inversion; an input layer having m neurons for receiving the m-bit input; an output layer having N neurons for generating the N-bit output; at least one inaccessible layer provided with n neurons for transferring the input received from the input layer to the directly higher inaccessible layer or the output layer; an input synapse group on a matrix having each predetermined weight value for connecting each neuron output on the input layer to each output layer neuron and at least one inaccessible layer; at least one transfer synapse group in a matrix having each predetermined weight value

  to link each neuron output of the inactive layer

  transferable to each neuron in its layer inaccessible to

  higher or the output layer; and

  a synapse group of polarization in order to polarize

  each neural input node of the inacces-

  sibles and the layer-out.

  Here, the input synapse group, the transfer synapse group, and the synapse polarization group are

  consisting of PMOS and NMOS transistors.

  In order to achieve the other goal, a pro-

  method of the multi-layer neural network design described above for receiving an m-bit input and generating an N-bit output, which comprises the following steps: a first step of initializing the synapse group connection weight value input

  a second step of setting the value of

  m-bit and a desired N-bit output value corresponding to the input value a third step of obtaining the sum of the weight values of 1 input on the node of 1 input of each neuron of the output layer and generating an actual output by a step function a fourth step of comparing the actual output value obtained in the third step with the desired output value set during the second step.

  step to calculate the error and memorize the varia-

  calculation of the calculated weight value according to the error value

  a fifth stage of apprenticeship termination

  wise if each output value is equal to its desired output value, or if it is not, to obtain the sum of the stored variation of the weight value and its addition to each current weight value for

  to obtain a new weight value after the se-

  fourth-stage count were performed compared to 2 mpairs of output nreet; a sixth step of reducing each weight value by a predetermined ratio, when the sum of

  the new weight value obtained during the

  second step in the node of 1 input of each neuron of the output layer is above a predetermined value; and a seventh step of using the output layer as an inaccessible layer, increasing the new output layer, and repeating the process starting with the second step using the output of the inaccessible layer and the initial entry as new entries, when the desired result is not obtained after repetition of learning

  up to the sixth step by the predetermined number of times

finished rehearsals.

  The foregoing and other benefits of the

  present invention will emerge from the description of the method

  preferred embodiment of the present invention with reference to the accompanying drawings, in which: Figure 1 is a conceptual diagram of a conventional multi-layered neural network; Figure 2 is a characteristic graph

  of a sigmoid function used during the course of

  classical multi-layer neural network; Figure 3 is a concept diagram of a multi-layered neural network according to the present invention; Figure 4 is a characteristic graph

  a step function used during the apprenticeship

  of the multi-layer neural network according to the pre-

  this invention; Figure 5A is a circuit diagram of an embodiment of the multi-layered neural network according to the present invention; and Figure 5B is a partial circuit diagram for explaining the synapse structure of Figure 5A. The present invention will be described below in

reference to the accompanying drawings.

  Figure 1 is a general multilayer neural network design scheme which is a predictive network having nodes of at least one layer.

  between input and output nodes These extra layers

  These components include inaccessible units or nodes that are not directly connected to both the input and output nodes. As shown in FIG. 1, the three-layer neural network has two-layer inaccessible layers L1 and L2 between the two-layer neural network. LO input layer and L output layer 3 The input layer

  LO has five neurons or nodes N 01 to N 05 to receive

  see entries X0 to X4 The inaccessible layers L1 and L2 each have three neurons or nodes N11, N12, and N13 and N21, N22, and N23, respectively, while the L3 output layer has also three neurons or

  nodes N 31, N 32 and N 33 to respectively generate outputs

  Y 0, Y 1 and Y 2 Here it should be noted that the number of neurons in each layer is determined by the number of input and output bits of the system circuit. The neurons or nodes of each layer are connected to all

  the neurons of its immediate lower layer

only dente.

  The network: classic multi-layer neural

  is instructed by the counter-training algorithm

  Previously known spread (BPTA) BPTA has the graphical feature shown in Figure 2

  and uses the sigmoid function represented in the equation

following (I)

1 + expl- (o 0).

  However, since the sigmoid function is an exponential function, the realization of the circuit is

difficult and complicated.

  Also, when a binary input and a step function are used, the conventional multi-layer neural network may have only one value with respect to different input values due to the inter-layer connection structure. upper layer input can not be

discriminated.

  Figure 3 is a view of the concept of a network of

  2 n multilayer neuron according to the present invention.

  The multi-layered neural network of the present invention

  is different from the multi-layered neural network of Figure 1 in that the neurons or nodes of each

  layer are connected to all the neurons of the layer:

  immediately as well as those of its directly previous lower layer Since other parts of its structure are the same as those in Figure 1, the

  same reference figures will be used for

  Likewise, network learning

  multi-layered neural of the present invention pos -

  follows the graphic characteristic represented on the

  4 and uses the step function represented by the following equation (II): N-1

Yi = lfh (Z Wi Xi O) + 1.

  i = O fh (y Wi Xi e): fixed limit nonlinear function G threshold value of the neuron node Wi: connection weight value with respect to Xi Xi: input The multi-layered neural network circuit according to the present invention invention is designed by

  the learning algorithm as follows.

  Step 1: All connection weight values between nodes are initialized.

  Step 2: a pair of input and output de-

  These inputs are binary values at m bits and the total number of inputs is 2 m, and the outputs are binary values at N bits and the total number of outputs is 2

  Therefore, identical output values

  port to different inputs can be obtained.

  Step 3: The sum of the input weight values at each node is obtained and the actual output is generated by the step function Here, equation (II) is used

for the step function.

  Step 4: the desired output value at the node

  output is compared to the actual output value obtained

  in step 3, thus calculating an error, and the variation of the weight value according to the error is stored. That is, the error <S is: S = desired output actual output and the change in weight value at W is at W = x input Step 5: After steps 2, 3 and 4 have been performed for each input and output pair, if all actual output values are equal to desired output values, the learning terminates, but if they are not, the total sum of the weight value variation t W is added to each weight value That is, the new value of weight (WT) is: WT = WT_i + w

  o T is equal to the number of learnings.

  Step 6: When the sum of the new weight value WT with respect to each node input is above a determined value M, the weight values WT are reduced to a predetermined rate That is to say that the weight value WT is reduced by the following equation WT '= WT x M (III) assuming that i WT> M and o WT' is the weight value obtained after

  the T learning processes have been carried out.

  Step 7: If the previous steps (from

  of step 2) have been repeated the number of times

  finished with a new WT weight value and without reaching the desired result, the current output layer becomes an inaccessible layer, the new output layer is incremented and then the process is repeated

  (starting with step 2) using the initial input

  together with the exit of the inaccessible beds

  directly as a new entry

of the new output layer.

  Thus, learning is done by an apprentice

  single-layer weaving, and if the desired output value is correctly obtained, the learning terminates However, if the learning has been repeated the number

  predetermined number of times, and if the result is still incor-

  rect, a layer is then added in the added new layer, the initial input and the actual output incomplete

  of the next directly inaccessible layer are used.

  as new inputs, and learning is repeated for the next layer At this time, the output layer for the first learning is changed to play the role of an inaccessible layer Thus, in the next layer, learning is repeated using the same method as learning the previous layer, but with more inputs by the number of outputs of the directly lower inaccessible layer During the learning process, each time an input

  is added, the variation of the weight value is memorized

  After all inputs have been applied, the sum of the changes in the total weight values is added to the weight value, thus obtaining a new value.

weight value.

  Here, the sum of the weight value to be compared to a neuron is greater than the predetermined value M, the equation (III) is applied with respect to each weight value to reduce them to a predetermined rate, thus limiting the sum of the weight values within the M value. An embodiment of a multi-layered neural network designed with respect to particular inputs and outputs by such training is shown in Figure 5A as shown in FIG. Figure A, the multi-layer neural network is realized

  with a CMOS inverter, and PMOS and NMOS transistors.

  In Figure 5A, a three-layer neural circuit pos-

he

  has a five-bit input and a three-bit output.

  Thus, an input layer LO has five neurons N 01 to N 05, and two inaccessible layers L1 and L2 each have three neurons N11, N12 and N13, and N21, N22 and N23, respectively, while that an output layer L 3 also has three neurons N 31, N 32 and N 33. Here, each neuron of each layer is a cascade of a pair of CMOS inverters INT 1 and INT 2 as shown in FIG. 5B, and is realized with a buffer circuit o an output node of the previous CMOS inverter INT 1 is an output node with NDB inversion and the output node of the CMOS inverter following INT 2 is an output node without ND inversion The synapse to connect each

  neuron of an input layer and each neuron of a

  output channel consists of PMOS and NMOS transistors

by the following method.

  If the training obtains a final connection weight which is positive, and if the input neuron IN receives a high logic signal (bit value = 1), the corresponding connection amplitude in the form of a first

  supply voltage (for example, the power supply voltage

  Vcc) is applied to the input node IND of the output neuron ON through the PMOS transistor B whose gate is common with the output node with NDB inversion, and for negative connection weight values, the connection is at a second voltage

  supply (eg mass or Vss) through the

  NMOS transistor C whose gate is common

  with the output node without ND inversion

  when the input neuron receives a low logic signal (input bit value = 0) and the connection weight is positive, the connection amplitude is in the form of the supply voltage Vcc applied by the PMOSA transistor whose gate is also common to the output node without ND inversion, while for negative weights, the connection amplitude is a mass potential or equal to the second

  supply voltage Vss, and is applied internally

  NMOSD transistor whose gate is connected to the

output node without NDB inversion.

  If the connection weight value is "0", no connection is made, regardless of the state

logic of the input bit.

  Using this method, an input synapse group 51 and transfer synapse groups 52 and 53 of FIG. 5 A consist of PMOS and NMOS transistors. Here, each LO layer neuron is connected to each input node of each neuron of the two inaccessible layers L1 and L2 and the layer of

  output L 3, via the synapse group of

  aforementioned treasure 51 in matrix Each neuron of the layer

  inaccessible Ll is connected to each input node of neu-

  of its immediately inaccessible layer next L 2 via the transfer synapse group 52 of the matrix Similarly, each neurone of

  the inaccessible layer L 2 is connected to each node of

  neurons in the L 3 output layer, through

  mediate the transfer synapse group 53 into a matrix.

  Also, all the neural input nodes of the two inaccessible layers L1 and L2 and the output layer L3 shown in FIG. 5A are polarized.

  at the second supply voltage Vss or GND by the

  intermediate of each polarization synapse group

  54 Since the 54 percent polarization synapse group

  the input node of each neuron to the second supply voltage Vss or GND when the input is not applied and thus polarizes each neuron output to "O", the polarization synapse group 54 consists of an NMOS transistor, wherein the first supply voltage Vcc is applied to the gate, the drain is connected to the input node of each neuron, and the second supply voltage (Vss or GND) is applied to source Here, the NMOS transistor for a polarization synapse has a geometric ratio (channel width (W) / channel length (L)) to have a connection amplitude equivalent to the unit weight value. For example, when the ratio W / L of the NMOS transistor is 2 μm / 2 μm as a unit weight value, the W / L ratio of the PMOS transistor becomes 5 μm / 2 μm. This is set considering the mobility ratio of an electron. relative to a hole and each weight value is a multiple of the unit weight value; this number being an integer Thus, the term "+ 1" in equation (II) is

  a constant considering the value of synapse of po-

  larisation. The embodiment applying the multi-layered neural network of the present invention as described above to the full two-bit adder and the sine wave generating circuit is as follows. Embodiment I Two-bit full add-on When the maximum value M of the sum of weight values of each node is 20 and 40, and the number of learnings is 300 and 500, the numbers of layers are as shown in the table. 1 and the result is

indicated on the list 1.

Table l

  LIST l The name of the input file is "a" The connection type is 2 Maximum weight sum = 20 Number of learning = 300 Initial weight value = O The maximum weight is used The displayed percentage is a variable unit The delta weight is uninitialized input / output

0 O O 0 1

C) O O 1 O

00 1 1

O 0 1 0 0

O O1 O 1

O 0 1 1 0

OO 1t 1

O 1110

0 1 0 C} O

0 1 001

1 00101

1 O 1 O

01 01 1

0 1 1001

01 1O t

01 11 0

01 11 1

1 0 0 O 1

t O O 1 0 1 1

1 0 1 0 0

1 01 O 1

1 011 0

11 1

1 1 O O

1100 1

1 0

1 101 1

11 1 01

  0 1 1 0 11 1 1 1 1 1 (Percentage of error)

3% 3% 15% 18% 25% 26%

% 21% 21 X 25% 21% 21%

% 21% 25% 25% 21% 28%

21% 28% 25% 21% 21% 28%

28% 25% 25% 21% 21% 25%

% 21% 21% 21% 25% 25%

21% 21% 25% 21% 21% 28%

21% 25% 25% 21% 28% 28%

28% 25% 21% 21% 28% 25%

% 25% 21% 21% 25% 25%

21% 21% 21% 25% 25% 21%

21% 25%

28% 28%

28% 25%

% 21%

256% 21%

21% 28%

28% 25%

% 21%

21% 21%

21% 25%

28% 25%

  % 21% 21%%% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 28 % 28% 21% 21%% 21% 28% 28% 26%% 28% 28%% 28%%% 28% 28%% 21% 28% 21% 21% 21% 21% 21% 21% 28% 28%%% 28% 28% Value 01 1 0 1 1 O 1 1 0 1 1 0 1 1 0 1 1 O 1 1 1 1 1 0 1 0 0 1 1 O 1 1 0 1 1 O 1 t 1 1 t 1 1 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 t 1 1 1 1 1 1 1 1 1 0 1 1 O 1 1 O 1 1 1 1 1 O 1 1 1 t 1 1 1 1 1

21% 28% 28%

28% -28% 25%

28% 25% 21%

% 25% 21%

% 21% 28%

28% 28% 25%

28% 25% 21%

% 21% 21%

% 21% 25%

21% 28% 25%

28% 25% 25%

% 21% 21%

  % 21% 21%%%% 21%%% 21% 21% 21%

% 21%

21% 21%

% 21%

% 21%

21% 21%

21% 21%

21% 25%

21% 21%

21% 28%

21% 28%

21% 25%

% 25%

  21%% 21% 28% 28%%% 28% 28%%% 21% h (actual output) layer number = O 3 4 3 3 i 4 4 4 4 4 j INPUT "1"

-1 -1 5 5 5 J

  21%%%% 21%%% 21% 21% 21% 21% 21% 21%%% 21% 21% 21% 21% 21% 21% 21%% 21% 28% 28%%% 28% 28% %% 21% 28%% 21% 21% 28%% 21% 28%% 21% 21% 28% 21% 21%% 21% 28% 21% 21%% 21% 21% 21% 2

-8 -2 -6 -1 -1

4 4 4 4 4 | "O" ENTRY

* 6 6 -2 -2 -2 J

new entry

000000 1

0 O O O '1 O t 1

0001 O O 1 1

01 1O 1 1

0 O 10101 1

00 1 1 1 1 1 1

0 1 O O O O 10

0 1 O 1 O O 1 1

0 1 O 1 1 O 1 1

0 1 1 O 1 1 1 1

0 1 1 1 O 1 1 1

1 O O 1 1 1 1 1

1O 1 O 11 1

1 101 11 1

1 O 1 1 O 1 1 1

11 1 1 11 1

1 1 O 1 O 1 1 O

1O 11 1 1 1

11111 1 11

3% 25% 25% 25% 21% 37%

46% 28% 31% 34% 50% 53%

46% 46% 59% 53% 50% 68%

46% 56% 56% 40% 43% 53%

28% 28% 21% 28% 25% 40%

53% 53% 62% 46% 50% 59%

46% 50% 62% 59% 50% 50%

% 46% 68% 59% 65% 46%

59% 50% 50% 68% 50% 59%

62% 71% 56% 53% 53% 46%

66% 28% 21% 34% 46% 62%

46% 46% 50% 53% 69% 53%

62% 59% 46% 50% 65% 59%

62% 50% 53% 65% 46% 46%

21% 50% 59% 56% 46% 34%

  28% 46% 46% 37% 59% 59%%% 62%% 46%% 59% 62% 34% 31% 43% 46% 28% 53% 43% 56% 43%% 37%%% 34% 59 %% 37%% 53% 59%%% 46% 59% 34% 59% 53%% 28%% 31% 43% 71%% 59% 34% 68% 56%%%%%%% 53% 43% 59% 43%% 46% 28% 59% 46%%% 34% 46%% 43% 56% 34% 46% 31% 34% 53% 46% 62% 46% 56%% 56% 46%%% 43 % 68% 3% 46%% 46% 56% 59% 59% 59% 56% 59% 59% 46% 59% 56% 31%

53% 59%

43% 50%

43% 71%

53% 46%

% 31%

56% 31%

56% 46%

% 43%

  53% value 01 1 0 1 1 1 00 0 1 1 1 10 0 11 1 00 1 10 1 O O 1 O O 1 00 1 1 O 1 1 1 of

46% 53% 50%

% 62% 59%

68% 71% 56%

34% 46% 53%

% 53% 53%

% 46% 43%

% 56% 65%

46% 62% 46%

  62% 68%% 46%% 46% 31%% 46% 43% 53% 53% 31% 59% 28%%

53% 62% 59% 66% 43%

% 50% 53% 68% 25%

56% 62% 62% 59% 68%

59% 62% 46% 59% 59%

28% 31% 43% 53% 62%

68% 65% 56% 50% 43%

31% 46% 46% 59% 62%

46% 50% 59% 59% 68%

h layer = 1

3 2 2 3

2 1 1 -5

3 1 1 -6

weight 2

-5 -2 -3 -1

-4 -2 -2 -1

-2 -2-3 -2

  -1 -5 -1 6 -2 4 0 O 1 2 1 -1 0 O 0 O 0 1% 43% 28% 62% 53% 56% 43%%% number new point

0 O O O O O O O

0 O O 0 1 0 1 0

0 O O 1 O 0 1 0 O O 0 I 1 O 1 0

0 0 1 O 0 0 1 O

0 0 1 O 1 0 1 1 O O 1 I0 O 1 t

0 O 1 1 1 1 0 0

0 1 0 0 0 0 1 0 O l o 01 0 1 O

0 1 O 1 0 O 1 O

0 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1

0 1 1 0 1 1 0 0

0 1 1 1 0 1 0 0 O 1 1 1 1 1 1 0

1 O O O O 0 1 0

1 0 0 0 1 0 1 1

1 o 0 1 O O I 1 1 O O t 1 1 O O

1 O I 0 0 1 O O

1 O I O 1 1 1 0

1 0 1 1 0 1 1 0

1 0 1 1 1 I 1 O

I 1 0 O 0 1 0 0

1 1 O 0 1 1 0 0

1 1 0 1 0 1 O O

I 1 0 1 1 1 1 0

1 1 1 0 0 1 1 O

1 1 1 O 1 1 1 0

1 t I t 0 1 1 O

I 1 1 I 1 1 1 1

  3% 25% 46% 56% 46% 6 56% 62% 62% 56% 50% 50% 59% 62%

  % 56% 62% 71% 560 71 X 65% 56 X 40% 62% 56% 71 X 71%

  62% 71% 56% 62% 71% 62% 71% 68% 56% 56% 71% 56% 71%

  71% 68% 59% 71 X 71% 59% 62% 68% 68% 43% 65% 62 i 50% 71% 65% 71% 56% 71% 68% 56% 68% t 1% 71 X 71% 59 % 71%

  % 78% 71 X 56% 71% 59% 50% 68% 62% 53% 25% 46% 71%

  68 X 81% 65% 59% 68% 56% 71% 71% 68% 71 X 71% 56 X 71%

  78% 75% 71% 65% 71% 34% 31% 65 X 71% 68% 68% 59 X 59% 78 X 71% 40% 56% 68% 71 X 71% 46% 26 X 566 71% 68% 65 %

  71% 71% 71% 68% 62% 78% 59 71% 68% 56% 68% 71 X 59%

  46 X 65% 71% 65% 71% 56% 71% 65% 65% 78% 68% 71% 65%

  68% 68% 65% 56 X 71% 71% 71% 65% 71% 71% 71% 81% 81%

  71% 849 87% 84% 96% 81% 62% 75% 90% 90% 84% 87% 93%

  71% 96% 87% 96% 96% 71 X 96% 87% 96% 93 X 78% 87% 93%

  84% 96% 87% 59% 84% 87 X 90% 846 87% 93% 71% 96% 87%

  96% 96% 71% 96% 87% 96% 93% 78% 87 X 93% 846 96% 87%

  59% 84% 87% 90% 84% 87% 93% 71% 96% 87% 96% 96% 71%

  96% 87% 96% 93% 78% 87% 93% 84% 96% 87% 59% 84% 87 X

  % 84% 87% 93% 71% 96% 87% 96% 96% 71% 96% 87% 96%

  93% 78% 87% 93% 84% 96% 87% 59% 84% 87% 90% 84% 87%

  93% 71% 96% 87% 96% 96% 71% 96% 87% 96% 93% 78% 87%

  93% 84%, 96% 87% 59% 84% 87% 90% 84% 87% 93% 71% 96%

  87% 96% 96% 71% 96% 87% 96% 93% 78% 87% 93% 84% 96%

87% 59%

value h 1 00 1 00 1 00 1 00

1 O 1

layer number 2

4 2 3 1 1 3 -2 -1

3 1 2 I 1-5 -1 1

-2-1 -2 -1 -1 4 3 3

weight 2

-4 -2 -3 -1 -1 -4 O -1

-3 -1 -2 -1 -1 5 2 O

2 2 1 21 -4-3 -3

new point

0 O 0100 01

0 to 110 10

0 01000 10

0 01010 11

0 1 O 11

0 01111 00

0 1000 O 01

0 10 O 10

0 10100 10

11,111

0 1 1000 11

011 11 00

0 11 O 1 00

01 1 1 1 O 1

1 00000 10

1 00010 11

1 00100 11

100111 00

01001 00

1 010 1 O 1

1 1 O 1

0 1 1 1 1 10

1 t O 1,000

110011 00

01 00

1 1O 1

11100 10 1

11 10 1 110

1 1 11 1 11 10

  96% 87% 87% 96% 81% 96% 96% 93%% 96 X 87% 3% 87% 87% 96% 84% 87% 93% 93% 96% 96% 96%% g 6% 96% 96 %% 96% 96% 96% 93% 96% 84% 78% 96% 96% 87% 96% 96% 96% 96% 93% g 6%% 96% 87% 96% 84% 96% 96% 93 % 96; 81% 96%

% 90 X 81% 87%

% 90% 96% 96%

87% 96% 96% 96%

96% 81% 96% 96%

96% 96% 96% 96%

93% 96% 96% 90%

81% 96% 96% 96%

96% 96% 93% 96%

879 96% 96% 90%

84% 96% 96% 96%

96% 96% 90% 96%

87% 96% 96% 87 X

96% 96% 90% 96%

96% 96% 815 78%

96% 90% 90% 96%

% 96 X 96% 96%

96% 93% 96% 96%

87 X 96% 96% 96%

96% 96% 93 X 96%

96% 84% 96% 96%

87% 96% 96% 96%

% 96% 96% 93%

86% 96% 100%

  value h 0 O O O O 1 O O 1 0 1 O 0 1 O 0 1 1 0 t 1 1 O O -0 to -00 O 000000 a

9 Q ç O O ç 000 00 00 -O

O O O O O

I-I-C-0 I

At N C

I I

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EMBODIMENT II

  Generating circuit of a sinusoidal curve The number of layers is represented in Table 2 under the same conditions as in embodiment I,

  and the results are shown on List II.

Table 2

  i sages 300 I 500 I r \ Number of apprentices IM \ l t y___ _ + ___ + _

I 20 I 4 4 1

2

  I 3 I 2 l List II Input file name is "s" Connection type is 2 Sum max weight = 20 Learning number = 300 Initial weight value = 0 Maximum weight is used Percentage displayed is a variable unit Weight uninitialized Delta input / exit 0 o O o 00 00 00

0 O O1 00 1 1

o O 1 O 0101

0 O 1 1 1000

0 1 O O I o 1 O

1 O 1 1011

o 1 1 0 1101

0111 1110

1000 1111

1001 1111

(Percentage error)

  % 10% 10% 30% 30% 50% 20% 30% 30% 50% 30% 40% 40%% 40% 50% 60% 50% 40% 60% 40% 40% 60% 60% 40% 50%

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ú 9

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0000000000000000 000000000000000 O

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O O O O O O CO O O O O O C 000000

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% 60% 80% 80% 60% 80% 80%

  valueh oo 0000 number of layers = 2

4 4 4 4 O O O

6 1 4-1 O 5 O O

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0 O O O -10 1 -2 3

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  value h 1 t 1111 number of layers = 3

4 4 4 4 0 0 0 0

O 4-1 0 6 -1 O

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3 -1-4O O 3 -1 4

weight 2

-1 -1O O -10 O -2 3

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-3 -32 -3 -1 O -4 O

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recall 101 l 1 O 1 0 0

1 0 1 0

  1 t 1 0 Input file name is "s" Connection type is 2 Sum max weight = 40 Number of learnings = 300 Initial weight value = O Max weight is used Percentage displayed is a variable unit Weight Delta is uninitialized 00 o 00 0000

0 00 1 00 1 1

O O 1 0 0 101

00 1 1 O 00

1010

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*% 50%

h value

1 O 00

11 ii number of layers = O

9 9 10

18 8 12 O

10 -8 10

4 4 9

weight 2

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v 0000005-

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O 0000000000 0000000 00000

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R E VE N DICA T ION S

  1 Neural network with multiple layers receiving

  an input with m bits and generating an output with N bits,

  characterized in that it comprises a neuron for cascading a pair of CMOS inverters and having an output node of the previous CMOS inverter from the pair of CMOS inverters as an output node with inversion of the CMOS inverter. this, and an output node of the next CMOS inverter as an output node without inverting an input layer (LO) having m neurons for receiving said m-bit input; an output layer (L 3) having N neurons for generating said N-bit output; at least one inaccessible layer (L1, L2) provided with N neurons in order to transfer the input received from said input layer (LO) to the directly higher inaccessible layer or to said output layer (L 3); an input synapse group (51) in a matrix having each predetermined weight value for connecting each neuron output to said input layer (LO)

  at each neuron of said output layer (L 3) and the

  said at least one inaccessible layer; at least one transfer synapse group (Sl, 52)

  in a matrix having each predetermined weight value

  mine to connect each neuron output of the inaccessible layer to each neuron of its directly higher inaccessible layer or of said output layer (L 3); and a synapse bias group (54) for biasing each neuron input node of said at least one inaccessible layer and said output layer

(L 3).

  Multilayer neural network according to claim 1, characterized in that said input synapse group (Sl) applies supply voltages to each neuron input node of said output layer (L 3) and said at least one inaccessible layer such that, when an input bit value received in each neuron of said input layer (LO) is "1", if a connection weight value is positive, a first voltage power supply is applied with an amplitude of

  connection of said connection weight value by the

  PMOS transistor whose gate is connected to each output node with neuron inversion of said input layer (LO) and, if a connection weight value

  is negative, a second supply voltage is applied

  with a connection amplitude of said connection weight value through an NMOS transistor whose gate is connected to each output node without neuron inversion of said input layer (LO), when a value of input bit is "O", if a connection weight value is positive, a first supply voltage is applied with a connection amplitude of said connection weight value via a PMOS transistor whose the gate is connected to each output node without neuron inversion of said input layer (LO), and if a connection weight value is negative, -a second supply voltage is applied with a connection amplitude of said connection weight value via an NMOS transistor whose

  the grid is connected to each output node with invert-

  neuron sion of said input layer (LO), and when said input bit value is "1" or "0" and a connection weight value is "0", no connection is made, and in that said transfer synapse group is made up of PMOS and NMOS transistors in order to connect each node of

  output with and without inversion layer neuron inversion

  sible to each neuron input node of the output layer (L 3) or of the directly higher inaccessible layer of said inaccessible layers (Li, L 2) according to the same method as said input synapse group (51). ).

  3 Multi-layered neural network according to the

  claim 2, characterized in that said bias synapse group (54) is constituted by an NMOS transistor

  whose gate is connected to said first supply voltage

  ment to polarize the input node of each neu-

  of said output layer (L 3) and said at least one

  a layer inaccessible to the second voltage of

  as the connection amplitude of a value of

unit weight.

  4 Multi-layered neural network according to the

  claim 3, characterized in that the connection amplitude of each weight value of said synapses is determined by a geometric ratio of a MOS transistor (width

channel / channel length).

  5 Multiple layer neural network according to the

  1, characterized in that each weight value

said synapses is an integer.

  6 Multiple layer neural network according to the

  claim 1, characterized in that the sum total of weight values of synapses connected to each node

  neuron input of the output layer (L 3) or of the-

  said at least one inaccessible layer is less than the input value of the preceding CMOS inverter of said neuron.

  In the multi-layered neural network

  7 cevis a m bits input and generating an output N bits, comprising: a neuron to cascade a pair

  CMOS inverters and having an output node of the in-

  the prior CMOS transponder of said pair of CMOS inverters as an inverting output node and an output node of the next CMOS inverter as a non-inverting output node; an input layer (LO) having m neurons for receiving said m-bit input; an output layer (L 3) having N neurons for generating said N-bit output; at least one inaccessible layer (L1, L2) provided with said N neurons in order to transfer the input received from said input layer (LO) to the directly higher inaccessible layer or said output layer (L 3); a synapse input group (51)

  in a matrix having each predetermined weight value

  mine to connect each neuron output on said input layer (LO) to each neuron of said output layer (L 3) and said at least one inaccessible layer; at least one transfer synapse group (Sl, 52) in a matrix having each predetermined weight value

  to connect each neuron output of the inacces-

  to each neuron in its layer inaccessible directly

  upper layer or outlet layer (L 3); and a synapse group of polarization (54) to polarize

  each neuron input node of said inactivated layers

  assignable (L1, L2) and said output layer (L3),

  the circuit design process of a re-

  multi-layered neural bucket characterized by comprising: a first step of initializing the connection weight value of said input synapse group (S);

  a second step of setting the value of

  m bits and a desired N-bit output value corresponding to the input value; a third step of obtaining the sum of the input weight values on the input node of each neuron of said output layer (L 3) and of generating a real output by a step function; a fourth step of comparing the actual output value obtained during said third step,

  said desired output value set during the se-

  step count for calculating the error, and storing the variation of the calculated weight value according to the error value;

  a fifth stage of apprenticeship termination

  wise if each output value is equal to its desired output value, or if it is not, to obtain the sum of the stored variations of the weight value and its addition to each current weight value to obtain a new weight value after said second to fourth steps have been performed with respect to 2 m input and output pairs; a sixth step of reducing each weight value by a predetermined ratio, when the sum of the new weight value obtained during said fifth step in the input node of each neuron of said output layer (L 3) is above a predetermined value; and a seventh step of using said layer

  (L 3) as an inaccessible layer, to increase

  tation of the new output layer, and repetition of the process starting with said second step using the output of the immediately inaccessible layer immediately below and the initial input as new inputs, when the desired result is not obtained after repetition of learning until the sixth step by

  the predetermined number of times of repetitions.

  8 Circuit design method of a neutral network

  multilayer film according to claim 7, characterized

  in that said step function is given by the following numerical expression: N-1 Yi = 1 Efh (Wi Xi G) + 1 i = 1 fh: non-linear function with fixed limit Wi: weight value Xi: input Yi : G output: output layer neuron threshold value 9 Network circuit design process

  multi-layer neural system according to claim 7,

  characterized in that during step 6, the said new

  the weight values are reduced by the following numerical expression: M W = W x

T 5 'WT

  w T WT: new weight value obtained after T learning WT: sum of weight value applied to the neuron output node of the output layer

(L 3)

  M: exit layer neuron input value (constant)