FR2663147A1 - Floating-gate dual-transistor programmable memory - Google Patents

Abstract

The invention relates to electrically programmable and erasable non-volatile memories (EEPROM). In order to reduce the control circuitry required for programming and erasing memory slots, the invention proposes to render the actual memory slot more complex: each memory slot consists of two floating-gate transistors (TGF1, TGF2) storing complementary information. The drain of one is connected to the gate of the other, only in write mode, by a respective link transistor (T3, T4). In read mode the link is broken. Erasure and programming can be undertaken in a single step for a specified word. The invention is particularly relevant to memories of small capacity (for example 64 bits) in which the size of the control circuitry is much greater than that of the memory slots itself so that there is advantage in having more sizeable memory slots if this makes it possible to save a great deal in the size of the control circuitry.

Description

PROGRAMMABLE MEMORY WITH DOUBLE TRANSISTOR
FLOATING GRID
The invention relates to non-volatile, programmable and electrically erasable memories, known under the usual name EEPROM.

 In recent years, these memories have experienced significant growth thanks to their ease of erasure, compared to EPROM type memories which can only be erased by ultraviolet illumination.

 But this advantage for the user has for counterpart, for the manufacturer, the fact that the circuitry necessary for the erasure and the reprogramming is complex.

 In fact, these memories use floating gate transistors in which the programming of a bit consists in storing electrical charges on the floating gate. Programming and erasing pass the loads through insulating layers which separate the floating grid from the rest of the circuit. Relatively high voltages (of the order of 20 volts today) must be applied for programming or erasing.

 On the one hand, these voltages must be correctly routed either towards the gate or towards the drain of the floating gate transistors constituting the memory points, this depending on the desired operation on a determined point. The decoding and routing circuits are complex.

 On the other hand, these voltages are higher than those which the usual transistors of integrated circuits can normally bear. To apply the voltages of 20 volts to the desired locations, either in programming or in erasure, there must therefore be switching circuits which must be specially designed to allow voltages of 20 volts and not voltages of 5 volts that 'we usually find in integrated circuits. These switching circuits are more bulky and complex than circuits operating with voltages of 5 volts.

 This is why the EEPROM memories include cumbersome programming and erasing control circuitry.

 On the basis of the present invention, there is first of all the remark that this bulk is all the more troublesome as the memory comprises a smaller number of memory points. For a memory with a very large number of points (for example 256 kbits) the surface of the memory points occupies for example 50% of the total surface of the circuit, and the control circuits also 50%. But for a memory with a small number of points, for example 64 bits, the proportion is 10 t for the memory points and 90% for the control circuitry. It is therefore important to pay close attention to the design of this circuitry if we want small capacity memories to remain interesting.

The invention proposes a means for reducing the complexity of the circuitry for controlling the memories.
EEPROM.

 It is proposed to modify the memory point by using for each memory point two floating gate transistors having their sources connected together and capable of memorizing complementary states, the gate of each of the two transistors being connected to the drain of the other transistor by the via a respective connection transistor, control means being provided to make the two connection transistors conductive in write mode (programming or erasing of the memory point), and to block them in read mode.

 Each floating gate transistor is preferably in series with a respective selection transistor making it possible to connect, for a memory point belonging to a selected word, the drain of each of the floating gate transistors to a respective bit line.

 More preferably, the sources of the floating gate transistors are connected to the drain of a bias transistor whose source is grounded. This transistor is individual for the memory point, or it is collective for several points, even for an entire row or an entire column or even for all of the memory points. It is made conductive or blocked by a command line defining whether one is in reading mode or on the contrary in programming or erasing mode. This mode command line defines the mode for all memory points; in read mode, it controls the grounding of the sources of the floating gate transistors for all of the memory points. In programming or erasing mode, it places the sources of the floating gate transistors at high impedance.

 More preferably, the memory includes means for applying to the gates of the floating gate transistors, in reading mode, a reading voltage. These means can consist of an individual transistor connected between on the one hand a line supplying the reading voltage and on the other hand the control gate of a floating gate transistor.

However, this transistor can be common to several floating gate transistors connected to the same bit line (or common to all this line).

 In the form of a method for memorizing information, the invention can be summarized as follows: the method is a method for non-volatile memorization of electrically erasable and programmable information in a network of memory points, and it is characterized in that the information is stored in each memory point in the form of two complementary states in two respective floating gate transistors, each floating gate transistor having, in programming and erasing mode, its gate connected to the drain of the 'other by a respective connection transistor which can be blocked in reading mode.

Other characteristics and advantages of the invention will become apparent on reading the detailed description which follows and which is given with reference to the appended drawings in which
- Figure 1 shows the structure of a conventional memory point EEPROM floating gate memory;
- Figure 2 shows the structure of a memory point and corresponding control means in a memory according to the invention.

 - Figure 3 shows an alternative embodiment of the memory point according to the invention.

In Figure 1, a conventional memory point is shown comprising a floating gate transistor
TGF and a selection transistor TS. This is the typical memory point for EEPROM memories.

 The two transistors are in series.

 The drain of transistor TS is connected to a bit line BL used to read or write information in the memory point. The bit line is connected to all the memory points in the same column.

 The source of transistor TS is connected to the drain of transistor TGF.

 The gate of the transistor TS is connected to a word line WL making it possible to select a word or an entire row of memory points.

 To program, erase and read such a memory point, it is necessary to apply well-defined voltage combinations on the gates of the two transistors, as well as on the drain of the selection transistor. Other combinations are necessary to protect the storage state of a determined memory point while other memory points belonging to the same row or column are being programmed or erased.

 As an indication, we can establish the following table, representing the voltages to be applied to a determined memory point to erase it (memorization of a state 0 by evacuation of the charges contained in the floating grid) or to program it (injection of charges in the floating grid: storage of a state 1).

Vd is the voltage on the drain of TS, applied by the bit line BL;
Vw is the voltage on the grid of TS, applied by the word line WL;
Vgf is the voltage on the control gate of the floating gate transistor, applied via a transistor TP which is not part of the memory point but which is common to a whole column of points;
Vs is the voltage on the source of the transistor TGF, applied through a transistor TM which is common to several memory points.

Vgf Vd Vw Vs
Erasure: 20v 0 20v 0
Programming: 0 20v 20v high
impedance
Reading: 1.5v 1.5v 5v 0
From this table it follows that the writing of information in the points of a line, selected by the word line WL, requires both the choice of an appropriate voltage on the bit line BL (20 volts or 0 volts depending on whether it is an erasure or a programming) and the choice of a corresponding complementary voltage on the drain of the transistor
TP (0 volt or 20 volt). And in addition, the control of the transistor TM is not the same depending on whether you erase or program. Consequently, the write command is complex since each item of information written requires a double voltage switching: towards the drain of the transistor TP of a column, towards the bit line BL.

 On the other hand, we are forced in practice to write twice: we erase everything, then we only carry out programming for the points that must be programmed, the others remaining erased.

This double step is an annoying waste of time.

 Furthermore, the switches required in the read control, programming and erasing circuitry are especially bulky because of the fact that voltages of 20 volts must be able to be switched.

 To reduce the complexity and size of the control circuitry, a double memory point is proposed according to the invention, that is to say comprising two floating gate transistors connected together; part of the switching circuits is then located in the memory point itself, but what is important is that these switches are no longer controlled as a function of the information to be entered. They are only controlled according to the operating mode: read or write.

 The two floating gate transistors store complementary logic states: when one is erased, the other is programmed. And, in writing mode (programming or erasing), the drain of one of the transistors is connected to the gate of the other, which makes it possible to apply to one of the transistors the drain and gate voltages which are complementary to the corresponding voltages of the other transistor.

 This is what makes it possible to simultaneously program and erase by routing a single voltage (or more precisely two systematically complementary voltages) to the memory point and not several different independent voltages.

 An exemplary embodiment of the memory point according to the invention is given in FIG. 2. There is a first floating gate transistor TGF1 in series with a first selection transistor TS1; and a second floating gate transistor TGF2 in series with a selection transistor TS2.

 The selection transistors are controlled by the same word line WL. But instead of having their drains connected to a single bit line, the first (TS1) has its drain connected to a bit line BL1 and the second has its drain connected to an auxiliary bit line BL2.

In programming or erasing mode, we will see that the logic level present on line BL1 is always complementary to the level present on line BL2, so that there is no provision for a controlled switch but only one inverter to supply line BL2.

In read mode, it is the imbalance between lines BL1 and BL2 which is read to detect the information stored in the memory point.

Two connection transistors T3 and T4, controlled simultaneously by a line CS, are provided in the memory point. The transistor T3 makes it possible to connect the drain of the first floating gate transistor TGF1 to the gate of the second TGF2; conversely, the transistor
T4 makes it possible to connect, under the control of the same line CS, the drain of the transistor TGF2 to the gate of the transistor TGF1.

 The command line CS is active (transistors T3 and T4 made conductive) in write mode, that is to say programming and erasing. It is inactive (transistors T3 and T4 blocked) in read mode.

The sources of the floating gate transistors are connected together and connected to the drain of a transistor.
T5 whose source is connected to ground (Vss). The conventional function of transistor T5 is the grounding or high impedance of the source of the floating gate transistors. It is controlled by a line CS * whose state is permanently complementary to that of the line CS, that is to say that the transistor
T5 is conductive in read mode (sources of TGF1 and
TGF2 grounded) and blocked (sources of
TGF1 and TGF2 in high impedance) in write mode. The transistor T5 is not necessarily individual for the memory point considered: it may very well be common to a whole group of points, for example a row or a column or even the entire memory plane. It has however been represented in the point memory itself since its presence is essential to understanding the circuit.

 Finally, two additional transistors T6 and T7 are provided to direct a reading voltage VL towards the gates of the floating gate transistors. These transistors are both made conductive by the line CS * which controls their gates. The transistor T6 connects the gate of TGF1 to the voltage VL; the transistor T7 connects the gate of TGF2 to the voltage VL. Here again, the transistors T6 and T7 are not necessarily part of a specific memory point: they can be common to several floating gate transistors connected to the same bit line (or common to this whole line). However, a transistor T6 or T7 cannot be common to two different bit lines, and in particular not common to lines BL1 and BL2.

The memory point therefore generally comprises six transistors: the two floating gate transistors
TGF1, TGF2, the two selection transistors TS1 and
TS2, and the auxiliary connection transistors T3 and
T4. And the memory includes command lines or potential supply lines
- the word line WL (conventional) which controls the selection of a word or of a whole row of dots and which is connected to an address decoder making it possible to select the desired word or row;
- a bit line BL1 (conventional) connected to an entire column of memory points;
- an auxiliary bit line BL2 which carries, in programming and erasing mode, logical levels complementary to those transmitted by the line BL1 (0 volts if there is 20 volts on
BL1 and 20 volts if there is 0 volts on Bol) ;;
- a CS command line for programming and erasing, which is not linked to a row or a column of memory points but which can be used for the entire memory plane (which means that it can be brought up indifferently by a physical row or column, unrelated to the addressing of a row or column of memory points);
- a CS * read command line which carries a level complementary to that of the line
CS and which can also be used for the entire memory plan;
- And finally, a line for applying the reading voltage VL, and a line for bringing the voltage Vss to ground; these two lines are also not linked to the addressing of a memory point and can therefore also be brought indifferently by a row or a column.

Now, to apply the erasing and programming voltages, simply bring the desired voltage to the bit line BL1 (and a complementary level systematically on the auxiliary line
BL2).

 In addition, we will see that writing a selected word can be done in a single step; it is not necessary to erase the entire word first before programming the points of the word which must be programmed.

The detailed memory operation is as follows
A. In erasure.

 The CS mode command line is brought to a potential level Vpp, Vpp being the programming voltage, for example of 20 volts. The line CS * is brought to earth (0 volts).

 The word line WL is brought to Vpp for the words to be deleted. It remains at 0 for the others. The bit line BL1 is brought to 0 (Vss) for the words to be erased; on the contrary, the auxiliary bit line BL2 is brought to the programming voltage Vpp.

 As a result, the sources of the floating gate transistors are at high impedance (transistor T5 blocked). The transistors T3 and T4 are both conductive. The transistor TGF1 receives on its drain, by the line BL1, a zero voltage, and it receives on its control gate the voltage Vpp, by the line BL2 and the transistor T4.

 Furthermore, the transistor TGF2 is blocked because its control gate is brought to Vss (through BL1 and the transistor T3). The source of the TGF1 and TGF2 transistors therefore remains at high impedance.

 The transistor TGF1 is then in erasure conditions since its drain is at Vss and its control gate at Vpp.

 During this time, the transistor TGF2 has on the contrary its drain at Vpp and its gate at Vss, its source being at high impedance. It is in programming conditions and its floating grid loads accordingly.

 We arrive at the following state: the transistor TGF1 is erased and the transistor TGF2 programmed. The transistors of words not selected by the word line WL are not affected since their drains, their grids and their sources remain at high impedance (blocking by the selection transistors TS1 and TS2).

 The "erased" state of the memory point will therefore be characterized by an erased state of the transistor TGF1 and a programmed state of the transistor TGF2.

 B. In programming.

In programming, there is always the application of the command CS to Vpp and of the command CS * to 0; the selection of a word to write is done by the word line
WL brought to Vpp for the word to write, to Vss = 0 for the others.

 This mode is symmetrical to the previous one, in the sense that a voltage Vpp is now applied to the bit line BLI and a complementary voltage Vss to the auxiliary line BL2. The transistor TGF1 is then programmed at the same time as the transistor TGF2 is erased. The transistors of unselected words are protected: they do not receive a voltage Vpp, neither on their gate nor on their drain.

 The "programmed" state of the memory point is therefore characterized by a programmed state of the transistor TGF1 and an erased state of the transistor TGF2; it is the complementary state of the preceding.

 C. In playback mode.

In read mode, the command line is inverted
CS which passes to Vss while CS * passes to a complementary logical level.

 Note that the physical voltage level on CS * need not be 20 volts. It can be equal to a classic Vcc level of 5 volts or less. Indeed, in reading mode we no longer use the programming voltage Vpp and we only work with voltages below 5 volts in general. It therefore takes voltages of 5 volts to control the voltage transmissions on the lines.

 The transistors T3 and T4 are blocked and therefore disconnect the gate-drain links between the floating gate transistors. The transistor T5 is made conductive and earths the sources of the floating gate transistors TGF1 and TGF2.

 Finally, the transistors T6 and T7 are made conductive and apply the reading voltage VL to the control gates of the floating gate transistors.

 The bit lines BL1 and BL2 are no longer supplied by additional logic levels; they are initially preloaded at a voltage Vpch common to the two lines.

 The reading voltage VL can be of the order of 1.5 volts. The precharge voltage Vpch can be of the same order.

A control voltage (for example Vcc) is applied to the word line WL corresponding to a word to be read, to make the transistors TS1 and
TS2 of the selected word.

According to the programming state of the memory point ("programmed" state in which the floating grid of
TGF1 has been programmed and that of TGF2 erased, or "erased" state in which the gate of TGF1 is erased and that of TGF2 programmed), a differential amplifier connected to the bit lines BL1 and BL2 will switch in one direction or another and will detect the stored information.

 Note that erasing and programming can be done simultaneously. Indeed, the sources of the transistors TGF1 and TGF2 remain at high impedance; and there is necessarily Vpp on a transistor gate and Vss on the other, as well as Vss on a drain and Vpp on the other, this by choosing only a voltage value (that of line BL1, and by deduction that of line BL2).

 The memory structure according to the invention is particularly advantageous for low capacity memories in which the area of the switching circuits of the voltages Vpp is much greater than the area of the memory points themselves: the memory point according to the invention is more bulky than a conventional point since it comprises two floating gate transistors, but it makes it possible to considerably reduce the surface of the control circuits since the only voltage to be switched bit by bit in write mode is the voltage Vpp or 0 on the line BL1.

An alternative embodiment of the invention, represented in FIG. 3, consists in connecting the transistor T3 between the drain of the selection transistor
TS1 and the TGF2 grid; and the transistor T4 between the drain of TS2 and the gate of TGF1. The only difference in writing mode is that, for unselected words, the floating gate transistors have a voltage of 20 volts or 0 volts on their control gate. But since they have their source and their drain in high impedance (isolated by TS1, TS2, T5), they are not likely to be programmed or erased.

Claims (9)

 1. Electrically erasable programmable non-volatile memory, characterized in that each memory point comprises two floating gate transistors (TGF1, TGF2) having their sources connected together and capable of memorizing complementary states, the gate of each of the two transistors being connected to the drain of the other transistor via a respective connection transistor (T3, T4), a control means (CS) being provided to make the two connection transistors conductive in write mode, and for them block in read mode.  2. Memory according to claim 1, characterized in that each floating gate transistor is in series with a respective selection transistor (TS1, TS2) making it possible to connect, for a memory point belonging to a selected word, the drain of each of the floating gate transistors to a respective bit line (BL1, BL2).  3. Memory according to claim 2, characterized in that the sources of the floating gate transistors are connected to the drain of a bias transistor (T5) whose source is grounded.  4. Memory according to claim 3, characterized in that the bias transistor is collective for several memory points.  5. Memory according to one of claims 3 and 4, characterized in that the bias transistor is made conductive or blocked by a control line (CS *) defining whether one is in reading mode or on the contrary in mode writing.  6. Memory according to one of the preceding claims, characterized in that it comprises means (T6, T7) for applying to the gates of the floating gate transistors, in reading mode, a reading voltage (VL).  7. Memory according to claim 6, characterized in that the means for applying a voltage comprise a transistor connected between on the one hand a line supplying the reading voltage and on the other hand the control gate of a floating gate transistor .  8. Memory according to claim 8, characterized in that the transistor used to apply the read voltage is common to several floating gate transistors connected to the same bit line.  9. A method of non-volatile storage of electrically erasable and programmable information in a network of memory points, characterized in that the information is stored in each memory point in the form of two complementary states in two respective floating gate transistors (TGF1 , TGF2), each floating gate transistor having, in programming and erasing mode, its gate connected to the drain of the other by a respective connection transistor (T3, T4) which can be blocked in read mode.