FR2660133A1 - Method of scrambling, of unscrambling and of searching for synchronisation in a binary train and circuit for implementing this method - Google Patents

Abstract

The invention relates to a method and a device for unscrambling a train of binary data. The binary train to be transmitted (TBT) consists of fixed-length (L) words (MB), in which one of the fixed-position (F) elements has a fixed value (0). It is scrambled with a fixed-length pseudo-random binary sequence (SBPA) (PRBS), and transmitted. The received train (TBER) is unscrambled with the aid of an identical pseudo-random sequence. Each element of the first word received (MB1) is compared with the element of the same rank of the second word received (MB2). The elements are selected which, in the words received, occupy the same rank and have the same fixed value (0) of the fixed-position (F) binary element, and the said comparison is continued until only one single selected element remains, which is therefore the fixed-position element (F) sought. The invention can be used, in particular, in data transmission systems.

Description

 The subject of the present invention is a method of scrambling, descrambling and seeking synchronization of a bit stream as well as circuits allowing the implementation of this method. It is applicable in data transmission systems.

 In data transmission systems, it is necessary to avoid the transmission on the line of long series of O or 1. Indeed, for example, the transmission of a long series of binary elements to O results in a long period of absence of oscillations on the line. The repeater connected to this line then no longer receives any reference and reset signals from its clock circuit. It therefore becomes necessary to provide an ultra-efficient clock circuit, which significantly increases its cost.

 To overcome such drawbacks, one solution consists in scrambling the data to be transmitted in order to obtain a binary train in which the number of binary elements O and the number of binary elements at 1 are substantially identical, these elements being also distributed in the train.

 On reception, this stream of binary elements must be descrambled in order to reconstitute the initial data stream.

 The present invention therefore relates to a method meeting the above mentioned requirements and a circuit allowing the implementation of this method.

The method of scrambling a binary data stream to be transmitted, descrambling and synchronization search for this scrambled binary data stream transmitted and received which is the subject of the invention is characterized in that it consists in :
- split the data stream to be transmitted into words of fixed length
- give one of the binary elements of fixed position a fixed value in all the words of said train
- scrambling said data stream with a pseudo-random binary sequence of fixed length in order to obtain a scrambled binary data stream to be transmitted;
- transmit said scrambled train;
- descramble the binary data stream received using a pseudo-random binary sequence identical to said pseudo-random binary sequence used for 'scrambling ;;
- compare each bit of the first word received with the bit of the same rank of the second word received;
- select the binary elements which, in the first two and second words received occupy the same rank and have said fixed value of the binary element of fixed position;
- Compare each of the selected bits with the respective bits of the same rank of each of the following received words and select, after each comparison, only the bits which, in each word, occupy the same rank and have said fixed value;
- Continue said comparison until there remains only one selected binary element which is therefore said binary element of fixed position sought.

The descrambling and synchronization search circuit making it possible to implement the method of the invention is characterized in that it comprises in particular:
- a fixed length pseudo-random binary sequence generator;
- a logic gate performing the EXCLUSIVE OR function, one input of which is connected to an output of said pseudo-random binary sequence generator and another input of which is controlled by the received binary data stream;
- a shift register, an input of which is connected to an output of a gate performing the OR logic function and an input of which is connected to an output of said gate performing the OR logic function
EXCLUSIVE and of which another input is connected to an output of this register
a counter, a counting input of which is connected to the input of the shift register via a gate controlled by a clock signal reconstructed by a clock circuit from said scrambled binary data stream received, a reset input of this counter being connected to an output of a door, the inputs of which respectively receive an initialization signal and a word count signal from said clock circuit;
a demultiplexer, one input of which is connected to an output of the counter and the outputs of which are connected to an input of respective logic gates controlled by said word count signal to respectively supply inhibition signals retransmitted to an input of said sequence generator pseudo-random binary, synchronization found, and further search for synchronization.

The main objects and characteristics of the invention will now be detailed in the description which follows, given by way of nonlimiting example, with reference to the appended figures which represent:
- Figure 1, an example of constitution of a binary train of words of fixed length scrambled with a pseudo-random sequence, according to the invention;
- Figure 2, a diagram illustrating the principle of synchronization search of the invention;
- Figure 3, an exemplary embodiment of a reception circuit for implementing the principle of synchronization search of the invention.

 Firstly, with reference to FIG. 1, the principle of scrambling a binary train of words of fixed length will be described, in accordance with the present invention.

 According to the principle of the invention, the binary train to be transmitted TBT is composed of words MB of fixed length, L binary elements according to the example chosen. One of the L bits of each word, in a predetermined fixed position F, has a fixed value. To simplify the description, by way of nonlimiting example, this binary element will be the first (represented at the right end of each word in the diagram of FIG. 1) of each word and it will have the value 0. The L- 1 other binary elements of each word take, according to the information to be transmitted, sometimes the value 0, sometimes the value 1. They are represented by X in the diagram of Figure 1, where the data to be transmitted are illustrated on the first line .

Before transmission on a transmission line, this binary train
TBT is confused with a fixed length SBPA pseudo-random binary sequence. The reception circuits, as will be seen later, know the characteristics of this sequence.

 We therefore obtain a scrambled binary element train to transmit TBEE consisting of words of L binary elements obtained by performing binary element to binary element the logical operation "EXCLUSIVE OR" of the pseudo-random sequence SBPA and the binary train to transmit TBT .

 In the diagram of FIG. 1, the train of scrambled binary elements to transmit TBEE consists of elements X, Y, O and 1.

Binary elements X are the result of the "OR
EXCLUSIVE "of the elements X of the binary train to be transmitted TBT and of the elements 0 of the pseudo-random sequence SBPA. The binary elements Y are the result of this same operation of the elements X of the binary train to be transmitted TBT and of the elements 1 of the sequence SBPA The binary elements 0 and 1 are respectively the result of the "EXCLUSIVE OR" of the binary elements at value 0 of the TBT bit stream and of the respective binary elements 0 and of the sequence SBPA.

 After this scrambling, the sequence of binary elements F therefore provides a certain sequence.

 The receiving circuits must recognize this sequence.

 When these reception circuits are synchronized, that is to say when the received binary elements are in turn the object of the logical operation "OR EXCLUSIVE" with the binary element of the same rank of the pseudo-random sequence SBPA that the one which was used for the scrambling, the result of this descrambling, for each word, is a sequence made up of a binary element with 0 and Ll elements having a value of 0 or 1, called X, as one saw it previously.

 We will now describe, also referring to FIG. 2, the principle of the search for synchronization.

According to the method of the invention, one writes in a register RG to
L stages a first descrambled MB1 sequence of L binary elements.

Among these L binary elements is the element F which, according to the example chosen, is the first of each word of length L, this element being at 0.

In order to reconstruct the words of the descrambled train, it is therefore sufficient to identify this binary element. All the binary elements with 0 written in the register RG, and only these, can be this element F sought.

 The diagram in FIG. 2 shows an example of the constitution of 4 words MB1 to MB4 of 6 binary elements received and the content MB1, MC1, MC2, MC3, of the register RG after the reception of each of these words.

 During the reception of the second sequence of L descrambled binary elements, each of these L binary elements is compared to the binary element of corresponding rank of the first sequence written in the register RO: when the two compared binary elements are at 0 one writes (or one maintains) 0 in the corresponding stage of the register RG. In all other cases, we write 1 in the register RG. Indeed, the binary element F which occupies the same position in all the words of the data stream is always a binary element at 0. After this first comparison, it is possible to eliminate all the stages of the register RG in which elements are written binaries 1.

 The preceding operation is repeated during the reception of the third series of L descrambled binary elements each compared to the binary element of corresponding rank of the word registered in the register RG, this word no longer being a "data word" MB but the first "word of comparison11 MC1.

 The second comparison word MC2 obtained will include a number of binary elements at 0 less, or at most equal, than the number of binary elements at O contained in the first comparison word.

 After the reception of a predetermined number S (4 according to the example illustrated in the diagram of FIG. 2) of sequences of L binary elements, therefore after Sl comparisons, the comparison word, MC3 according to the chosen example, can include several binary elements at 0. All, can be the element F sought. We then begin a second cycle of comparisons.

 The comparison word MC3 can have only one binary element O, as shown in the example chosen, illustrated by the diagram in FIG. 2. This element can be the element F sought. Depending on the case, it is considered that this element is indeed the element F, or else, one or more additional comparisons are carried out to confirm that the binary element identified is indeed the element F sought.

 The comparison word can also contain only binary elements at 1: the element F of each word has not been identified due to poor synchronization of the binary train received and of the pseudo-random sequence SBPA.

 One then proceeds to an offset, or sliding of a binary element of the SBPA sequence and one continues the comparisons. This sliding of the sequence can be achieved, for example, by suppressing a clock pulse.

 We will now describe, with reference to FIG. 3, an exemplary embodiment of a reception circuit allowing the implementation of the principle of synchronization search of the invention and, more particularly, of descrambling a binary train received TBER and compare the successive sequences of L descrambled binary elements according to the principle described above.

 The reception circuit of FIG. 3 notably comprises a generator GPA of pseudo-random sequence, a clock recovery circuit RHB, a clock HGR, a shift register RGD and a counter CPR.

 The clock HGR, controlled by the clock signal recovery circuit RHB, supplies a clock signal -t and two control signals 10 and iL.

 The signal o is an initialization signal used to initialize the pseudo-random sequence generator GPA, that is to say to reset this generator to the same position as the pseudo-random sequence generator of the transmitting circuit used to scramble the train of data to be transmitted, so that it produces the same pseudo-random sequence as that used in the transmission, but with a possible phase shift, the "phase" of this sequence being anyway unknown.

The initialization signal 10 is also used for zeroing the shift register RGD and the counter CPR.

 The signal tel is a word count signal which passes to logic level 1 after the reception of L binary elements.

 The GPA generator initialized by the signal t0 provides the pseudo-random descrambling sequence identical to the pseudo-random scrambling sequence at an input of a stol logic gate performing the logic function EXCLUSIVE and whose other input receives the scrambled bit stream received TBER.

 The shift register RGD is controlled by the clock signals I and initialization tO. A data input ed of this register is connected to the output of the logic gate pti via a gate st2 performing the logic OR function. Another input of this gate nt2 is connected to an output sd of the register RGD.

 The output of gate ot2 is also connected, via an inverter lvi, to an input of a gate pt3 performing the AND logic function.

Another input of this gate receives the clock signal t. An unreferenced output from this door is connected to a counting input ec of the CPR counter.

 A reset input of the CPR counter is connected to an output of a gate 24 performing the OR logic function and two inputs of which respectively receive the initialization signal 10 and the word count signal IL.

 An output of the CPR counter is connected to an input of a DMX demultiplexer of which three outputs dsl, ds2 and ds3 are respectively connected to an input of gates sot5, ot6 and st7 performing the AND logic function. These doors are controlled by the word count signal IL supplied on another of their inputs. These gates provide counting signals sx0, sxi and sx2 respectively.

 On reception of a scrambled binary train TBER, the clock recovery circuit RHB makes it possible to reconstruct the clock rate. It supplies the clock circuit HGR which supplies in response the clock signals t, initialization 10 and word count IL. The latter goes to logic level 1 after the reception of L binary elements.

At each clock step, under the signal control, the binary elements of the scrambled train TBER received are set to EXCLUSIVE OR with the respective binary elements of the pseudo-random sequence from the GPA generator, by the logic gate pt1 The binary elements retransmitted by this gate are supplied to an input of the OR gate pt2 of which another output receives the output signal of the shift register RGD. The output signal from gate pt2 is then entered in this register. After inversion by the lvi circuit, this signal is supplied to the input ec of the counter.
CPR via the AND gate r> t3 controlled by the clock signal t,
The counter CPR is reset to zero by the signal 10 (time t0), then at the start of the reception of each word, that is to say after the reception of each group of L binary elements, by the signal tL.

 The CPR counter, which advances by one step for each level 1 binary element supplied on its counting input ec, therefore counts the number of binary elements at 0 supplied by the gate out2.

At the end of the reception of each word, the counting signal IL goes to logic level 1. It is then proceeded to examine the content of the counter CPR. As we saw earlier, three cases are possible:
- the content of the counter CPR is equal to O, that is to say that the shift register RGD contains only binary elements at 1. The signal supplied by the DMX demultiplexer on its output dsl is at logic level 1. An inhibition signal sx0 of logic level 1 is consequently transmitted by the gate sot5, after inversion by a logic inverter lv2, to a control input of the pseudo-random generator GPA via an AND gate st8 of which one input receives the signal d 'clock t. The latter is therefore not retransmitted and the progression of the GPA generator is inhibited.

 The word count signal IL goes to logic level 0. It is the same for the inhibition signal sx0. The gate 28 becomes active again, the clock signal I is again transmitted to the control input of the GPA generator, the progress of which resumes.

The operation of the reception circuit of FIG. 3 therefore resumes in the manner previously described:
- the digital value contained in the counter CPR is greater than 1, that is to say that the shift register RGD contains several binary elements at o. The signal supplied on the output ds3 of the DMX demultiplexer is at logic level 1. It is therefore the same for the signal sx2 retransmitted by the gate out7. The research continues.

 - the counter CPR contains the digital value 1, that is to say that the shift register RGD contains a single binary element at 0. We have therefore identified the binary element F sought, of each word. The signal supplied on the output DS2 of the DMX demultiplexer passes to logic level 1. The same is true of the synchronization signal found sxi retransmitted by the gate out6. This signal can be used to control the continuation of the operation of the reception circuit of FIG. 3 in the manner which has just been described in order to confirm the identification of the binary element F, therefore of the synchronization of the scrambled binary train received. .

 The synchronization of this train being acquired, the descrambled data train TBDR can be taken from an output -1 of the logic gate otl. The first binary element of each word is indicated by the passage to o of the output signal of the logic gate pt2.

 The reception circuit of FIG. 3 whose operation has just been described therefore makes it possible to find the binary element F of fixed position and of predetermined logic level in each word, to descramble the binary train received and therefore to reconstruct the words transmitted. .

 The foregoing description has been provided by way of non-limiting example only and numerous variants can be envisaged without departing from the scope of the invention.

Claims (4)

 - Continue said comparison until there remains only one selected binary element which is therefore said fixed position binary element (F) sought.  - compare each of the selected binary elements with the respective binary elements of the same rank of each of the following received words and select, after each comparison, only the binary elements which, in each word, occupy the same rank and have said fixed value (0 )  - select the binary elements which, in the first two (MB1) and second (MB2) received words occupy the same rank and have said fixed value (0) of the binary element of fixed position (F)  - compare each binary element of the first received word (MB1) with the binary element of the same rank of the second received word (MB2) ;;  - descrambling the received binary data stream (TBER) using a pseudo-random binary sequence identical to said pseudo-random binary sequence (SBPA) used for scrambling;  - transmit said scrambled train (TBEE) ;;  - scrambling said data stream with a pseudo-random binary sequence (SBPA) of fixed length in order to obtain a scrambled binary data stream to transmit (TBEE);  - give one of the fixed position bits (F) a fixed value (0) in all the words (MB) of said train (TBT)  - split the data stream to be transmitted (TBT) into words (MB) of fixed length (V;  1. Method for scrambling a binary data stream to be transmitted, descrambling and synchronization search for scrambled binary data transmitted and received, characterized in that it consists in:  2. Method as defined in 1, characterized in that it consists, when said successive comparisons do not make it possible to select a single binary element of fixed value (0) after a predetermined number of comparisons, to start a second cycle of comparisons and selection with the following received words.  3. Method as defined in 1, characterized in that it consists, when said successive comparisons do not lead to the selection of any binary element, in sliding the pseudo-random binary sequence of descrambling of a binary element and to carry out a second cycle of comparisons and selection.  4. descrambling and synchronization search circuit making it possible to implement the method described in claims 1, 2 and 3, characterized in that it comprises in particular:  - a generator (GPA) of pseudo-random binary sequence of fixed length;  - a logic gate (otl) performing the EXCLUSIVE OR function, an input of which is connected to an output of said generator (GPA) of pseudo-random binary sequence and another input of which is controlled by the scrambled binary data stream received (TBER); ;  - a shift register (RGD) of which an input (ed) is connected to an output of a door (2) performing the OR logic function and of which an input is connected to an output (spi) of said door (, otl) carrying out the logic function EXCLUSIVE OR and of which another input is connected to an output (sd) of this register (RGD) ;;  - a counter (CPR) of which a counting input (ec) is connected to the input (ed) of the shift register (RGD) via an inverter (Ivl) and a controlled gate (pt3) by a clock signal (t) reconstructed by a clock circuit (HGR) from said received scrambled binary data stream (TBER), a reset input of this counter (CPR) being connected to an output d 'a door (pt4) whose inputs respectively receive an initialization signal (10) and a word count signal (IL) from said clock circuit (HGR); ;  - a demultiplexer (DMX), an input of which is connected to an output of the counter (CPR) and of which outputs (ds1, ds2, ds3) are connected to an input of respective logic gates (pt5, pt6, 27) controlled by said signal word count (fol) to respectively supply inhibition signals (sx0) retransmitted to an input of said generator (GPA) of pseudo-random binary sequence, synchronization found (sx1), and continuation of the synchronization search ( sx2).