FR2652212A1 - Device for coding information intended to be transmitted and/or stored after data rate reduction - Google Patents

Abstract

Device for coding information of the image type, represented, on the one hand, by input signals intended to be transmitted and/or stored after data rate reduction and, on the other hand, by first information relating to the movement between these signals, the said device comprising a coding stage (220). This device also comprises, for processing the said input signals, which correspond to the chrominance component: (a) a stage (205) called spatial filtering stage; (b) a stage (250) called stage for estimating movement by identical blocks, these blocks being bounded by or within the said batches of information of the said defined rank, on the basis, on the one hand, of the current input signals to be processed and, on the other hand, of the signals processed during the preceding processing cycle, and also of the said first movement information, the said stage being intended to deliver second movement information; (c) a stage (240) called stage for prediction on the basis, on the one hand, of the said previously processed signals and, on the other hand, of the said second movement information, the said stage being intended, for the purposes of the coding, to deliver signals corrected by the said second movement information; (d) a stage called stage of selection of the signal to be coded. Application: system for storage of data on compact discs.

Description

Description
The present invention relates to a device for coding information, and in particular two-dimensional information, arranged in batches of periodic information of the image type, of successively odd and even ranks, represented on the one hand by input signals of determined rank, intended to be transmitted and / or stored after reduction in bit rate, and secondly by initial information relating to the movement between these signals and intended, after their estimation, to be substituted, in said representation, for the complementary signals of opposite rank while being linked to signals of determined rank which surround the latter, said device comprising a coding stage.

 This invention finds a particularly interesting application in the case where the information to be encoded is representative of moving images and where a compact disc is used as a medium for the information transmitted and / or stored.

 The transmission and / or storage of a very large quantity of information, associated for example with imageas, generally involves operating a compression of the signals to be transmitted and / or stored, that is to say a reduction , in a report to be determined, of their number. The reduction ratio is determined inter alia by the fact that one must keep a sufficient quantity of signals so as not to degrade too much the global information which they carry, for example, within the framework of the cited application, by the fact that we must maintain an acceptable image quality.

 Most of the coding methods currently known for achieving this bit rate reduction are based on orthogonal transformations, of the discrete cosine transformation type, which allow a bit rate reduction in a ratio of the order of 10 to 1. An example of such transformations is described in U.S. Patent No. 4,394,774. However, for a good number of applications, and for example in the application for storage and processing of images on compact disc, this ratio is not sufficient.

A previous French patent application ne8908186, filed on June 20, 1989 by the applicant company, describes a signal processing device which makes it possible to carry out additional reduction processing in a ratio of 2 to 1. This device, intended to be of generally included in a signal transmission and / or storage system which comprises on the one hand a transmission stage and on the other hand, after transmission and / or storage of the signals transmitted on a medium with limited bandwidth making necessary said rate reduction processing, a stage for receiving and / or reading the transmitted and / or stored signals, itself essentially comprises the following sub-assemblies
- a motion estimation circuit between batches of signals of the same dimension (between successive images in the case where the signals to be transmitted and / or stored are representative of animated images)
- a time sub-sampling circuit
- a filtering and spatial sub-sampling circuit in a 1/2 ratio
- And a decision-making circuit intended to control, according to the output of the motion estimation circuit, the selection of one or the other of the outputs of the time sub-sampling circuit and of the filtering and spatial subsampling in a 1/2 ratio.

 In one of the embodiments described in said request, the time sub-sampling circuit (in a 1/2 ratio) is a switch controlled at a frequency equal to half the repetition frequency of the input signals of the processing device. signals, and it therefore eliminates every other image in the series of image signals, for example even images. The motion estimation circuit then acts on the non-eliminated images, the odd images in the example given, to seek the direction of movement from one to the other of them and subsequently allow the reconstruction of the non-images. As the signals are generally processed in blocks, the motion estimation circuit, more precisely, searches for each of these blocks the direction of the movement, in order to deduce later (on reception and / or reading). transmitted and / or stored signals) an approximation of the different blocks composing the non-transmitted images, on the one hand from the movement information thus obtained1 and on the other hand from the content of two successive images adjacent to an eliminated image.

The motion estimation circuit used comprises for example two image memories and a block correlator. Such correlators are already known, for example from the article by JR Jain and AK Jain, UDisplacement measurement and its application in interframe image coding ", IEEE Transactions on Communications, vol.COM-29, n012, Dec. 1981, pages 1799 1808 The correlation motion estimation thus proposed has the effect of determining for each block the eliminated images (12, I4 for example, in a series of images
Il, 12, 13, 14, 15, etc ...) a displacement vector D such that one can deduce from this knowledge of D an approximation î2, î4, etc ... of the image eliminated from the half-sum of the non-eliminated images which surround it, according to a relation of the following type, in the case of 12 to be reconstructed between Il and 13
I2 (X) = (1/2) (I1 (XD) + I3 (X + D)) where X is the spatial index of the current image point1 r1, 12,
I3 the original images, D the displacement (in image points), and 12 the sought-after approximation of the intensity of point X of the current block of the eliminated image.

Expressed in other words, this motion estimation amounts to searching for each block, represented by a current point of spatial index X, a vector D such as the expression
2
(DFD (X, D)) for all blocks is minimal.

In this expression, DFD, which comes from the corresponding English terms, "Displaced Frame Difference" r is the approximation error attached to the current block and equivalent, for this block, to the sum of the squares of the approximation errors on all block points. This approximation error therefore has the expression
E (12 (X) - (1/2) (I3 (X + D) + I1 (XD))) 2r
(blocks) and it is this expression whose minimum value is sought. The selected displacement vector is the one associated with this minimum value, after an exhaustive test of all the possible displacement vectors in a search range delimited by horizontal and vertical values
Dx and Dy respectively.

 In the processing device described, the normal operating mode is that of block motion estimation, which allows subsequent motion compensation and which is therefore called compensated mode (in English, "compensated mode"). However, the motion estimation circuit may be faulty (too much noise, movement too fast causing this circuit to leave its operating range, objects with contradictory movements, etc.), and, in such situations, the spatial filtering and subsampling replaces it. The normal operating mode is therefore replaced, in this case, by an uncompensated mode called fallback mode (in English, "fall-back mode").

 This spatial filtering and subsampling circuit which replaces the motion estimation circuit when there is a switch from compensated mode to fallback mode comprises in the example described, a spatial filtering circuit, limiting the bandwidth of the signals then two parallel channels, the first of which includes a first spatial subsampling circuit in a 1/2 ratio (staggered subsampling line ortho goal subsampling, etc.) and the second of which includes a delay circuit (equal to the period of the input signals) and a second spatial subsampling circuit in a 1/2 ratio, similar to or complementary to that produced by the first one. A signalman finally selects one of the outputs of these first and second spatial subsampling circuits, so as to deliver from the samples of two successive images, a complete image, at the frequency half that of the signals of e input obtained by mixing two previously filtered images.

 The failure criterion of the motion estimation circuit is controlled by a decision circuit which determines in parallel channels, what would be on the one hand the error of interpolation compensated in motion, by blocr in the case of operation in compensated mode and other similar error in fallback mode. Following these calculations in parallel, a comparison of the two results leads to selecting the weakest result and to delivering for each picture block corresponding mode information, indicating that this block will be transmitted and / or stored in compensated mode. or on the contrary in fallback mode, without eliminating every other image in the latter case.

 The signal processing method described in the cited application, the essential characteristics of which have just been recalled with the aid of a description of its implementation, therefore makes it possible to remedy the shortcomings observed, in terms of reduction of flow with the most of the signal coding methods currently known.

 However, by associating with these now traditional methods the method thus described, it appears that simplifications of the signal processing, associated with new possibilities of reduction in bit rate, can be implemented.

 The object of the invention is to propose a device for coding signals which authorizes in a simple and economical manner a reduction in the quantity of information to be transmitted which is greater than in the case of previous embodiments.

To this end, the invention relates to a coding device characterized in that its input signals are representative of the color difference signals U and V - or chrominance component - of a sequence of moving images, and in that '' it also includes, for processing said input signals of determined rank
(a) a so-called spatial filtering stage
(b) a stage called motion estimation by identical blocks, these blocks being delimited by or within said batches of information of said determined rank, on the one hand from the current input signals to be processed, d on the other hand of the signals processed during the previous processing cycle and also of said first movement information and said stage being intended to deliver second information relating to movement, on the one hand between the signals of determined rank and the signals of opposite rank which follow them, and on the other hand between successive determined rank signals
(c) a stage called prediction on the one hand from said previously processed signals and on the other hand from said second movement information, said stage being intended to deliver, for coding of the signals corrected by said second movement information
(d) a stage known as for selecting the signal to be coded.

 Classic type motion estimators have a fairly long computation time. Thanks to the structure proposed here, a simplification of the processing of the signals is obtained by taking advantage of the fact that a motion estimation concerning the input signals of the present coding device has already been carried out, and quer of this motion estimation can be deduced, in accordance with the invention, from new movement information making it possible to modify the conditions of the coding processing in the desired direction of reducing the calculation time and also the bit rate.

In an embodiment which is both simple and advantageous, the motion estimation stage comprises in series an addressing circuit receiving on a first input said previously processed signals and on a second input said first movement information, a subtractor , a square riser, a summator, and a comparator
(a) for the determination of the second information relating to the movement between the signals of determined rank and the signals of opposite rank which follow them, the subtractor receives on its second input not connected to the addressing circuit said signals of opposite rank
(b) for the determination of the second information relating to the movement between successive determined signals of rank, a multiplier by two precedes in series the second input of said addressing circuit, and the subtractor receives on its second input not connected to said addressing circuit signals of determined rank.

 Preferably, the so-called previously processed signals are supplied to the prediction stage by a so-called reconstruction stage connected in parallel in the coding stage and executing the operations opposite to those already executed, on the input signals of said stage of coding.

the reconstruction stage thus provided may for example comprise, at the output of an orthogonal transformation circuit and quantification provided in the coding stage, an orthogonal transformation circuit and inverse quantization followed, in series, by a reconstruction circuit of the signal present before selecting the signal to be coded and a memory. The size of this memory is, in general, designed to contain one of said batches of periodic information of successively odd and even ranks.

 In a particular embodiment, the signal reconstruction circuit comprises a switch controlled by said additional information, a switch for eliminating a batch of information reconstructed in two and, in parallel between this switch and this switch, a channel direct link or a link channel via an adder according to the intra or inter mode respectively indicated by said additional information.

your features and advantages of the invention will now appear more precisely in the description which follows and in the appended drawings, given by way of nonlimiting examples and in which
FIGS. 1, 5 and 6 show three exemplary embodiments of coding devices which can be used in particular when the information to be coded is representative of moving images and for example when it corresponds to the luminance component of the signals representative of these images
- Figures 2a, 2b, 2c, 3, 4 respectively illustrate an interpolation principle with motion compensation for a block to image an example of association of a neighborhood of blocks of an image not transmitted to a block of the following image transmitted, a principle of approximate determination of additional motion information, an embodiment of the motion estimation stage delivering this additional motion information, and a principle of correction of this information following their approximate determination
- Figure 7 shows an embodiment of the coding device according to the invention;
- Figure 8 illustrates, in the case of U signals, the spatial subsampling processing performed on the U and V color difference signals constituting the chrominance component
- Figure 9 shows an exemplary embodiment of the motion estimation stage of the coding device of Figure 7
FIGS. 10 and 11 show two exemplary embodiments of a decoding device, corresponding respectively to the coding device of FIG. 6 and to that of FIG. 7.

 The description which follows is carried out first with reference to FIG. 1. It will be assumed beforehand that, in the case of the application described here by way of nonlimiting example, it is desired to transmit and / or record sequences of images animated in non-interlaced luminance format (comprising 288 lines per image of 352 image points per line), and including the two components U and V in chrominance (also 352 x 288 image points), at the original frequency 25 hertz, with a desired speed of 1.2 Mbit / second. It is also assumed that these original images have been, as regards their luminance component, processed according to the principle of subsampling described in the French patent application No. 8908186 already cited, and recalled above.

 The prior realization of this processing therefore leads to having now, for luminance, a share of image blocks classified into so-called compensated blocks or so-called fallback blocks according to whether they will be transmitted and / or stored in compensated mode or in fallback mode, and on the other hand, displacement vectors associated with these blocks. The displacement vectors are associated with each block, of dimensions pxq for example, images of even rank then eliminated (this choice is given only as an example, and one could also choose to transmit the even images and eliminate odd images). The classification into compensated blocks or fallback blocks can be made on blocks of size different from that of the preceding ones, which will be noted p 'x q' for example.

 In the case of the particularly advantageous application where the signals to be coded include information representative of moving images with one or more compact disks as support for the transmitted and / or stored signals, the best results have been obtained for p = q = 16 and p '= q' = 8. However, this hypothesis is in no way restrictive and the processing described below is applicable to other block sizes r as well as to other image formats.

 It will also be assumed in the example described with reference to FIG. 1, that the information available at the input of the coding device are only motion compensated blocks, and we will generalize later in the event that this information includes blocks of withdrawal.

 These input signals, in the case of a luminance component of image signals, correspond here to successive images at a frequency of 12.5 Hz, divided into blocks of 8 x 8 image points, and accompanied respectively by displacement vectors D constituting first movement information.

 The coding device of FIG. 1 comprises a stage called selection in this case a subtractor 10, the output of which is connected to a stage 20 constituting the coding chain proper. This coding chain itself comprises, here, a circuit 21 for orthogonal transformation and quantification (delivering information C of classification of the blocks according to their activity defined in general using thresholds, as a function of subjective tests linked to the contrasts, with greater or lesser uniformity, etc.), a variable length coding circuit 22, a buffer memory 23 delivering the coded signals Sc at a constant bit rate, and a flow regulation circuit 24 (delivering information Normalization N). Auxiliary information C and N is transmitted, because it will be used on reception, during orthogonal transformation and inverse quantization operations. An example of such a coding chain is described for example in the patent US-A-4394774 already cited or, in an even more advantageous embodiment, in the French patent application filed on September 29, 1987 under the number "d 'registration 8713429.

 The subtractor 10 receives on the one hand the input signals of the device, constituted here by image blocks B compensated in movement, and on the other hand the output B 'of a stage 40 called prediction, and sends to the input of circuit 21 of the coding chain the difference between this motion compensated block B received as input signal and the signal B 'which is a predicted block as indicated below. Thus, the coding chain instead of successively coding all the blocks of an Itr image then all the blocks of an I3 image, does it only code the difference between these images. More precisely, this inter-image coding processing amounts to coding, for each block of imageas, the difference between a block B of the current image I3 and a block B 'of the image I1 previously processed and reconstructed, taking into account a displacement vector D' between B and B '. This new displacement vector D 'constitutes a second movement information.

 The predicted block B 'is provided by the prediction stage 40 which takes from the reconstructed previous image (I1, when the current image is I3) the samples of the block corresponding to B but spatially shifted from the vector D' and called BR . These reconstructed blocks BR are in the present case supplied by a reconstruction stage 30, comprising here, in series and at the output of the circuit 21 for orthogonal transformation and quantification of a circuit 31 for orthogonal transformation and inverse quantization, a circuit 32 for signal reconstruction present before the selection of the signal to be effectively coded (also receiving the input D 'and the output B' of the prediction stage 40 and performing the opposite operation to that performed by the selection stage 10), and a memory It is the output of this image memory 33 which is connected to the prediction stage 40 to supply it with the blocks BR. your vectors D 'constituting the second movement information are provided by a stage 50 called motion estimation stage operating as indicated now.

 The prediction stage 40 is here, in fact, a memory addressing circuit 33 as a function of the displacement vectors D ′ supplied by the movement estimation stage 50. This prediction stage can include, at the following the addressing circuit, a so-called prediction filter, intended in particular to improve prediction and coding. The circuit 32 of the reconstruction stage 30 is, in the example described, an adder followed by an addressing circuit for writing to the memory 33.

It was previously considered that with each block B2 (of size pxq for example) of the even images I2, 14, etc ... eliminated (and then interpolated) was associated a displacement vector D, represented on the diagram of figure 2a (which, to illustrate this principle in general, shows three successive images I2n-ll I2n, 12n + 1) as well as in the images I1 and 13 (then coded) surrounding I2, the corresponding blocks B1 and B3 taking into account this vector D. If we consider (see Figure 2b representing a sequence of images I2n-1 12nr I2n + 1
I2n + 2) in the image transmitted to code, I3 for example, a block B2n + 1, B3 for example, of size p 'x q', we can associate with this block B3 any neighborhood composed of nii blocks B2n ( B2, for example, with i varying from 1 to n) in the division of image 12 into blocks of size px q. It is then likely that the displacement vector, denoted D ′, which represents the movement of block B3 between image I1 and image 13 is close to double of one of the vectors Di associated with blocks B2 (see the figure 2c).

the motion estimation stage 50 therefore has the function of testing each of these vectors Di and of determining the best of them then of carrying out a correction on this selected vector. The stage 50r represented in FIG. 3 comprises, on the one hand, a first vector determination subset 51. This subset 51, which performs the test function must determine which of the vectors Di which minimizes the expression fi (I3 (x) - Î1 (x-2Di)) for each block of size p 'x q', I3 (x) being the current image and li (x-2Di) the reconstructed image shifted by -2Dir and successively understands for this purpose
an addressing circuit 510 which takes from the image memory 33 the samples of the reconstructed image li corresponding to those of the block B3 and shifted by (-2Di), for the vector Di considered
- a subtractor 511, which makes the difference between I3 (x) r current image, and Il (x-2Di), reconstructed and offset image
- an elevator squared 512 of the difference thus obtained
- a summator 513, over the entire block B3, of the squared differences thus obtained
a comparator 514, which determines that of the vectors Di thus leading to the lowest result, this selected vector being denoted D'int.

 Stage 50 also includes a second vector correction subset 52. This sub-assembly 52, intended to carry out a correction of t 1 picture element (see FIG. 4) on each component of the vector D'int selected by the sub-set 51, successively comprises elements 520 to 524 similar to the elements of the sub-assembly 51, except that the addressing circuit 520, instead of receiving the different vectors Di to be tested, receives D'int and applies to it the eight different possibilities of correction of + 1 image element (such as shown in the neighborhood example of Figure 2c). This time, at the output of the comparator 524, and therefore of the motion estimation stage 50, the vector D 'which is used to perform the prediction on the block B3 is obtained. In general, each comparator, 514 or 524, compares the results two by two and select the lowest, but it could also ensure the temporary storage of all the results before making the selection of one of them. It will also be specified that instead of providing two subsets 51 and 52 in series, one could provide only one subset first performing the vector determination function, then that of correcting the vector thus determined. Such a solution saves a few circuits, but in return leads to a slightly slower operation.

 In a second embodiment of the coding device, shown in FIG. 5, the selection stage is no longer a simple subtractor 10, but a circuit 100 called inter / intra decision circuit, the structure of which is specified below and function.

This variant embodiment is advantageous when it is desired to refine the coding of the blocks by carrying out a processing which is different according to the energy contained in the different frequency components of the current signals to be processed. The interlintra decision circuit 100 comprises on the one hand a first circuit 101 for calculating the energy contained, by block B of the signals to be processed in the components other than the DC component. The inter-intra decision circuit 100 also includes a subtractor 102r receiving on the one hand the samples corresponding to a current block B, on the other hand the samples corresponding to the block
B 'corresponding predicted, and followed by a second energy calculation circuit 103. This circuit 103 likewise calculates the energy contained in this block of samples formed at the output of the subtractor 102 from B and B' (always excluding component keep on going). A comparator 104 then receives the output of the energy calculation circuits 101 and 103 and selects, according to the result of this comparison, one or the other of two coding modes called inter-image coding and intra-image coding ( inter and intra coding in the general case). In either case, additional information M1 specifying said coding mode is transmitted, since it will be necessary, on reception, for the reconstruction of the images. This information M1 is also supplied to the signal reconstruction circuit 32 of the reconstruction stage 30.

 A third embodiment of the coding device is shown in FIG. 6 and corresponds to the case where the motion estimation circuit which made it possible to obtain the vectors D associated with the input signals B is faulty. In this case, the input information of the coding device is no longer only compensated blocks in movement, but can also be fallback blocks. Additional information M2 then accompanies, of course, this input information to indicate the nature of the blocks and the operating mode, compensated or fallback, which made it possible to obtain them. This additional information M2 is firstly transmitted since it will be necessary, on reception, for the reconstruction of the images, and on the other hand supplied to the inter / intra decision circuit 100 as well as to the signal reconstruction circuit 32 of the reconstruction stage 30.

In this third embodiment, the intertintra decision circuit 100 receives the additional information
M2, so that the coding mode is forced internally when there are input B of the coding device for the fallback blocks, and the reconstruction stage 30 is modified, as follows. At the output of circuit 31, unchanged, of orthogonal transformation and inverse quantization, circuit 32 is now replaced by a circuit 320 for reconstitution of the signal present before selection of the signal to be coded, the output of this reconstitution circuit 320 being supplied to the memory 33.

 The reconstruction circuit 320 first comprises a switch 321, controlled by the information M2 to make the selection between a processing in compensated mode and a processing in fallback mode. In the case (noted CP) of the processing in compensated mode, each blocr as we have seen, can be coded inter or intra, according to the position of a switch 322 receiving the output C of the switch 321 and controlled by l information M1, and the output of this switch is then sent to a switcher 323r either directly in the case of intra coding, or, in the case of inter coding, via an adder 324 which receives on a second input the output of the prediction stage 40 to add it to the output of the switch 322 present on its first input.

In the case (denoted R) of the processing in fallback mode, a spatial sub-sampling circuit 325 receives the output R of the switch 321 so as to keep in each fallback block only the samples belonging to the current image to be reconstructed. The blocks in compensated mode are sampled in a similar manner, the intra output of the switch 322 and the output of the adder 324 being supplied to the circuit 325 for this purpose. A circuit 326 then receives the samples present on the output of this circuit 325 in order to interpolate the missing samples from the fallback blocks. After this interpolation, the output of circuit 326 is sent to the switch 323 to ensure the reinsertion of the blocks in fallback mode in the reconstructed image. The output of the switch 323, on which this reconstructed image is present, is sent to memory 33.

 In the case where the input signals from the coding device correspond to the color difference signals U and V - c, that is to say to the chrominance component - of the sequence of moving images, said input signals n ' like the luminance, have not been subjected to the prior realization of a processing leading to a classification of the image blocks into compensated blocks or fallback blocks. It is however possible, as for luminance, to take account of the fact that movement information D is available at the same time as said input signals in order to propose an improved coding device.

 Such a coding device is shown, in a particular exemplary embodiment, in FIG. 7. The device shown first comprises a spatial filtering stage 205 of the chrominance signals, successively comprising a spatial pre-filtering circuit 206 operating separately on the signals U and on the signals V and a spatial subsampling circuit 207. Indeed, the content of chrominance components being poorer at high frequencies than that of luminance components, a first reduction in bit rate is obtained by a sub - spatial sampling of each of the U and V signals.

 This spatial sub-sampling, here by a factor of 4, is represented in FIG. 8 for the signals U for example, but is similar for the signals V. In this FIG. 8, the image points of the component are represented. chrominance by the corresponding symbol U or V, and we have circled those that the subsampling keeps. We then observe that to a block of 4 x 4 image points of the signals U (or V, in a similar manner) corresponds a block 16 x 8 in luminance (or eight blocks 4 x 4), that is to say say that a block of 8 x 8 U (or V) samples covers the same spatial extent as a 32 x 16 luminance block.

More generally, the spatial sub-sampling of the chrominance component means that a chrominance block Bchr of pxq samples U (or V) to be coded corresponds to n blocks Bi of luminance whose set covers the same spatial extent. The coding device will therefore, in the case of chrominance, provide a motion estimator intended to determine, for the image block to be reconstructed, which displacement vector can be used for this reconstruction among all the displacement vectors Di (i varying from 1 to n) attached to said blocks
Bi of luminance. In addition r we will thus reconstruct, here, on the one hand, a chrominance image of even rank, noted
AA lchr2r Ichor4 etc ..., compared to the image of opposite rank rchrlr Ichor3, etc ... which precedes it and on the other hand a chrominance image of odd rank, noted 1cher3 1chr5 'etc ..., by relation to the image of the same rank ichrîr Ichr3r etc ... which precedes it.

The coding device of FIG. 7 therefore comprises, following the spatial filtering stage 205, the selection stage, then a stage 220 constituting the coding chain and identical to stage 20. The stage of selection here is an inter / intra decision circuit 210 of the same structure as the circuit 100 of FIGS. 5 and 6. This stage 210 receives on the one hand the blocks B of output of the spatial filtering stage and on the other hand the output blocks B 'of a prediction stage 240, identical to stage 40 of FIGS. 1, 5 and 6 and therefore constituted, like him, of an addressing circuit of the output memory of a stage of reconstruction 230 similar to stage 30. Stage 210 also delivers, as before, additional information Mi, relating to the inter or intra coding mode and which is also transmitted since it is necessary for reception. The addressing of the memory is carried out as a function of displacement vectors D ′ supplied by an estimation stage 250 and constituting here again the second movement information. In the reconstruction stage 230, the reconstruction circuit, referenced 232, located between a circuit 31 for orthogonal transformation and inverse quantization and an image memory 33 and intended for reconstructing successive batches of periodic information is similar to that of Figure 6, with the following exceptions
- the absence of classification into compensated blocks and fallback blocks makes the path including circuits 321, 325, 326 unnecessary, and these elements are therefore eliminated, the output of circuit 31 then being directly connected to the input of circuit 322
- the switcher 323 is no longer useful and is replaced by a switch operating here at the rate of 12 ^ 5 hertz to send to memory 33 only the only necessary images, here the odd images.

The motion estimation stage 250, represented in FIG. 9, here comprises a single vector determination subset. Indeed, due to the lower definition and the poorer content of the chrominance at high frequencies, the correction on the selected vector, carried out in the case of luminance by the subset 52, is no longer necessary here. The vector determination is carried out on the one hand from the input signals B to be processed on the other hand from the signals already processed during the previous processing cycle and therefore available at the output of the reconstruction stage 230, and also from said first movement information. This subset is quite similar to the subset 51 described above, and the motion estimator makes the choice of vector which minimizes the same criterion as in the case of luminance. This first motion information is here the n vectors Di attached to the n blocks Bi of luminance which correspond to the chrominance block considered. The vector determination sub-assembly which here constitutes the motion estimation stage 250 firstly comprises an addressing circuit 251, receiving on a first input said previously processed signals, that is to say the output BR blocks of the reconstruction stage 230, and on a second input the n vectors
Di constituting the first movement information. The addressing circuit 251 is followed by a subtractor 252, a square elevator 253, a summator 254, and a comparator 255.

 two situations must therefore be distinguished here. In the first situation, for the determination of second movement information D 'relating to the movement between an image of odd rank and the image of even rank which follows it, for example between I1 and I2, between 13 and I4, etc. ., the addressing circuit 251 directly receives the vectors Di, and the subtractor 252 receives on its second input, not connected to the addressing circuit, the current signals, which at this instant correspond to 12, I4, etc. . On the other hand, in the second situation, when the stage 250 performs the determination of second movement information D ′ relating to the movement between successive odd-rank images, for example between li and 13, between 13 and Isr, etc., the addressing circuit 251 receives the vectors Di this time by means of a multiplier by two r the current signals present on the second input of the subtractor 252 now corresponding to 13, 15, etc ... Indeed, in the first case, the second s movement information is, in approximation, of the order of magnitude of the first movement information, while, in the second case, it is in approximation, of the order of magnitude of twice this first movement information.

 Conversely, when signals have been, prior to their transmission and / or storage, coded in coding devices such as those which have just been described, their decoding must be provided to allow reconstruction of the original signals.

 In the case where these original signals (on transmission, before coding) correspond to the luminance signals of a sequence of television images, an exemplary embodiment of a suitable decoding device is shown in FIG. 10 In this decoding device, the transmitted and / or stored signals are first sent to a buffer memory 310, at the output of which is provided a variable length decoding circuit 320. This circuit 320 provides, for the various successive blocks r of the quantized coefficients, which are then sent to a circuit 330 for inverse quantization and orthogonal transformation, the inverse quantization being carried out using a standard signal delivered on transmission by the flow control circuit 24 and then transmitted and / or stored, with a view precisely to the reverse operation on reception, during decoding.

 The decoding device of FIG. 10 also includes a circuit 340 for reconstructing batches of information on the one hand from the output signals of the inverse quantization and orthogonal transformation circuit 330, on the other hand from prediction information determined (during a previous reconstruction cycle), and also information M1 (inter or intra coding) and M2 (compensated or fallback blocks). The output of this circuit 340 is sent to a storage circuit 360, via a signal processing circuit 350 such as that described in French patent application No. 8908187, that is to say a subsampling and interpolation stage with or without motion compensation.

 The signals thus transmitted to the sub-sampling and interpolation stage generally comprise, for each batch of information such as an image in the application more specially described, partly of the reconstructed blocks, corresponding to the compensated mode and coded either in inter, or in intra, and for part of the blocks in fallback mode. Storage in the storage circuit 360 completes the reconstruction cycle and makes it possible to have useful signals for determining said prediction information and the following reconstruction cycle. This prediction information is determined in a prediction circuit 370 receiving on the one hand the output of the storage circuit 360 and on the other hand the second movement information D ′, and here is in fact, an addressing circuit of the circuit 360 taking into account the movements indicated by this information D '.

 In the case where the original signals (on transmission before coding) correspond to the chrominance signals of a sequence of television images, another exemplary embodiment of a decoding device is shown in FIG. 11. The circuits 310, 320, 330, 360, 370 are, in this device, identical to the circuits of the same references in FIG. 10. The reconstruction circuit 340 is very similar to the previous one, the only difference being that, in the case of the figure lîr it does not receive M2 information since there is no distinction between compensated or fallback blocks for chrominance. The output of this reconstruction circuit 340 is sent on the one hand to a circuit 450 of reinterpolation of color difference signals, the output of which is intended to be supplied to a display device, and on the other hand to a switch 480, operating here at a rate of 12.5 hertz and inserted between the circuit 340 and the vs memory circuit 360 to eliminate a batch of reconstructed information out of two and to select only that which is useful for prediction, according to the same operating principle as the switch for selecting the odd images, in the reconstruction circuit 232 of the figure 7.

ou l'expression suivante

selon qu'on se trouve dans l'une ou l'autre des deux situations définies précédemment (mouvement entre images de rangs impair et pair, ou entre images de rang impair), les vecteurs ainsi sélectionnés étant transmis et/ou stockés de façon commune pour U et V. Of course, from the embodiments described, variants can be proposed. We have seen in particular that the processing operations concerning the color difference signals U and V were carried out separately, for example the spatial pre-filtering carried out by the circuit 206, the decisions taken by the circuit 210. On the contrary, one can choose to carry out these treatments in common on U and V, by reconstituting the chrominance component globally. In this case, the test function performed by the vector determination subset of the motion estimation stage is also common and is then concretized by a determination of that of the vectors Di which also minimizes, for U or for V the expression given above, but now the following expression

or the following expression

depending on whether one is in one or the other of the two situations defined above (movement between images of odd and even ranks, or between images of odd rank), the vectors thus selected being transmitted and / or stored in common for U and V.

Claims (7)

Claims  (d) a stage known as for selecting the signal to be coded.  (c) a stage called prediction on the one hand from said previously processed signals and on the other hand from said second movement information, said stage being intended to deliver, for the purpose of stringing, signals corrected by said second movement information  (b) a stage called motion estimation by identical blocks, these blocks being delimited by or within said batches of information of said determined rank, on the one hand from the current input signals to be processed, d secondly of the signals processed during the previous processing cycle, and also of said first movement information, and said stage being intended to deliver second information relating to the movement on the one hand between the signals of determined rank and the signals of opposite rank which follow them, and on the other hand between successive determined rank signals  (a) a so-called spatial filtering stage  1 Information coding device, and in particular two-dimensional information, arranged in batches of periodic information of the image type, of successively odd and even ranks, represented on the one hand by input signals of determined rank, intended for be transmitted and / or stored after rate reduction, and secondly by initial information relating to the movement between these signals and intended, after their estimation, to be substituted, in said representation, for the complementary signals of opposite rank while being linked to the signals of determined rank which surround the latter, said device comprising a coding stage characterized in that its input signals are representative of the signals U and V of color difference - or chrominance component - of a sequence of moving images, and in that it also includes, for processing said input signals of determined rank 2. Coding device according to claim 1, characterized in that said motion estimation stage comprises in series an addressing circuit receiving on a first input said previously processed signals and on a second input said first movement information, a subtractor, a square elevator, a summator, and a comparator, and in that  (a) for the determination of the second information relating to the movement between the signals of determined rank and the signals of opposite rank which follow them, the subtractor receives on its second input not connected to the addressing circuit said signals of opposite rank  (b) for the determination of the second information relating to the movement between successive determined signals of rank, a multiplier by two precedes in series the second input of said addressing circuit, and the subtractor receives on its second input not connected to said addressing circuit signals of determined rank. 3. Coding device according to one of claims 1 and 2, characterized in that the previously processed signals are supplied to the prediction stage by a stage known as the reconstruction of batches of information connected in parallel in the stage of coding and performing the reverse operations of those already executed, on the input signals of said coding stage, at the point of connection to this coding stage. 4. Coding device according to claim 3, characterized in that the reconstruction stage comprises, at the output of an orthogonal and quantization transformation circuit provided in the coding stage, an orthogonal transformation circuit and reverse quantization followed, in series, a circuit for reconstituting the signal present before selecting the signal to be coded and a memory. 5. Coding device according to claim 4, characterized in that the size of the memory is that of one of said batches of periodic information of successively odd and even ranks. 6. Coding device according to one of claims 1 to 5, characterized in that the selection stage is a so-called inter / intra decision circuit also delivering additional information corresponding to the inter mode or to the intra mode. 7. Coding device according to claim 6, characterized in that the signal reconstruction circuit comprises a switch controlled by said additional information, a switch for eliminating a batch of information reconstructed in two and, in parallel between this switch and this switch, a direct link channel or a link channel via an adder according to the intra or inter mode respectively indicated by said additional information.