FR2651352A2 - Interfacing circuit of a receiver for radio-broadcast guidance information for motorists - Google Patents

Abstract

The invention relates to an interfacing circuit for implementing a system in which a procession of information items is transmitted by radio via a method such as RDS. This circuit (100) is linked to the car radio (200) and to digital data processing means (300), and comprises a first stage receiving, as input originating from the car radio, on the one hand, a clock signal and, on the other hand, the digital signal information in the form of a synchronous serial data flow, and delivering, as output, this same digital signal information in the form of an asynchronous parallel data flow, this first stage comprising two similar shift registers and control means operating in such a way that the registers are loaded successively and alternately by portions of the synchronous data flow, the contents of one of the registers, after completion of the loading, being read in parallel form, while the other register is still being loaded, and conversely, the information at the output of this first stage then being decoded and discriminated by the processing means delivering corresponding signals to display means (400). Very advantageously, the circuit further comprises a second stage receiving, as input, the asynchronous parallel data flow delivered by the first stage (110) and delivering, as output, a controlled, asynchronous serial data flow to the RS-232C standards for sending to the processing means.

Description

Interfacing circuit for information receiver
radio guidance for motorists
The present addition relates to an improvement to the system for collecting and disseminating information for motorists described in the main patent 89-01390.

 This patent proposed in particular to transmit a scrolling sequence of information broadcast over the air by a method of broadcasting digital data with a subcarrier added to a broadcast transmission signal, the receivers on board vehicles being receivers of broadcasting equipped with a decoder ensuring the separation of digital signal information from the audio program signal.

A characteristic system for broadcasting digital data by such a method is the RDS system (Radio Data
System), which authorizes the broadcasting of digital data by radio in frequency modulation in accordance with a certain number of well-defined specifications.

 As mentioned in the main patent, one of the major advantages of the RDS system is that it can be used by simple car radios equipped with an appropriate decoder, and of which various models are currently available or under development.

 To use the guidance forms broadcast by the system of the main patent, it then suffices to connect to the digital data output of the car radio a box comprising the appropriate circuits and control means.

 The object of this addition is precisely an interfacing circuit making it possible to adapt the signals delivered by the car radio and to implement the appropriate functions by simple means.

 More specifically, one of the aims of the present addition is to propose an interfacing circuit which makes it possible to have all the necessary software functions executed by preexisting means such as a commonly available microcomputer circuit or a microcomputer. compatible with trade, possibly simplified to keep only the essential elements (logic card).

 Very advantageously, the interfacing circuit of the invention will also include means making it possible, from signals delivered by the microcomputer, to control a display such as a bar of alphanumeric characters with liquid crystals.

 It is thus seen that only the interface circuit of the invention will be specific, all the other elements (car radio, microcomputer and display) being standard elements available commercially and produced in large series, therefore very low cost.

 Furthermore, it will be seen that, in a preferred embodiment, the interface circuit of the invention communicates according to the RS-232C standard with the microcomputer (in transmission to the latter to transfer the raw data to be processed to it, and in reception to receive the data to be presented on the display); this standard is a standard of universal use, which will therefore make it possible to cooperate with the interface circuit of the invention and its associated radio with a very wide variety of microcomputers without requiring any particular adaptation of the circuit, the only adaptations being adaptations software internal to the microcomputer and therefore easy to implement.

 According to the invention, the circuit is characterized in that it is connected to the car radio and to digital data processing means and in that it comprises a first stage receiving at the input, coming from the car radio, on the one hand a clock signal and on the other hand the digital signal information in the form of a synchronous serial data stream sequenced on this clock signal and delivering as output the same digital signal information in the form of a stream of asynchronous parallel data, this first stage comprising two similar shift registers and control means operating so that the registers are loaded successively and alternately by portions of the synchronous data stream, the content of one of the registers being, after completion of the loading, read in parallel form while the other register is being loaded, and vice versa, the information at the output of this first stage then being d ecoded and discriminated by the processing means delivering to the display means corresponding signals.

 Very advantageously, the interfacing circuit further comprises a second stage receiving as input the asynchronous parallel data stream delivered by the first stage and delivering as output an asynchronous serial data stream controlled according to RS232C standards for transmission to the processing means.

 In this case, preferably, the second stage also receives as input, from the processing means, a serial data stream in accordance with RS-232C standards and transforms this received serial stream into a parallel stream suitable for controlling the display means. .

0
We will now give a detailed embodiment of the invention, with reference to the accompanying drawings.

 Figure 1 is a schematic overview of the interface circuit of the invention and the various members with which it cooperates.

 Figure 2 is an internal schematic representation of the interface circuit of the invention showing the two stages used and the different connectors.

 FIG. 3 is a timing diagram showing the evolution over time of the various control signals produced by the first stage of the interface circuit of the invention.

 Figure 4 shows the detail of the elements constituting the first stage of the interfacing circuit of the invention.

 FIG. 5 shows the detail of the elements constituting the second stage of the interfacing circuit of the invention.

 FIG. 1 is a general view of all of the elements allowing reception and display of the guidance information constituting the reception part, mounted on board vehicles, of the guidance information dissemination system exposed in the main patent, to which reference is made for further details.

 This assembly is organized around a specific interfacing circuit 100 which is the subject of the present invention; this circuit 100 receives information from the digital data output (data channels for external use in the terminology of the RDS standard) from a car radio 200, which is a commercial car radio, unmodified, equipped with RDS circuits allowing to ensure the separation between audio data and digital data transmitted simultaneously by the same broadcasting station.

 The interfacing circuit 100 transmits and receives data in the direction of and coming from processing means 300, which may consist of a conventional microcomputer (for example of the so-called compatible type), unmodified or simplified for n ' keep only the essential elements (logic card only, that is to say comprising the central unit, the read-only and read-only memories and their control circuits, the circuits making it possible to communicate with the outside world); the calculation means 300 may also consist of a card comprising a microcomputer circuit of the conventional type, also architectured in a conventional manner.

 The calculation means 300 can advantageously be connected to a speech synthesis circuit 310 delivering messages directly perceptible by the driver on a loudspeaker 311.

 The route or urban guidance information is also displayed on a display 400, for example a bar of alphanumeric characters with liquid crystals, preferably controlled by signals delivered by the calculation means 300 via the interfacing circuit 100 (this circuit acting then in reception vis-à-vis the calculation means 300).

 The configuration data by the driver (choice of route, request for a situation for a particular traffic node, etc.) are introduced directly into the calculation means 300 for example by a numeric keypad 320.

 FIG. 2 schematically shows the internal structure of the interfacing circuit 100. This essentially comprises two stages 110, 120 and three connectors 111, 121 and 122.

 The role of the first stage 110 is essentially to receive, via the connector 111, the data stream coming from the radio 200 and to transform this data, which arrives in the form of a synchronous serial data stream into a data stream asynchronous parallel on a bus 115.

 The second stage 120 performs two functions.

 Firstly, it receives the asynchronous parallel data stream produced by the first stage 110 and transforms this stream into an asynchronous serial data stream with RS-232C standards for transmission to the calculation means 300.

 Secondly, it receives means of calculation 300 of signals in RS-232C standards which correspond to the only information to be delivered to the driver, that is to say after filtering, error correction and discrimination; stage 120 converts this serial RS-232C data nux into parallel signals applied, via connector 122, to the various terminals of the display 400 while ensuring the adaptations necessary so that these signals are made compatible with the inputs of the display 400.

 We will now describe in detail the structure of the two stages 110 and 120, respectively with reference to FIGS. 4 and 5.

 The first stage 110, illustrated in a simplified manner in FIG. 4 (only the lines corresponding to the different logic signals produced have been shown, apart from the ground, supply lines, etc.).

 This stage receives from the radio, via the connector 111, on the one hand a CLK signal which is the Clock signal associated with the RDS signal and whose frequency is 1187.5 Hz (i.e. the frequency from the RDS subcarrier, 57 kHz, divided by 48), and on the other hand a DATA signal which constitutes the RDS information proper. In accordance with RDS standards, this DATA signal is a logic signal whose value (0 or 1) may change during the rising edge of the CLK signal; ; the two signals CLK and DATA are TTL compatible signals Ge logic zero corresponding to zero volts and the logic corresponding to five volts) which can therefore directly attack the different stage circuits 110.

 Stage 110 will transform the serial signal DATA at 1187.6bits / s, synchronous with the signal CLK, into parallel information on eight bits, asynchronous, on an internal bus 50.

 Due to asynchronous operation, it would normally be impossible to guarantee that all of the RDS information available at the output of the car radio will be transmitted without loss on the bus 115 and then to the calculation means.

 In order to remedy this drawback, the stage 110 provides two similar circuits 113, 114 and 113 ', 114', respectively, controlled by a circuit 112 ensuring the switching between these two similar circuits. The stage 110 can therefore simultaneously receive the RDS information and transfer it to the bus 115 without loss, the two similar circuits operating in double buffer or ping-pong mode.

More precisely, the data arriving on the terminal
DATA from connector 111 are applied to each of the data inputs of two shift registers 113, 113 '(for example,
HC 164) outputting eight simultaneous bits applied to a respective buffer register 114, 114 '(for example, EC 241) whose outputs are connected to a common bus 115.The shift registers 113, 113' and the buffers 114 , 114 ′ are controlled by a control circuit 112 receiving the CLK clock signal RDS as an input and delivering as output to the shift registers 113, 113 ′ modified clock signals CLK1 and CLK2 (illustrated in the timing diagram of the figure 3) and to buffers 114, 114 of the control signals Q and Q1
As can be seen in the timing diagram of FIG. 3, the clock signal CLK is firstly divided by eight by the divider IC1 (for example, an HC 161); this divided signal, as well as its corresponding complemented signal, are then logically added to the signal CLK to produce the signals CLKi and CLK2 applied respectively to the shift registers 113 and 113 '.

 It is thus seen that, during a period of eight clock pulses, the sequencing of the shift register 113 but not that of the shift register 113 ′ will be sequenced, and conversely during the following period of eight clock pulses.

 While one of the shift registers (for example, the shift register 113) is sequenced, and therefore being loaded, the other register (in this case, the register 113 ') is read as output by the intermediate of its buffer stage (here, 114 ′) which is then activated by the signals Q and Q / also produced by the circuit 112: the sequence of eight bits which had been loaded into the shift register 113 during the period of eight immediately preceding clock pulses are thus applied, in parallel, to the bus 115; meanwhile buffer 114, whose control inputs Q and Q / are inverted with respect to those of buffer 114 ', will see its output set to high impedance so as not to disturb the operation of the other register 114' and therefore the information applied to the bus 115 (the outputs of the buffers 114, 114 ′ are outputs in three-state logic).

The various circuits ICI to IC5 constituting the control circuit 112 are flip-flops and inverters in themselves conventional (for example ICi: EC 161, IC2: HC 138, IC3: HC 74, IC4:
HC 04 and IC5: HC 08) configured to produce the different control signals CLK1, CLK2, Q and Q / according to the sequence explained above; the combination of the different circuits results directly from the proper functions of these and will not be described in detail.

 FIG. 3 shows the detail of the second stage 120.

 The primary function of this second stage 120 is to transform the parallel data present on the internal bus 115 into serial data transmitted to external calculation means 300 in accordance with the universal standard RS-232C via the connector 121.

For this purpose, a UART (Universal Asynchronous Receiver-Transmitter) circuit 123 is used, for example an AY3-1015 appropriately configured, so as to deliver to a TXD terminal (Transmit
Data: data transmission) an asynchronous serial data stream at a rate determined by a time base 124 adjusted to a frequency compatible with the possibilities of the processing means 300, for example a rate of 9600 bits / seconds.

 The UART 123 is parameterized by a set of switches 125 making it possible to determine the number of bits returned (5,6,7 or 8), the existence or not of a parity check and, if this is the case, the even or odd parity).

 The other function of stage 120 is to receive data from the calculation means 300, also in the form of a serial stream in accordance with the RS-232C standard, and to transform this serial stream into parallel data allowing, via the connector 122, to control the liquid crystal display.

 The same UART 123 circuit is used, but functioning as a signal receiver; the signals received on terminal RXD (Receive Data: reception of data) of connector 121 are adapted in level and impedance by a stage 126 and applied directly to UART 123, which delivers directly as output, on its terminals RD0 to RD7 , the eight bits used to display the data.

These eight bits include, for example, four data bits (one byte then being transferred twice) and three control bits, one bit remaining unused. These signals are applied directly to the liquid crystal array via a simple buffer 128 (for example, a 74lu241).

 The UART 123, and therefore the interface circuit of the invention, can operate either autonomously or under the control of the computing means 300.

In the latter case, the CTS signals (Clear To
Send:: ready to send) and RTS (Request To Send) of the RS-232C standard. The signal CTS, received from the calculation means 300, and the signal RTS, sent towards the calculation means 300, are managed with respect to the UART 123 by a circuit 127; this circuit is, in itself, of a conventional scheme recommended for a UART of the type AY3-1015, and it will therefore not be described in detail.

 It will simply be noted that, to put it into service, it will be necessary to open the connection 129, which makes it possible to ensure the switching between an autonomous operation of the stage 120 (link 129 established) and a non-autonomous operation, with exchange RTS and CTS signals (link 129 deleted) under the control of the calculation means 300.

 We will now briefly describe how the signals transmitted by the interface circuit of the invention to the calculation means are processed by the latter.

 It will be noted that all of the software functions are executed by these calculation means, and therefore that the interface circuit of the invention - which is the only specific subset of reception assembly - is responsible for the execution of only hardware functions, which makes it possible to reduce the cost and the complexity accordingly.

 Beforehand, the means of calculation dialogue with the driver by asking on the display a certain number of questions which the driver can answer by pressing the keys of a numeric keypad 320. We can in particular list the various major traffic nodes by digital codes given by a card or table made available to the driver.

 For example, the driver may request the selection of the information corresponding to a given route by indicating the starting point and the finishing point (the calculation means then responsible for determining the corresponding significant sections and nodes of traffic), or else enter a unique section or traffic node number to obtain information on this single point.

 After this dialogue, the calculation means will carry out the actual processing of the signals delivered by the interfacing circuit 100.

First of all, in the continuous not of data which is transmitted to them asynchronously, they will perform a search for the start of the frame and ensure a timing and synchronization thereon; the RDS standard provides for this purpose, in each block of 104 bits, four 26-bit frames each comprising 16 bits of data proper and 10 bits of control and synchronization configured in a very precise manner. It is these control and synchronization bits that the calculation means will search for in the uninterrupted flow of data that they receive, in order to be able to extract the different successive data words from each frame.
Successive RDS transmitted.

 An error check is then carried out and, if necessary, a correction when this is possible (redundant error detection codes are indeed used).

 It is then verified, according to the identification information of the station contained in the RDS data stream, that we are indeed on the right station, that is to say the one which transmits the guidance data motorists and not on another station which does not transmit such data. In the event of an error, a message is applied to the display 400 asking the driver to modify the tuning of his car radio.

 We then operate the specific decoding proper: first of all, we extract from the RDS data stream the only information concerning guidance, by filtering all the other information systematically or optionally transmitted by the RDS system (name of the station, frequency of the closest transmitters, clear identification of the transmitter, date and time, radio text information, etc.).

Then, from among all of these guidance data, we extract the only information relating to the section (s) or traffic nodes previously selected during the dialogue with the driver.
The state of the nodes or sections thus selected is then transmitted in clear to the driver on the display 400 and / or by voice synthesis means (circuit 310 of FIG. 1) directly controlled by the calculation means 300.

 It is thus possible to display the identification in clear of the section or of the traffic node, followed by its corresponding state, also in clear; for example, the states can be: fluid, idle, dense or blocked (values automatically generated by the data collection system), not recommended or prohibited (states that can be forced from a control station), or an unspecified state.

 Such information can be easily presented on a display, of a commonly available type, of 1 or 2 lines of 40 alphanumeric characters.

Claims (3)

 1. An interfacing circuit for implementing a system according to one of the claims of the main patent, system in which a scrolling sequence of information is broadcast over the air by a method of broadcasting digital data under -carrier added to a broadcast transmission signal, the receivers on board vehicles being car radios equipped with a decoder ensuring the separation of the digital signal information from the audio program signal,  circuit (100) characterized in that it is connected to the broadcasting receiver (200) and to means (300) for digital data processing, and in that it comprises a first stage (110) receiving as input, in from the radio, on the one hand a clock signal (CLK) and on the other hand the digital signal information (DATA) in the form of a synchronous serial data stream sequenced on this clock signal and delivering as output this same digital signal information in the form of an asynchronous parallel data stream, this first stage comprising two similar shift registers (113, 113 ') and control means (112) operating such that the registers are loaded successively and alternately by portions of the synchronous data stream, the content of one of the registers being, after completion of the loading, read in parallel form while the other register is being loaded, and vice versa,  the information at the output of this first stage then being decoded and discriminated by the processing means delivering to display means (400) corresponding signals.  2. The interface circuit of claim I, further comprising a second stage (120) receiving as input the asynchronous parallel data stream delivered by the first stage (110) and outputting an asynchronous serial data stream (TXD ) checked against RS-232C standards for transmission to the processing means.  3. The interfacing circuit of claim 2, in which the second stage (120) receives as input, from the processing means, a serial data stream (RXD) in RS-232C standards and transforms this received serial stream into a parallel flow suitable for controlling the display means (400).