FR2649265A1 - AMPLIFIER-SEPARATOR CIRCUIT FOR TTL-CMOS CONVERSION - Google Patents

Abstract

The invention relates to logic level conversion circuits. An amplifier-isolator circuit for TTL-CMOS conversion comprises a first circuit 10 comprising a relatively fast inverter, and a second circuit 12 comprising a relatively slow inverter, which is connected to the first circuit and which controls the operation of the inverter P1, N1, P3 which is part of the first circuit to ensure that noise pulses of positive or negative direction and of short duration, with an amplitude of up to 2.4 volts, do not erroneously affect the output level. Application to microelectronics.

Description

The present invention relates generally to circuits

  input splitter amplifiers, and more particularly it relates to an input splitter amplifier for converting low level signals to higher level signals.

  In many semiconductor integrated circuits,

  modern, it is necessary to convert a signal

  low level logic input into a logic output signal.

  tie having a higher level. For example, it is often necessary to convert a TTL input signal, which typically varies between 0 and 3.0 volts for a logical "0" and a "1" logic, so as to obtain a level CMOS excursion. higher, which is between 0 and 5

  volts. For TTL circuits to be capable of

  CMOS circuits, it is necessary to incor-

  port an interface or an amplifier-splitter between the two circuits, to convert TTL logical levels

  relatively low, to give higher levels

  which CMOS circuits can work reliably.

  A TTL-conversion amplifier-splitter

  CMOS relatively simple is a CMOS inverter that receives a TTL level input signal and provides a

  CMOS level output signal. This amplifier-separator

  Inverter TTL-CMOS includes an NMOS transistor which is approximately five times larger than the transistor

  PMOS, instead of having a width equal to half of this

  PMOS transistor, as is usual in an invert-

  CMOS type of characteristic. Therefore,

  With the use of a +5 volts supply voltage, this CMOS inverter will typically switch its output signal through the entire 5 volt CMOS range when its input signal passes

  about 1.5 volts, instead of about 2.5 volts, corre-

  at the switching point in a normal CMOS inverter

  wrong. Separate amplifier circuits are also known

  more complex functionors, and examples of such circuits are described in the patents

  United States of America Nos. 3,755,690 and 4,048,518.

  A switching point of 1.5 volts for this inverter is suitable for operation with a TTL input signal, because the TTL convention is that a voltage level of 2.0 volts or more is considered a "'1" logic, while a voltage level of 0.8

  volt, or less, is considered a logical "0". How-

  However, these TTL limits of 0.8 volts and 2.0 volts are a DC specification. A TTL circuit is usually operated under AC conditions, with an excursion of 0 to 3 volts, which places the

  switching point of 1.5 volts of the amplifier-sepa-

  simple controller in the middle of the input TTL signal range.

  If the input amplifier-splitter has a switching point of 1.5 volts, and if the input voltage varies

  normally between 0 volts and 3 volts, it is said that amplification

  The separator has a noise margin of about 1.5 volts either side of the switching point. In other words, if we assume that the input signal is at 0 volts, we can

  tolerate a short-lived noise pulse of

  sitive, whose level rises to almost 1.5, so no error is introduced into the output level of the amplifier-splitter if a noise pulse of this

  level appears at the entrance. Similarly, if we

  that the input signal is at 3.0 volts, we can tolerate

  in this amplifier-separator a negative-direction noise pulse of about 1.5 volts only. Therefore, this known input amplifier amplifiers can not tolerate positive sense or sense pulses

  negative values greater than 1.5 volts, which means that

  noise levels at these levels cause the appearance of a

  incorrect CMOS level due to one of the levels of

TTL, or both.

  An object of the present invention is to provide an improved TTL-CMOS amplifier amplifier, with a

  higher noise margin, that is to say an amplifier-

  separator that is able to tolerate higher level noise pulses.

  The amplifier-separator of the invention is

  to tolerate positive-sense noise pulses of about 2.4 volts superimposed on a 0 volt input signal, and to tolerate negative-going noise pulses of about 1.8 volts superimposed on a signal entry

  3.0 volts. The amplifier-splitter of the present invention

  The specification satisfies the 0.8 volt DC TTL specification for a logic "0" and 2.0 volts for a logic "1". The amplifier amplifiers of the invention make it possible to achieve these apparently contradictory objectives in

  taking advantage of the fact that the input noise is

  short-lived (a few nanoseconds to a few tens of nanoseconds), while the input voltages corresponding to the current TTL specification

  continuous have a much longer duration.

  The input amplifier-splitter circuit of the present invention comprises two separate paths between its input and its output. The first is a fast AC path that switches between logic states "0" and "1" at a high switching voltage of about 2.5 volts, on a rising input signal that rises from 0 to 3 volts, and which switches between logic states "1" and "0" at a low switching voltage of about 1.1 volts on

  a descending input signal that goes down from 3 to 0 volts.

  The second path, which. controls the operation of the first path, is a DC path operating at a lower speed, which has a low switching voltage of about 1.1 volts for both the increasing input signals and the decreasing input signals . In

  setting different switching voltages in

  alternating current and direct current, and by creating an ef-

  hysteresis for the AC path, the am-

  TTL-CMOS splitter-splitter of the invention presents a

  better ability to reject noise peaks from

  high frequency, compared with amplifi-

classical separators.

  To achieve the above goals as well as additional goals that may appear later,

  the invention consists of an amplifier-separator of

  advanced type TTL-CMOS which is defined in subs-

  in the appended claims and which is described

  in the description that follows, taken together with the

drawings in which:

  FIG. 1 is a diagram of an amplifier-se-

  TTL-CMOS input parser according to a mode of

  of the present invention; Figure 2 shows a transfer curve in

  alternating current between the input voltage Vin and the voltage

  output voltage Vout for the amplifier-separator

  trea of the invention; and Fig. 3 shows a DC transfer curve between the input voltage Vin and the output voltage Vout for the input amplifier-splitter of the invention. In general, the TTL-CMOS amplifier / separator of the invention, which is exemplified by its embodiment diagrammatically shown in FIG. 1, comprises a first fast or AC path, and a second, slower path, or DC, 12. The two paths 10 and 12 are connected between an input node 14, which receives an input TTL level signal.

  Vin, and an output node 16, on which one obtains a

  CMOS level output signal, Vout.

  The first path 10 includes an inverter

  which includes PMOS transistors P3 and Pi and a trans-

  NMOS sistor, connected in series between a voltage of

  tion, which is here represented by a voltage of +5 volts, and a reference potential, which is here represented by the mass. The larger the width / length (W / L) ratio of a transistor, the greater the drain current that transistor can circulate for the same gate voltage. The preferred width / length (W / L) ratios, with dimensions expressed in microns, are shown in FIG. 1 for each of these MOS transistors, as well as for all other MOS transistors that are incorporated in the amplifier-splitter circuit of Figure 1. It should be noted, however, that these dimensional ratios are given purely by way of example and in no way limit

  nothing the scope or scope of the invention. As an example

  these reports would change if para-

  meters of different electrical processes.

  The W / L ratios for the inverter constituted by the transistors N1, P1 and P3 are selected so that its switching voltage for Vin is about 2.5 volts if the gate of the transistor P3 is at 0 volts. The gates of transistors P1 and Ni are connected to the input node of

  Vin, 14, and an inverter node 18 is set to their

  common drain nexion. Node 18 is connected to the grills

  the transistors P2 and N2, which are connected between the + 5 volts supply and ground. P2 transistors

  and N2 form a second inverter stage. An inversion knot

  20 to the common drain connection of the P2 transistors

  and N2 is connected to the output node of Vout, 16.

  The less rapid DC path, 12, includes an input inverter stage consisting of

  transistors P4 and N3 which are connected between the power supply

  at +5 volts and the mass. W / L ratios for the inverse

  N3, P4 are lower than the corresponding ratios for the inverter P1, Ni, and are selected to establish a switching point of the inverter N3, P4 at a voltage Vin of about 1.1 volts. The gates of transistors P4 and

  N3 are connected to the Vin node, 14, and a node of

  Pourer 22 is formed at their common drain connection. The node 22 is connected to the gates of the transistors P5 and N4, which are connected between the +5 volts supply and the ground. The inverter output node 24 at the common drain connection of the transistors N4 and P5 is connected to the gate of the transistor P3 and to one side of a capacitor C1, the other side of which is connected to ground. Cl represents the parasitic capacitance plus the input capacitance of the transistor P3, and its value can be typically

the order of 0.1 pF.

  The slower path 12 also includes a second inverter constituted by transistors P6 and N5 connected between the + 5 volts supply and the ground. The gates of the transistors P6 and N5 are connected to the output node Vout, 16. An output inverter node 26 to the common drain connection of the transistors N5 and P6 is

  connected to the gate of transistor P7. The source of the

  sistor P7 is connected to +5 volts and its drain is connected

  to the output node 24 of the inverter stage which is con-

  by the transistors P5 and N4, as well as

  C1 and to the gate of transistor P3.

  The operation of the amplifier-amplifier circuit of FIG. 1 can now be described with reference also to the AC and DC transfer curves of the fast and slow paths 10 and 12, which are respectively shown in FIGS. 2 and 3. There are four cases to consider: 1) the voltage Vin is subjected to a pulse that changes it from 0 volts to 3.0 volts and brings it back to 0 volts, to represent a real signal; 2) the tension Vin is subjected to an impulse which makes it pass

  from 0 volts to 2.4 volts, which brings it back to 0 volts to

  feel a sound of positive sense; 3) the voltage Vin is subjected to a pulse that changes it from 3.0 volts to 1.2 volts and brings it down to 3.0 volts, to represent a noise of negative direction; and 4) Vin voltage is switched

  between 0.8 and 2.0 volts in con-

  tinu. For case 1), if the voltage Vin goes from 0 to

  3.0 volts, the nodes 18 and 22 go immediately to the

  low, because the 3.0 volt input signal is greater than the switching points of the two inverters, and

  is therefore high enough to switch both

  pourer N1, P1, P3 and the inverter N3, P4. A low level at node 18 causes nodes 20 and Vout to go high, thereby switching inverter P6, N5 and causing node 26 to go low. A low level on the node 22 blocks the transistor N4, and a low level on the node 26 unblocks the transistor P7. When the transistor P7 is thus unlocked, the node 24 immediately goes to +5 volts, which blocks

  the transistor P3. When Wine returns to 0 volts, the

  sistor P4 becomes conductive and the node 22 goes high, but because the transistor P3 is blocked, the node 18 remains at low level although the transistor P1 is

  driver. The high level at node 24 unlocks the trans-

  tor N4, and the node 24 goes low, because because of its W / L ratio higher than that of the transistor P7, the transistor N4 exerts a preponderant action on that of the transistor P7 which is also conductive at this time . Once node 24 is at the low level, the

  transistor P3 becomes conductive, and because the

  sistor P1 is conductive, node 18 goes high.

  The level on node 18 is reversed in the invert.

  P2, N2 and Vout goes low, while the node 26 goes high, which blocks the transistor P7. For case 2), if Vin goes from 0 to 2.4 volts, the

  input voltage is not high enough to

  immediately turn node 18 down, but the node

  22 of the inverter P4, N3 immediately switches to the

  because its switching point is only

  about 1.1 volts. A low level on the node 22 blocks the transistor N4 and unblocks the transistor P5. The transistor P5 is relatively long and narrow, so that although it is conductive, it constitutes a weak current source and it only slowly charges the node 24 to

a positive potential.

  If Vin is at 2.4 volts for only a few nanoseconds before returning to 0 volts, as would typically be the case with a noise pulse,

  node 24 does not rise to a positive potential no-

  table before being brought back to earth by the unlocking of transistor N4. If node 18 does not go low,

  the voltage Vout, which is the output voltage of the invert-

  N2, P2, does not go high. If Vin remained at 2.4 volts for a long time, which is not the case for a noise pulse, the gate of transistor P3 would eventually go to the off state and a 2.4 volt input level would be enough to switch node 18 to

low level and Vout high.

  In case 3), if Vin is at 3.0 volts, this if-

  that the gate of transistor P3 is at 5.0 volts and that transistor P3 is off. If Vin then drops to 1.2 volts, the transistor P1 becomes conductive, but because the transistor P3 is off and is connected in series with the transistor Pi, the node 18 does not go high, and the voltage Vout remains at the high level. If Wine falls

  only at 1.2 volts, this voltage will not be enough

  low to switch the node 22 to the high level, which would be necessary to switch the node 24 to the low level

  and to unblock the transistor P3. For this case of an im-

  negative sense drive, even a long noise signal

  duration will not switch Vout to a low level, unless the impulse

  input voltage falls below 1.1 volts.

  For the case 4) corresponding to conditions of

  DC, the inverter N3, P4 controls the situation.

  For a voltage Vin less than 0.8 volts, the node 22 is

  at the high level, the node 24 is at the low level, the

  tor P3 is conductive, the transistor P1 is conductive, the

  node 18 is high, and Vout is low.

  For a wine level higher than 2.0 volts, the transistor

  Neither is conductive, transistor P1 is partially

  conductor, the node 22 is low, the node 24 is high (after a sufficient time), the transistor P3 is blocked, the node 18 is low and the nodes

and Vout are at the high level.

  In addition to effectively reducing the effect of noise on Vin, the input amplifier-splitter

  the invention also attenuates the noise of the mass. The re-

  Mass towers that are shown in Figure 1 are ideal returns. Typically, because of the inductance, a high-speed chip will have noisy mass returns that will not be exactly zero volts. For example, a pulse of

  positive sense ground noise in the ampli-

  separator of Figure 1 would be equivalent to an im-

  negative noise impulse on Wine. If Vin must cor-

  respond to a logical "1" at 3.0 volts, the circuit can withstand a positive mass noise up to 1.8

  volts, before switching incorrectly. In a similar way

  If Vin corresponds to a logical "0" of 0 volts, a negative sense ground noise of up to 2.4 volts

  will still not cause a logical

correct.

  It can be seen that the amplifier-separator of

  TTL-CMOS system of the invention effectively

  incorrect logical mutation that would be caused by

  noise signals up to 2.4 volts. It is also necessary to

  It should be noted that modifications may be made to the embodiment of the invention which is described here specifically without necessarily going beyond the spirit and

framework of the invention.

Claims (32)

  An amplifier-splitter comprising an input (14) and an output (16), characterized in that it comprises a first circuit (10) connected between the input (14) and the output (16), and comprising at least a switching element (P3), and a second circuit (12) which is connected between the input and the output, and the first circuit (10), and which controls the operation of the switching element ( P3).   2. Amplifier-separator according to the claim   1, characterized in that it further comprises charging means (C1) connected to the switching element   (P3) 'and the second circuit (12), this second circuit comprises   means (P5, N4) for supplying a charging current to the charging means (C1), for charging the means   charging at a high voltage or a low voltage.   3. Amplifier-separator according to the claim   2, characterized in that the first circuit comprises   a first inverter (Pi, Ni, P3) having a connected input   at the input (14) of the amplifier-splitter, and   taking the aforementioned switching element (P3), and a second inverter (P2, N2) having an input connected to the output (18) of the first inverter (Pi, N1, P3), and an output (20)   connected to the output (16) of the amplifier-splitter.   4. Amplifier-separator according to the claim   3, characterized in that the first inverter (P1, Ni, P3) comprises first and second transistors (P1, N1) whose output paths are connected in series and whose gates are connected to the aforementioned input (14). ), the switching element (P3) having an output circuit which is connected between a supply voltage and the output circuits of the first and second transistors (P1, Ni).   5. Amplifier-separator according to the claim   4, characterized in that the means providing a   current comprises a third transistor (P5) which, when   it is conductive, charging the charging means (C1) to one of the above-mentioned voltages, with a first low speed, and a fourth transistor (N4) which, when it is conducting, charges the charging means (C1 ) to a second   voltage with a second higher speed.   6. Amplifier-separator according to the claim   5, characterized in that the fourth transistor (N4) has a width / length ratio, or W / L, higher than that of the third transistor (P5).   7. Amplifier-separator according to the claim   6, characterized in that the output circuits of the third and fourth transistors (P5, N4) are connected between a voltage source and a reference potential, an output node (24) is set at the connection point   output circuits, and this output node (24) is connected to the charging means (Cl).   8. Amplifier-separator according to the claim   7, characterized in that the second circuit (12) comprises   takes a third inverter (P4, N3) which is connected to the aforementioned input (14), and a fourth inverter (P5, N4) which is connected to the output of the third inverter (P4, N3), and which includes the third and fourth transistors (P5, N4).   9. Amplifier-separator according to the claim   8, characterized in that it further comprises a   fourth inverter (P6, N5) in the second circuit (12), whose   the input is connected to the output (16) of the amplifier-   separator, and a fifth transistor (P7) whose gate is connected to the output (26) of the fifth inverter (P6, N5), and whose output terminal is connected to the means   charge (Cl) and at the output node (24) of the fourth pourer (P5, N4).   10. Amplifier-separator according to the claim   2, characterized in that the means providing a   current comprise a first transistor (P5) which, when   it is conductive, charges the charging means (Cl) to   a first voltage, with a first relative speed   a second transistor (N4) which, when it is conducting, charges the charging means (C1) to a second   conde tension, with a second higher speed.   11. Amplifier-separator according to the claim   10, characterized in that the second transistor (N4) has a ratio width / length, or W / L, higher than that of the first transistor (PS).   12. Amplifier-separator according to the claim   11, characterized in that the output paths of the first and second transistors (P5, N4) are connected in   series between a voltage source and a reference potential.   ence, an output node (24) is established at their point of   common output connection, and this output node of the in-   pourer is connected to the charging means (Cl).   13. Amplifier-separator according to the claim   1, characterized in that the first circuit (10) comprises   takes a first inverter (P1, Ni, P3) having an input connected to the input (14) of the amplifier-splitter, and comprising the aforementioned switching element (P3), and in that the second circuit (12) ) comprises means which are connected to the switching element (P3) to control its operation, thereby preventing operation of the first inverter (P1, N1, P3) under the effect of a signal   short-term noise present at the entrance (14).   14. Amplifier-separator according to the claim   13, characterized in that the control means   take means (C1) connected between the communication element   mutation (P3) and the second circuit (12), the latter   additionally taking steps to establish at one level   one of two voltage levels, a control voltage of feel on the control means.   15. Amplifier-separator according to the claim   14, characterized in that the control means   take means of charge (Cl), and the means of   of the voltage comprise means (P5, N4)   arranged to supply power to the charging means (C1), for charging said charging means to one of the voltage levels with a first high speed, and for charging the charging means (C1) to a second voltage level with a second low speed.   16. Amplifier-separator according to the claim   characterized in that the means which supplies a current comprises a first transistor (PS) which, when conducting, charges the charging means (C1) at one of the above-mentioned voltages with a first speed, and a second transistor (N4) which, when conducting, charges the charging means (C1) to a second voltage with a second speed.   17. Amplifier-separator according to the claim   16, characterized in that the second transistor (N4) has a ratio width / length, or W / L, greater than that of the first transistor (P5).   18. Amplifier-separator according to the claim   17, characterized in that the output paths of the first and second transistors (P5, N4) are connected between a voltage source and a reference potential, an inverter output node (24) is set at the connection point said output paths, and this inverter output node (24) is connected to the load means (C1).   19. Amplifier-separator according to the claim   14, characterized in that the first inverter (P1, N1, P3) comprises first and second transistors (P1, Ni) whose output paths are connected in series and whose gates are connected to the input (14). , and the element   switching device (P3) having a connected output path   be a supply voltage and the output path of the   first and second transistors (Pi, Ni).   20. Amplifier-separator according to the claim   3, characterized in that the second circuit (12) comprises   takes a third inverter (P4, N3) having a con-   connected to the input (14) of the amplifier-separator, the first inverter (P1, N1, P3) comprising first and second transistors (Pi, Ni), the third inverter (P4, N3) comprising third and fourth transistors (P4, N3), and the first and second transistors (Pi, N1) having width / length ratios, or W / L, greater than those of the third and fourth transistors (P4, N3), by virtue of   what the first inverter (Pi, N1, P3) has a communication point   higher than the third inverter (P4, N3).   21. Amplifier-separator according to the claim   20, characterized in that it further comprises a quadrature   third inverter (P5, N4) having an input connected to the output of the third inverter (P4, N3) and an output (24)   connected to the switching element (P3).   22. Amplifier-separator according to the claim   21, characterized in that it further comprises a   fourth inverter (P6, N5) having an input connected to the output (20) of the second inverter (P2, N2), and a fifth transistor (P7) having an output path connected between   a source of voltage and the output (24) of the fourth invert-   (P5, N4), and a control gate connected to the   output of the fifth inverter (P6, N5).   23. Amplifier-separator according to the claim   1, characterized in that the first circuit (10) comprises   takes a first inverter (Pi, N1, N3) having an input connected to the input (14) of the amplifier-splitter, and having a first switching voltage, and the second circuit (12) comprises a second inverter ( P4, N3) having   also an input connected to the input (14) of the amplifier   separator, and having a second voltage of   lower than the first switching voltage.   24. Amplifier-separator according to the claim   23, characterized in that the first and second invert-   (Pi, Ni, N3, P2, N2) respectively comprise a   pair of complementary transistors, and the   geur / length, or W / L, transistors of the first inverter (Pi, Ni, N3) are greater than those of the second inverter (P2, N2).   25. Amplifier-separator according to the claim   23, characterized in that the switching element   (P3) is part of the first inverter (P1, Ni, N3).   26. Amplifier-separator according to the claim   25, characterized in that it further comprises charging means (C1) connected to the switching element   (P3) and the second circuit (12), and that the second circuit   (12) comprises means (P5, N4) for supplying   a charging current to the charging means (Ci), for charging   load means at a high voltage or voltage low voltage.   27. Amplifier-separator according to the claim   25, characterized in that the first inverter (Pi, Ni, N3) comprises first and second transistors (Pi, Ni) whose output circuits are connected in series and whose gates are connected to the input (14) , and in that the switching element (P3) has an output circuit which is connected between a supply voltage and the output circuits of the first and second transistors (Pi, Ni).   28. Amplifier-separator according to the claim   27, characterized in that the current supplying means (P5, N4) comprises a third transistor (P5) which, when conducting, charges the charging means   (Ci) to one of the above-mentioned tensions, with a first   low frequency, and a fourth transistor (N4) which, when   it is conductive, charges the charging means (C1) to   a second voltage, with a second higher speed.   29. Amplifier-separator according to the claim   28, characterized in that the fourth transistor (N4) has a width / length ratio, or W / L, greater than that of the third transistor (P5).   30. Amplifier-splitter according to claim 29, characterized in that the output circuits of the third and fourth transistors (P5, N4) are connected between a voltage source and a reference potential, an output node (24). is established at the connection point of   these output circuits, and the output node (24) is connected to the charging means (C1).   31. Amplifier-separator according to the claim   30, characterized in that the second circuit (12) comprises   takes a third inverter (P4, N3) connected to the input   (14), and a fourth inverter (P5, N4) connected to the output   of the third inverter (P4, N3) and comprising the third   sth and fourth transistors (P5, N4).   32. Amplifier-separator according to the claim   31, characterized in that it further comprises a   fourth inverter (P6, N5) in the second circuit (12),   whose input is connected to the output (16) of the amplifier   separator, and a fifth transistor (P7) whose   gate is connected to the output (26) of the fifth invert-   (P6, N5), and whose output terminal is connected to the load means (C1) and the output node (24) of the fourth inverter (P5, N4).