FR2642867A1 - DEVICE FOR IMPLEMENTING BY MATERIAL A DIGITAL COMPARISON LOGIC IN A GRAPHIC VIDEO DISPLAY SUBSYSTEM - Google Patents

Abstract

This device makes comparisons between pairs of coordinates of an object to be displayed which is either a quadrilateral to be drawn or an image block to be moved. A registration window is defined by top, bottom, right, and left registration coordinates, and a test window with predetermined X and Y offsets. According to the invention, the device comprises: a) loading means, for loading a plurality of object coordinate registers 37 by said object coordinates (X0, YO to X3, Y3) a plurality of coordinate registers of framing 39 by said framing coordinates (XClipMin, XClipMax, YclipMin, YClipMax) and a plurality of shift registers 41 by said predetermined offsets (XRasOff, YRasOff); b) comparator means, connected to the loading means, for performing said comparisons; c) calculating means, connected to the shift registers and to the registration coordinate registers, for calculating the limits of the test window with respect to the limits of the registration window; d) multiplexer means, for selecting some of said comparisons; e) register means for storing these comparisons which have been selected; and f) comparison control means 49; to control the operation of the comparator means, the multiplexer means and the register means.

Description

The present invention relates to a device making it possible to

  implement, by hardware, a framing comparison logic in a graphic display subsystem. Framing is necessary when it is defined that an object to be displayed must be contained on a partial video display only, within the limits of a predetermined window. For example, if you define a rectangular window in the upper-left corner of a video display, and you have defined a line from the upper-left corner to the lower-right corner of the display, you do not want will not display the part of the line that is outside the defined window; in other words, we will have to "frame" it, that is to say the re-cut or cut. Also, if a line of text is wider than the window, the part of the line of text that is outside the

  window must also be "framed" (cut).

  Framing is usually done by software. The present invention, on the contrary, executes the calculations, operated by a graphics subsystem, relating to the comparisons necessary for the framing of the images to be displayed on a video display, as far as possible by hardware, the software being implemented only for those of images, or parts of images, which can not be framed

  appropriately by the hardware of the graphics subsystem.

  The invention also ensures obtaining all the comparisons between coordinates necessary to obtain the restitution of objects consisting of arbitrary quadrilaterals and the execution of block image transfers or BLITs (BLock

  Image Transfers) by the graphics subsystem.

  For this purpose, the invention proposes a device for making comparisons between pairs of coordinates - of an object to be displayed by means of a graphic subsystem, this object being either a quadrilateral to be plotted or an image block. to move, this device having a registration window with predetermined top, bottom, right and left registration coordinates and a test window with predetermined X and Y offsets relative to said top and bottom, and with respect to said right and left, the coordinates of the object, the framing coordinates and the offsets for calculations intended for

  the execution of the framing of the object before its display.

  According to the invention, this device comprises: a) loading means, for loading (i) a plurality of object coordinate registers by said object coordinates, (ii) a plurality of coordinate coordinate registers by said coordinate coordinates, and (iii) a plurality of offset registers by said predetermined offsets, b) comparator means, connected to the loading means, -to perform said comparisons, c) calculation means, connected to the shift registers and to the coordinate coordinate registers, for calculating the limits of the test window with respect to the boundaries of the registration window, d) multiplexer means, for selecting some of said comparisons, e) register means, for storing such comparisons as f) comparison control means for controlling the operation of the comparator means, means for controlling

  multiplexers and register means.

  We will now describe an example embodiment,

  illustrated in the accompanying figures.

  FIG. 1 is a block diagram of a workstation graphics subsystem according to FIG.

present invention.

  FIG. 2 is a block diagram of the coordinate step portion of the graphics subsystem according to

the invention.

  Figure 3 is a detailed block diagram of

  the adder 31 and the multiplexer 35.

  Figure 4 is a detailed block diagram of

X / Y coordinate registers 37.

  Figure 5 is. a detailed block diagram of

  coordinate coordinate registers 39.

  Figure 6 is a detailed block diagram of the register

frame offset 41.

  Figure 7 is a block diagram of the circuit

  to control the text window 45.

  Figure 8 is a detailed block diagram of the

  comparison logic and result memory 47.

  Fig. 9 is a table showing the relative sequencing of the load control state machine 35 and the comparisons performed by the comparison logic

and result memory 47.

  Figure 10 is a truth table using the

  comparison results for the XO coordinate.

  FIGS. 11a and 11b are truth tables using comparisons between each of the four vertices X and each of the four vertices Y. FIGS. 12a to 12d define a truth table using comparisons between the four vertices X and the

  four Y vertices and framing boundaries.

  Figure 13 defines a truth table using comparisons between the four X and Y vertices and the boundaries

test windows.

  Figure 14 defines a truth table giving the direction in which objects will be drawn or in

  which will perform the block image transfers.

0

  The present invention relates to a graphic subsystem of an engineering work station, and more particularly to a hardware implementation that makes it possible to obtain the information necessary for carrying out the operations required to frame the parts of the workstation. imagery

  and text that goes beyond a window that has been defined.

  The logical blocks of coordinate staging and comparison of coordinates (see FIG. 1) are intended to ensure the necessary storage and comparison of the information necessary to restore arbitrary quadrilaterals with framing, as well as for image block transfers with framing. In either case, it is necessary to specify four pairs of X / Y coordinates and

  to specify the boundaries of the frame window.

  The possibility of restoring quadrilaterals implies that we have four vertices that will define the quadrilateral. The embodiment of the present invention described here imposes very few constraints on these vertices. These are stored in four pairs of registers (a pair of registers consisting of a register for the X coordinate and a register for the Y coordinate), and are referenced by the vertex numbers O to 3. The vertex O is implicitly attached to the vertex 1, the vertex 1 to the vertex 2, 'the vertex 2 to the vertex 3 and the vertex 3 to the vertex 0. No attachment between the vertices O and 2, or 1 and 3 for example, is expected. The coordinate and comparison staging logic forms the initial stages of a pipeline which, at the end of the chain, will perform the rendering in the display memory of the specified quadrilateral. The following stages of the pipeline need information about the relationship between each adjacent vertex and its neighbors (for example, for the vertex 1: X1 with respect to XO, Y1 with respect to Y0, X1 with respect to X2 and Y1 with respect to at Y2). This information is necessary to properly deliver to the addressing functional block a series of trapezes which, when combined, will represent exactly the original quadrilateral. The decomposition of any quadrilateral is

  realized by the logic of sequencing of the coordinates.

  In addition, to allow the quadrilateral framing on the framing boundaries in subsequent stages of the pipeline, the relationships between the vertices and the appropriate framing boundaries are needed. This means, for example, that all X vertices will be compared to the X minimum framing limit and the X maximum framing limit. A similar set of comparisons is similarly needed for Y vertices. In some cases, these comparisons can indicate whether an object has visible parts (not framed), or if it does not have any at all. By identifying in advance the objects that will not be visible, it is possible to avoid the use of the following stages of the pipeline, because it has been identified that no visible pixel will have to be written in the display memory. This is advantageous in terms of performance, since the quadrilateral restitution can be considered to have taken place immediately after analysis of the registration information. The preferred embodiment of the graphical system described herein uses, in determining the pixel associated with a line segment, a two-by-sixteen bit complementation operation. This operation means that we take the difference between the two vertices X and the two vertices Y of the line segment. To avoid a mathematical overflow, we must limit the range of the numerical values of the vertices X and Y so as to be able to represent them on fifteen bits, that is to say that they will have to be between -214 and 214-1l. To enable this, the coordinate comparison logic performs a control

  of the numerical extent of the vertices.

  The ability to perform block image transfers also requires four vertices, two of which specify opposite angles. of a source rectangle and the two others specify the opposite angles of a destination rectangle. The purpose of the image block transfer operation is to copy in the destination rectangle the pixels contained in the source rectangle. In the current embodiment, the upper left corner of the source rectangle is stored at vertex 0, while the bottom right corner of the source rectangle is at vertex 1. In the same way, the upper left corner of the destination rectangle is located at the top 2 and the lower right corner of the rectangle at the top 3. To correctly copy the source rectangle to the destination rectangle, we must be careful if the two rectangles overlap. If this is the case, we must copy the pixels in a certain order if we want to obtain the correct result. This problem is well known to those skilled in this art. The information needed to properly determine pixel copy constraints involves comparing the limits

  the source rectangle and the bounds of the destination rectangle.

  This is necessary for both X coordinates and

  for the relevant Y coordinates.

  In addition, to allow both the source rectangle and the destination rectangle to be framed in subsequent stages of the pipeline, the relationships between the source and destination vertices and the appropriate framing boundaries are needed. Here again, it can be determined that either of the source or destination rectangles is totally hidden (invisible), thus avoiding the use of subsequent stages of the pipeline. This is advantageous in terms of performance, since it can be considered that the execution of the image block transfer took place immediately after

  the analysis of the framing information.

  The control logic of the coordinate layering makes it possible to obtain the coordinate values in several ways. In this respect, the coordinate comparison logic retains the necessary comparison information regardless of how the coordinate values are delivered. The various methods of obtaining the coordinates can be designated abbreviated as absolute value process, indexed value method and relative value method. The particular method that will be used is determined by the address of the register that the central processing unit will use to identify the

or the registers to load.

  An absolute coordinate value is loaded by storing the actual value delivered by the central processing unit in the addressed register. This loading method is used to load the framing limits registers and the frame shift registers that are

Z642867

  -7 will describe below, as well as the individual coordinate registers. The second method, that in indexed value, is used to efficiently load a plurality of coordinates by the same values. In this case, the value delivered by the central processing unit is first added to the appropriate frame shift register (either the frame shift register X or the field offset register Y) before storing it. in one or more coordinate registers. The addition of the frame offset makes it possible to shift the addressed X / Y domain given by the central processing unit to a different area of the display memory. The indexed load process uses a two-bit index for its registration and determines the number and identity of

  coordinates to be loaded during any given cycle.

  It is thanks to this process that the central processing unit can simply specify a single X / Y pair to identify a degenerate quadrilateral, ie a point, or two X / Y couples for a segment , or three X / Y couples for a triangle. When one of these degenerate quadrilaterals is loaded into the four vertex registers, one or more vertices can be duplicated. This is necessary so that the next stages of the pipeline can always interpret the object defined as being a quadrilateral (even if it is degenerate> and not treat as special cases all the objects of lower rank (that is to say points, segments or triangles.) The indexing loading process also allows to introduce only the opposite angles of a rectangle to define properly

  the four angles of the corresponding quadrilateral.

  The last loading method, in relative value, is used to allow the CPU to specify only the difference between the last coordinate

  introduced and the new coordinate value considered.

  In this case, before loading into one or more registers, a difference or offset delivered by the central processing unit is added to the coordinate previously loaded. The two-bit index is used to identify, for the addition that must be made, the last coordinate entered [vertex (index-1) modulo 4] and also to identify the one or those of the registers that must be load, as in the case of indexed loading. In the end, the central processing unit is free to choose, from all possible means, those by which the loading of the coordinate registers will be carried out. When an operation, whether it is the rendering of a quadrilateral or an image block transfer, is actually requested (after the coordinates have already been loaded), the current state is used directly. of the four summits, regardless of how they were obtained. This provides the CPU with the utmost flexibility of operation. Fig. 1 is an overview of a graphics subsystem in which the present invention can be used. A bus interfacing logic 11 is connected to a central processing unit (not shown) via address, data and command buses. The functional components of the graphics subsystem are the data and memory routing interface 13, the coordinate staging section 15, the coordinate sequencing section 17, the functional addressing block 19, the mask generating block 21 and the

  linear address generator 23.

  The data routing interface and memory 13 updates a frame buffer (not shown), which is a memory retaining the graphic information to be displayed on a video display such as a cathode ray tube. In other words, the data loaded in the frame buffer will be accessed by the video circuits which will convert these data into appropriate electrical signals which, in turn, will produce the illumination or extinction of the different pixels of the display. video. The data from the bus interface logic is modified by the mask generator block 21 and the linear address generator 23 as a function of the processing performed by the coordinate staging section 15, the coordinate sequencing section 17 and the functional addressing stage 19. The functional addressing stage 19 also performs a part of the registration necessary for the adaptation of particular graphic objects to the registration window where they must be displayed, and then transfers the signals. at the mask generator stage 21, which configures the information in sixteen pixel fractions which, for each scanning line, go from the beginning to the end of the visible object and are used to address the interface of

  data routing and memory 13.

  The mask generation signals are also delivered to the linear address generator 23, which translates the addresses delivered by the mask generator stage 21 into signals making it possible to linearly address the frame buffer for output transfer to the display. Embodiments of the memory interface and data routing block 13, the coordinate sequencing logic 17, the functional addressing block 19 and the linear address generator are disclosed in other applications, including

  course of issue, belonging to the Applicant.

  The present invention relates to the circuits of the coordinate staging block 15 which perform certain operations according to the inputs applied thereto, the features of which will be described below with reference to FIGS. 2 to 14, to produce information having the nature of control signals and intended to allow a graphics subsystem to perform a restitution of arbitrary quadrilaterals with framing, and image block transfers with framing. The present invention thus relates to the particular circuits located at

  inside the coordinate staging section 15.

  The implementation of the various sequencing and control signals necessary for the proper operation of the above-mentioned functional blocks which constitute a video display subsystem are well known to those skilled in the art and will therefore not be described here at exception of the elements necessary for

  understanding of the present invention.

  Referring now to FIG. 2, there is shown a block assembly diagram of the coordinate staging section. The coordinate staging section 15 comprises an adder 31, a loading control state machine 33, a multiplexer 35, XY coordinate registers 37, framing coordinate registers 39, frame shift registers 41, an indexing logic 43, a control logic of the test window 45, a comparison logic and result memory 47, a comparison control state machine

  49 and a state generation logic 51.

  Before indicating the particularities of the present invention, the manner in which the objects are represented will be briefly described below in order to better understand

  the manner in which the present invention is implemented.

  XY pairs of vertices represent video display coordinates. For a current type display, X varies between 0 and 1151 and Y varies between 0 and 899. Each X coordinate and Y coordinate is stored in a separate 32-bit register or in a set of two 16-bit registers. Although sixteen bits are more than sufficient to maintain the highest screen coordinate value (the value up to 65,535, or between -32,768 and +32,767), 32 bits of information because this is the type of data that is most commonly found in graphics software, and this provides a range of values large enough to handle most real objects, which can be on large scales. wider than that of

only video display.

  Quadrilateral objects are represented as combinations of four pairs of vertices (X0, Y0), (X1, Y1), (X2, Y2), and (X3, Y3). If the object is a point, then all four vertex pairs are identical, that is, three points are obtained by simple repetition. If the object is a segment, then two of the four pairs of vertices (or three of the four vertex pairs) are obtained by repetition. If the object is a triangle, one of the four vertex pairs is obtained by repeating another. If the object is a quadrilateral, then the four couples are different. These objects (ie the point, the segment, the triangle or the quadrilateral) are, in the most efficient way, defined by using the minimum number of different vertices necessary to completely define the object, that is, a vertex for a point, two vertices for a segment, three vertices for a triangle, four vertices for a quadrilateral, and two vertices for a rectangle (opposite angles). If an image block transfer operation is to be performed, the four X / Y registers are interpreted as follows (and loaded accordingly): - X0: X coordinate of the upper left corner of the source block; - YO: Y coordinate of the upper left corner of the source block; X: X coordinate of the lower right corner of the source block; Y1: Y coordinate of the lower right corner of the source block; X2: X coordinate of the upper left corner of the destination block; Y2: Y coordinate of the upper left corner of the destination block; X3: X coordinate of the lower right corner of the destination block; Y3: Y coordinate of the lower right corner of the destination block; The images to be displayed on a display such as a cathode ray tube are formed of distinct pixels which are kept in a random access memory called "frame buffer" in one or more planes (or bits), the number of planes being usually eight to a color system. The data stored in the frame buffer are addressed by a pair of X and Y coordinates, a pair (X, Y) identifying a given pixel in all the planes, X being the row and Y being the column.

  A pixel is defined by an isolated bit in each of the planes.

  Thus, if eight planes are used, each displayed pixel is defined by eight bits in the frame buffer. In this way, one bit of one pixel can be used to specify whether it is illuminated or off, the other seven bits specify the color of the pixel, or the eight pixels can be used to specify the color, one of the colors being the same as the background color of the display, so as to

turn off the pixel.

  The present invention resides mainly in the implementation of the indexing logic 43, the comparison logic and result memory 47 and the comparison control state machine 49, which coordinates the obtaining of the comparison information of the coordinates with each other and with the coordinates of the framing window. This is why the operation and implementation of the other functional blocks illustrated in FIG. 2 will only be described with regard to the details necessary for a

  good understanding of the present invention.

  Adder 31 and Multiplexer 35 The adder 31 is a 16-bit or 32-bit two-complement complement binary adder having two inputs, namely a "DataIn" referenced input receiving bus interfacing logic 11, the incident data in the form from the central processing unit, and another input connected to the output of the multiplexer 35 which selects, from among several inputs, one of the inputs from the frame shift registers 47, X / Y coordinate registers 37 or register of coordinate coordinates 39. The input of the multiplexer 35 is selected by signals produced by the state machine

  loading control 33 which will be described later.

  The details of the adder 31 and the multiplexer 35 will now be described with reference to FIG. 3. In FIG. 3, the adder 31 has been represented as a 16-bit adder. In this respect, although a 32-bit adder can be used because, in the preferred embodiment, the DataIn input is on

  32 bits, the description below will be given for a

  16-bit adder, which will save space on the integrated circuit where the present invention will be implemented, and because a two-step addition satisfies the sequencing constraints of the pipeline used by the present invention. The differences in use with respect to a 32-bit adder will be readily apparent to the specialist of this

  technical and therefore will not be described.

  The multiplexer 35 is, in fact, composed of two multiplexers 35a and 35b and a third multiplexer 36 used to input the sixteen bits of higher rank and lower rank from DataIn. The multiplexers 35a and 35b receive, respectively, the sixteen upper and lower rank bits from seven thirty-two bit inputs, as follows: a sixteen bit input value (sign range at thirty-two bits); two bits) from the frame shift registers 41, four thirty-two bit input values from the X / Y coordinate registers 37 and two sixteen bit input values (extended as a sign to thirty-two). bits) -from the frame coordinate registers 39. The outputs of the multiplexers 35a and 35b are combined to form the signal referenced "DataOut" (which will allow the CPU - processing to read access to these values of register), and are also inputted to a third multiplexer 40 which transmits the output value of the multiplexer 35a whenever the higher order bits from X0-X3 or Y0-Y3 are accessed; in the opposite case, the multiplexer 40 selects the output value of the multiplexer 35b. The output of the multiplexer 40 constitutes one of the inputs of the logic gate 42 which passes either the value of sixteen bits at the output of the multiplexer 40, or sixteen bits at zero. In this respect, the zeros are forced by the logic gate 42 each time the DataIn bits are transmitted by the multiplexer 32 for direct loading (absolute loading) into a register in the frame shift registers 47, the registers X / Y coordinates 37 or the coordinate coordinate registers 39. FIG. 3 also shows the logic circuits 44 and 46 which perform the following function: when the addition of the sixteen lower order bits takes place, the AND gate 44 has forced its output low, which causes the carryover of a "0" at the input of the adder 31. The output of this adder is saved in the latch 46. When adding the sixteen bits higher, the output of the flip-flop 46 is transferred, by control of an AND gate 44, to the transfer input of the adder 31.This configuration makes it possible to have the equivalent in two cycles of an addition sure

thirty-two bits in one cycle.

  The operation of the adder 31, the frame shift registers 41, the X / Y coordinate registers 37, the frame coordinate registers 39, the control circuit of the test window 45 and the comparison logic and result memory 47 is coordinated by the load control state machine 33 and the comparison logic state machine 49 which triggers the operation of the aforementioned functional blocks so as to allow the pipeline data transfer. Thus, although not all the control lines from the load control state machine 33 and the comparison logic state machine 49 have been shown, the details of this configuration will readily be apparent to the skilled artisan. of this technique

  according to the description of the control state machine of

  loading 33 and the logic state machine of

  comparison 49 that we will give below.

  X / Y coordinate registers 37 The X / Y coordinate registers 37 are constituted, as can be seen by referring to FIG. 4, of a set of sixteen bit registers which store the vertices (X0, Y0) at X3, Y3) of an object to graphically represent. One of the sixteen bit registers is used to store the top sixteen bits of each X coordinate, and another sixteen bit register is used to store the bottom sixteen bits of each X coordinate. Likewise, another register of sixteen bits retains the upper sixteen bits of each Y coordinate, and another sixteen bit register retains the sixteen lower bits of each Y coordinate. These registers have been illustrated in Figure 4, XOL (L for Lower, Lower) representing the sixteen lower bits of the XO and XOU coordinate (U for Upper, lower) representing the top sixteen bits of the X0 coordinate. The registers X1L to X3L and X1U to X3U represent, respectively, the sixteen upper and lower bits of the coordinates X1 to X3. Similar registers Y0L to Y3L and YOU to Y3U store the lower and upper sixteen bits of the Y0 to Y3 coordinates of the object. References XO, YO, etc. will indicate the 32-bit value stored in the register pair

  corresponding, that is to say (XOU, X0L) and (YOU, YOL).

  Each pair of registers (X0L, YOL) to (X3L, Y3L) is connected to a pair of multiplexers used to select either the X-register or the register. Y corresponding. For example, the XOL and YOL registers are connected to the multiplexers 61a and 61b. The load control state machine 33 produces a signal which instructs the multiplexer 61a to select the input from either the XOL register or the YOL register, depending on whether one has to work on the X coordinates or on the Y coordinates. Each of the multiplexers 62a, 62b to 64a, 64b operate, respectively, in the same way for the register pairs (XlL, YlL) to (X3L, Y3L). The outputs of the multiplexers 61a to 64a go to the multiplexer 35b, while the outputs of the multiplexers 61b to 64b go to the

  comparison logic and result memory 47.

  Blocks 67, 69, 71 and 73, referenced "all zero" or "all at one" are each constituted by logic circuits which examine the upper 18 bits of the pair of corresponding X, Y coordinates to determine whether they are entirely to zero or entirely to one. Sixteen bits are from the registers (XOU, YOU) to (X3U, Y3U), the seventeenth and eighteenth bits from the two higher order bits of the corresponding register of the group (XOL, YOL) to (X3L, Y3L ). The seventeenth and eighteenth input bits were not represented on the

  Figure 4 to avoid unnecessarily confusing the figure.

  The pairs of registers (X0U, YOU) to (X3U, Y3U) are respectively connected to the inputs of the multiplexers 75 to 78 which select either the X coordinate or the Y coordinate, in the same way as for the multiplexer pairs 61a, 61b to 64a, 64b. The outputs of the multiplexers 75 to 78 go to the multiplexer 35a. One of the four-bit outputs of each of the logic blocks 67 to 73 is, in each case, a "one" if the eighteen upper bits of the corresponding register are entirely zero or all one;

  otherwise, each of the four bits is zero.

  The four four-bit outputs of blocks 67 to 73 are

  applied as input to the state generation logic 51.

  The coordinate coordinate registers, illustrated in FIG. 5, comprise four registers, namely XClipMin, XClipMax, YClipMin and YClipMax, and multiplexers 81a, 81b, 83a and 83b. The values XClipMin, XClipMax, YClipMin and YClipMax, kept in the aforementioned registers of the same name, define, respectively, the left, right, top and bottom of the current active window. These values are produced by the central processing unit and are inputted to the adder 31 which adds a zero to these values to load the XClipMin, XClipMax, YClipMin and YClipMax registers, as described above. The multiplexers 81a and 83a, on the one hand, and the multiplexers 81b and 83b, on the other hand, select XClipMin and XClipMax, or YClipMin and YClipMax, as a function of the control signals produced, respectively, by the state machine. 33 and by the comparison control state machine 49. The values from the multiplexers 81a and 83a are sent to the multiplexer 35, while the values of the multiplexers 81b and 83b are sent to the comparison logic and result memory.

  47 and the test window control 45.

  Frame Shift Registers 41 The frame shift registers 41, which are illustrated in FIG. 6, comprise two registers XRas.Off (X Raster

  Offset) and YRasOff (Y Raster Offset), and a multiplexer 53.

  The values XRasOff and YRasOff that are stored in the aforementioned registers of the same name define, respectively, the X and Y offset to be added (if desired) to DataIn before storage in each of the four coordinate sets X, Y of the coordinate registers. X / Y 37. These values are generated by the central processing unit for storage in XRasOff and YRasOff. The multiplexer 53 selects either XRasOff or YRasOff based on the control signals generated by the load control state machine 33. The value selected by the

  multiplexer 53 is sent to the multiplexer 35.

  Control of the test window 45 With reference to FIG. 7, the test window control 45 will be described. The central processing unit produces the values TestXVal and TestYVal which serve to carry out an offset by a predetermined distance , that is, a predetermined number of pixels, up and down (for TestYVal) and to the right and to the left (for TestXVal) of the current active framing window. That is, for a given window of a display, we have an AX and an AY that define

  a test window surrounding the actual framing window.

  The purpose of this test window is to prevent, whenever it may be advantageous, the hardware to calculate the position of objects or parts of objects located outside the frame window. Details concerning the use of the test window are described in another application for

  patent, pending, on behalf of the Claimant.

  The four-bit TestXVal and TestYVal values are maintained in the four-bit TestX and TestY registers, respectively. The multiplexer 91 selects one of the registers TestX or TestY, depending on whether one has to operate on the X coordinates or the Y coordinates, as a function of the MUX Enable signal for activating the multiplexer produced by the control state machine. The output of the multiplexer 91 is input to the decrement register 93 and the incremental register 95. The decrement register 93 receives on its second input the value XClipMin or YClipMin and the incremental register receives on its second input the value XClipMax or YClipMax, again depending on the MUX Enable signal for activating the multiplexer. The output values produced by the decrement register 93 and the incremental register 95 will be designated XTestMin, YTestMin, and XTestMax, YTestMax, respectively. The decrement register 93 gives the values XTestMin and YTestMin by subtracting from XClipMin and YClipMin a value equal to 2

  raised to the power (TestX-1) and (TestY-1), respectively.

  In the same way, the incremental register 95 determines the values XTestMax and YTestMax by adding to XClipMax and YClipMax a value equal to 2 raised to the power (TestX-1) and (TestY-1), respectively (i.e. 2TestX-1 and 2TestY-1) Load control state machine 33 and indexing logic 43 Load control state machine 33 produces the control signals "MUX Enable", "Index" and "Register Enable" . "MUX Enable" is a set of control signals, one of which causes the various multiplexers to select frame shift registers 41, X / Y coordinate registers 37 and frame coordinate registers 39 from their respective axes. respective X or Y inputs, and another signal causes the multiplexer 35 to select one of the inputs from the frame shift registers 41, X / Y coordinate registers 37, or frame coordinate registers 39. "Index" is an isolated control signal that increments one unit of an index register in the indexing logic 43 for each of the values 0,

  1 and 2 and, if the value is 3, its resetting (modulo 4).

  "Register Enable" is a set of control signals, with a signal for each of the frame shift registers 41, X / Y coordinate registers 37 and X / Y coordinate registers 39, allowing each of these registers to load the value on sixteen bits present on

  the line coming from the adder 31.

  We will now describe, by way of example, the operation of the load control state machine 33 and the indexing logic 43, the details of implementation will emerge easily. As indicated above, the images to be graphically represented are defined as one or more objects having four pairs of vertices (X0, Y0) to (X3, Y3). The objects can be points, segments, triangles, rectangles or quadrilaterals. For points, the four pairs of vertices are identical. For some

  segments, we only have two pairs of different vertices.

  Any quadrilateral has four different vertices. A rectangle corresponds to a particular case of quadrilateral where one has only two different X coordinates and two different Y coordinates (the rectangles can be defined by a pair of vertices defining the diagonally opposite angles). For triangles, we only have three

couples of different peaks.

  The index value indicates which of the registers to activate according to the type of object to be defined. For correct operation, the Y values preceding the X values. With the exception of the rectangles, the index register is incremented after the X values have been loaded into the appropriate registers. For rectangles, the index register is incremented after the two X and Y values. In this respect, Table I below gives, for each type of object, the X registers that are activated for each register value. 'index. Although not shown, the activated Y registers correspond to the activated X registers.

TABLE I

  Type Value of the index when loading object 0 1 2 3 point X0, X1, X2, X3 X1, X2, X3, X0 X2, X3, X0, X1 X3, X0, X1, X2 XO segment, X1, X2 X1, X2, X3 X2, X3, X0 X3, X0, X1 quadril. X0 X1 X2 X3 rectangle X0, X1 X1, X2 X2, X3 X3, XO An important characteristic that can be seen in Table I is that the coordinate on which the index register is pointed is always written. The writing mode (point, segment, triangle, etc.), also indicates in how many registers (modulo 4) one will then have to write. For example, if the index is 2 at the moment when we receive the order of inscription of a segment according to X, we write in three registers, namely X2, (X2 + 1) modulo 4 and ( X2 + 2) modulo 4, ie X2, X3 and X0. A quadrilateral writing

according to Y will only affect Y2.

  Examples 1 to 3 below will explain the role of the index register when defining an object. Each line of the example indicates the intended write operation, the value of the index register used by the load control state machine to drive the loading of the coordinate registers, the values stored in the coordinate registers after the inscription, as well as

  the index value after completion- the registration cycle.

  The mnemonics of the write commands are PntX or PntY to indicate the operation of writing a point, LineX or LineY to indicate the writing operation of a segment, TriX and TriY to indicate the operation of writing a triangle, QuadX and QuadY to indicate the operation of writing a quadrilateral and RectX and RectY to indicate the operation

  writing a rectangle. The actual registration operation

  The identification identified by each registration order is in fact an operation over several clock cycles, as will be described later. However, for these examples, the duration

  execution of the order does not matter.

  To facilitate the interpretation of these examples, we will describe the first. The interpretation of Examples 2 and 3 is

  will easily deduce from this description.

  At the instant we receive the order PntY (6), all the coordinate registers contain the value "0" and the index is equal to "1". The order PntY (6) indicates that a point of value 6 must be loaded in the Y coordinate registers. As the index is a "1", Table I indicates that the input value (6) must be memorized in Y1, Y2, Y3 and Y0. The next order we receive, which is PntX (3) indicates that we must then load point 3

  in X1, X2, X3 and X0. As is the case after all

  inscription of indexed X coordinates, the index is incremented (modulo 4) at the end of the registration cycle. The next order of registration is LineY (9). For this loading, the index is worth 2, and the table I indicates that one will load 9 in Y2, Y3 and YO. The last order of registration is, in this example, LineX (7). Table I indicates that 7 will be loaded into X2, X3 and XO, after which the index register will be incremented again. The final state of the coordinate registers identifies two different vertices (three vertices at (7, 9) and a vertex at (3,6)). Geometrically, this corresponds to a segment whose extremities are in (7,9) and (3,6), as desired.

Example 1

  we want to specify a segment (3,6) (7,9) Index Index before order X0 Xl X2 X3 Y0 Y1 Y2 Y3 write write

- 0000 0 0 0 0 01 01-

  Esq. PntY (6) 0 0 0 0 6 6 6 6 01 01 Ecr. PntX (3) 3 3 3 3 6 6 6 6 01 02 Ecr. LineY (9) 3 3 3 3 9 6 9 9 02 02 Ecr. LineX (7) 7 3 7 7 9 6 9 9 02 03

Example 2

  we want to specify a triangle (1,5) (9,3) (4,6) Index Index before order X0 Xl X2 X3 Y0 Y1 Y2 Y3 write writing

- 7 3 7. 7 9 6 9 9 03 03

  Esq. TriY (5) 7 3 7 7 5 6 9 5 03 03 Ecr. TriX (l) 1 3 7 1 5 6 9 5 03 00 Ecr. TriY (3) 1 3 7 1 3 3 9 5 00 00 Ecr. TriX (9) 9 9 7 1 3 3 9 5 00 01 Ecr. TriY (6) 9 9 7 1 3 6 6 5 01 01 Ecr. TriX (4) 9 4 4 1 3 6 6 5 01 02

Example 3

  we want to specify a rectangle (0,7) (8,7) (8,1) (0,1) Index Index before order X0 Xl X2 X3 Y0 Y1 Y2 Y3 write writing

- 9 4 4 1 3 6 6 5 02 02

  Esq. RectY (1) 9 4 4 1 3 6 1 1 02 03 Ecr. RectX (0) 0 4 4 0 3 6 1 1 03 00 Ecr. RectY (7) 0 4 4 O 7 7 1 1 00 01 Ecr. RectX (8) 0 8 8 0 7 7 1 1 01 02 Although, in example 1, the index register is arbitrarily set to 1 when the first coordinate is received, the index register of the logic d The indexing 43 may be initialized according to a value placed on DataIn, if the order is so given by the central processing unit (it should be noted that the correct operation of the device of the present invention is totally independent of the initial value of the index register when a loading sequence is triggered). It is also assumed in this example that XRasOff and YRasOff contain the value 0, so as not to

  complicate the description of the operation of these circuits.

  The load control state machine 33, which cooperates with the comparison logic state machine 49, controls a pipeline process which, in addition to loading the various registers described above, also controls the selection of the necessary registers and multiplexers. the correct operation of the comparison logic and result memory 47 and the state generation logic 51. In addition, when it is desired not to use the frame shift option that the present invention allows, It is necessary, before performing comparisons by the comparison logic and result memory 47, to force the addition of zeros to the incident data for storage in the X and Y coordinate registers. In this respect, the control signals " MUX Enable "and" Register Enable "produced by the load control state machine 33 and the compare logic state machine 49 may be derived from the FIG. 9 and the list below showing the order of execution, by the staging section, of the coordinates 15 for each introduced Y coordinate: i0 1. DataIn reception on the Y coordinate. 2 Adding the lower 16 bits of the Y-string received a) to YRasOff (16 lower bits), or b) to the lower 16 bits of YOL to Y3L referenced by (index-1),

or c) zeros.

  3. Adding the top 16 bits of the Y-string received: a) to YRasOff (upper 16 bits extended in sign), or b) to the upper 16 bits of YOH to Y3H referenced by (index-1), or c) to zeros, and comparing the result of step (2) with

other coordinates.

  4. Comparison of the result of step (2) with YClipMin, YTestMin, YClipMax and YTestMax and examination of the upper 18 bits of the result of steps (2) and (3) for

  detect whether or not they are all '1' or '0'.

  In steps 2 and 3 above, the choices (a), (b) or (c) are made as follows: for non-relative entries in an indexed register (PNT, LINE, TRI, QUAD, RECT), we make the choice (a). For a relative inscription in an indexed register (RELPNT, RELLINE, RELTRI, RELQUAD, RELRECT), one makes the choice (b). For all other inscriptions, select the choice (c). The loading

  an X coordinate is the same.

  Keeping in mind the descriptions and definitions

  above, and assuming that the value of the index register of the indexing logic 43 is "01" and that the registers (XO, Y0) to (X3, Y3) described above with respect to FIG. are all entirely zero, the sequence of events that will now be described makes it possible to load the registers so as to define a segment whose ends have for coordinates X, Y (3,6) and (7,9),

as in the case of Example 1.

  At clock cycle n 0O, the write command PntY (6) sets the value "6" to DataIn, and causes the register address inputted to the load control state machine 33 contains a value indicating that the incident data is a point Y. At the clock cycle n1 (refer to FIG. 3), the multiplexer 36 receives the order to select the sixteen lower-order bits of DataIn and the multiplexers 35. (i.e., the multiplexers 35a and 35b) and 40, and the logic gate 42, are instructed to transmit the lower sixteen bits of YRasOff. Thus, during the clock cycle n 1, the adder 31 adds the output values of the multiplexer 36 and the logic gate 42 to each other and delivers the result on its output. At the end of the clock cycle n1, the registers Y0L to Y3L are activated and loaded by the value coming from the adder 31, that is to say the value 6, which represents the order bits

  lower than the value 6 that was on DataIn.

  At clock cycle n 2, multiplexer 36 receives the order to select the top sixteen bits of DataIn, and multiplexers 35 and 40, as well as logic gate 42, are instructed to transmit the upper sixteen bits. , extended in sign, of YRasOff. Thus, during the clock cycle n 2, the adder 31 adds between them the outputs of the multiplexer 36 and the logic gate 42 and delivers on its output the result. At the end of the clock cycle n 2, the registers YOH to Y3H are activated and loaded by the value coming from the output of

the adder 31.

  At clock cycle n 3, the PntX write command (3) sets the value 3 to DataIn, and causes the register address inputted to the load control state machine 33 to contain a value indicating that the incident data is a point X. Also at clock cycle n 3, the multiplexer 36 receives the order to select the sixteen lower rank bits of DataIn and the multiplexers 35 and 40, as well as the logic gate 42 , receive the command to transmit the lower sixteen bits of XRasOff. During the clock cycle n 3, the adder 31 adds between them the outputs of the multiplexer 36 and the logic gate 42 and delivers on its output the result. At the end of the clock cycle n 3, the registers X0L to X3L are activated and loaded by the value coming from the adder 31, that is to say the value 3 which represents the order bits

  lower than the value 3 that was on DataIn.

  At clock cycle 4, the multiplexer 36 receives the order to select the sixteen high order bits of DataIn and the multiplexers 35 and 40, as well as the logic gate 42, are instructed to pass the sixteen bits.

  superiors extended in sign of XRasOff.

  At the clock cycle n 4, the adder 31 adds between them the outputs of the multiplexers 36 and the logic gate 42 and delivers on its output the result. During the clock cycle n 4, the registers XOH to X3H are activated and loaded by the value coming from the output of

  the adder 31, and the index register is incremented.

  At clock cycle n05, the registration order LineY (9) sets the value 9 to DataIn, and causes the register address inputted to the load control state machine 33 to contain a value indicating that the input data is a Y segment. At clock cycle n 5, the multiplexer 36 receives the order to select the sixteen lower order bits on DataIn and the multiplexers 35 and 40, as well as the logic gate 42. , receive the command to transfer the lower sixteen bits of YRasOff. During the clock cycle n 5, the adder 31 adds between them the output values of the multiplexer 36 and the logic gate 42 and delivers on its output the result. At the end of the clock cycle n 5, the registers Y2L, Y3L and Y0L are activated and loaded by the value coming from the adder 31, that is to say 9, which represents the lower order bits of the value 9 that was on DataIn. At clock cycle 6, the multiplexer 36 receives the order to select the sixteen top-rank bits of DataIn and the multiplexers 35 and 40, as well as the logic gate 42, receive the order to transmit the upper sixteen bits, extended in sign, of YRasOff. At the clock cycle n 6, the adder 31 adds between them the outputs of the multiplexer 36 and the logic gate 42 and delivers the result on its output. During the clock-n cycle 6, the registers Y2H, Y3H and Y0H are activated and loaded by the

  value from the output of the adder 31.

  At clock cycle n: 7, the LineX (7) registration command places the value 7 on DataIn, and causes the register address inputted to the load control state machine 33 to contain a value indicating that the input data is a segment X. Similarly, the registers X2L, Y3L and Y0L are ultimately activated to load the value 7, after which the index register of 2 to 3 of the way

exposed above.

  Loading X / Y coordinate registers for other objects follows the same pipeline process as the one just described. For triangles and rectangles, examples are given in Examples 2 and 3 above. Objects are also loaded in the same way

constituted by quadrilaterals.

  Frame shift registers 41 and frame coordinate registers 39 are loaded in a manner similar to that described above for X / Y coordinate registers 37; however, the logic gate 42 receives for each addition cycle a forcing order at zero

  (that is, we have an absolute load).

  The present invention, by using the index register of the indexing logic 43, also executes a relative addressing which makes it possible to have a procedure

  effective for displaying duplicate objects.

  Relative addressing will be best described by means of

the following example.

  The three vertices of a triangle can be defined by (XO, Y0), (Xl, Y1) and (X2, Y2). To duplicate this object 50 times in different places of the display, it would be necessary to store 150 pairs of X, Y coordinates. By using relative addressing, a vertex is defined as an origin (XO, YO), and the second and third vertex are defined as offsets from the previous vertex, i.e., in the form of (AX01, AYO1) and (AX23, AY23). To duplicate the object 50 times, it will be necessary to memorize only the two pairs of offsets and a new value (X0, YO) for each duplicate (which will correspond, in total, to fifty object origins plus

two offset pairs).

  This can be achieved, with the present invention, by first storing the vertex of the original coordinate pair in one of the pairs of registers of the X / Y coordinate registers 37 by using an indexed loading instruction (by example PntY, PntX). The two offset vertices are then stored relative to the vertices on which the current value of the index register points. This is done by selecting the vertex on which it is pointing (index-1) and adding it to DataIn before loading the register. We will be sure that the vertex referenced by (index-1) will have been loaded on the previously indexed registration regardless of the type of inscription (PNT, LINE, etc.), and therefore it will be the top relative to

  to which the relative offset applies.

  Comparison logic and result storage logic 47 The comparison logic and result storage logic 47 will now be described with reference to FIGS. 7 and 8. The comparison logic and logic of szneITA xnap saT azZua uosT = 22dmoO aun, p • • • • • ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• xe, 4seAX / UTwqSlX 'XTNdTiOX / uTNdTTO.X' xeWdTTDOX / uTWdTTDX uu; Duoo SZ suosT'eeduoo sap uoT; deDxaT 1 'II nelTaTe aT sunC úX:' ZA gx X- úX: ZXZZ EX: x ú úX: TIX ITZ Zx: lx gtP ZX: IX Ozu Where úX: ox IPU úX: OX 6TU zX: oX o0 ZX: 'OX 8Te TX: 0X 6EU IX: ox LIU xweNsaLI: ex 8uE xewsalX: úX 9IH xNdTITOX: X LEU xedTTIDX: úX I 'SZ uTNdTIDX: ÜX UTWdTiOX: úX EÜT Xe4salx: ExPéE XNqsaix: Ex giu xeNldTTD ,: ZúE xewdTTOX: ZX TII uTsoaI: z ZEU uTr; salx: gx 0IE OZ uTdtIDA: ZZ EU uTdTTIDX: ZX 6U xesaX: ITx 0OU xvqsajX: TX 8U xedTTIDX: IX6ZE xeNdTIDX: IX LU uTKsqaLX: I 8ZE uT sIX: IX 9U uTdtIDX: TXLZt uTdTTIDX: IX Su Sl xewsaix: 0X 9ZU xexsalx: ox fe xeWdTID: OX ZE xeWdTTIDX: OX úe uTNsaX: -0oxPZE uTWsZax: 0Ox Z uTWdIDTT: 0 úZE UTdTIOdX: OX read snossap-To II neplqe; eI suep flnbTPUT e2a-ueUI tl aP bZI e IZI sanaeedwoD sGT ed seaanDe ;; suoTIeZGdo sap breastsgz sal 'u9ss: YES TO HIS ILLQSTB7a sa ú * nbT IT A) OA U? Ta SGIISTbeZ sep la 9bl 1ú1 san @ xa [of no sap 'BEE IZI s.in 2duioD sGp the (LGnBTg ZTOA) 601 the L0oI '01' ú0I '10I sznaXaTdTInuI sap eanqTqsuoo qsa LP TelnsaI ap uoTq2STZou1UI 6Z indicated. If the value to the left of ":" is greater than the value to the right of ":", the binary value stored in the corresponding register will be "10"; if the value to the left of "-:" is less than the value to the right of ":", the binary value stored in the corresponding register will be "01"; if the two values are equal, the binary value stored in the corresponding register will be "00". For XClipMin, YClipMin, XTestMin and YTestMin, if the value of the compared coordinate is lower, a "1" is memorized, and in the contrary case a "0" is memorized. For XClipMax and YClipMax, XTestMax and YTestMax, if the compared value is higher, we memorize a "1", and in the contrary case we

memorize a "0".

  The input values to the multiplexers 101, 103, 105, 107 and 109 are derived from the X / Y coordinate registers 37, namely XOL, YOL to X3L, Y3L, framing coordinate registers 39, namely XClipMin, YClipMin and XClipMax, YClipMax, and test window control 45, namely XTestMin, YTestMin, XTestMax and YTestMax. Of course, at any given instant, the values applied to the inputs of the multiplexers 101, 103, 105, 107 and 109 are either X values or Y values, as explained above, as a function of a "MUX Enable" signal. by the comparison control state machine

49.

  The comparator 121 compares the output of the multiplexer 101 and that of the multiplexer 109. In the same way, the comparators 122 to 124 compare the outputs of the multiplexers 103, 105 and 107, on the one hand, and those of the multiplexer 109, on the other hand. somewhere else. The outputs of the comparators 121 to 124 are input to the multiplexers 131 to 146, which direct the appropriate data to the registers Ri to R44, which will be loaded in the manner that one is going to.

now indicate.

  The output of the comparator 121 is connected to the multiplexers 131 to 135, 139 and 143, which are used to load the registers Ri, R2, R3, R4, R5, R9, R13, R17, R18 and R19 by X values, and the registers R23, R24, R25, R25, R26,

264286Y

  R27, R31, R35, R39, R40 and R41 by Y values, as illustrated in Figure 8 and in Table III below. In Table III, A, B, C and D refer to comparators 121,

122, 123, and 124, respectively.

  The output of the comparator 122 is connected to the multiplexer 132, 135, 136, 137, 138, 140, and 144 which are used to load the R2, R5, R6, R7, R8, R10, R14, R17, R20 and R21 registers for the values X and the registers R24, R27, R28, R29, R30, R32, R36, R39, R42 and R43 for the values Y,

  as shown in Figure 8 and Table III.

  The output of the comparator 12-3 is connected to the multiplexers 133, 137, 139, 140, 142 and 145, which are used to load the registers R3, R7, R9, R10, R12, R15, R18, R20, and R22 by values X and the registers R25, R29, R31, R32, R34, R37, R40, R42 and R44 by Y values, as

  illustrated in Figure 8 and Table III.

  The output of the comparator 124 is connected to the multiplexers 134, 138, 142, 143, 144, 145, and 146, which are used to load the registers R4, R8, R12, R13, R14, R15, R16, R19, R21 and R22. by X values and the registers R26, R30, R34, R35, R36, R37, R38, R41, R43 and R44 by Y values, as

  illustrated in Figure 8 and Table III.

  The comparisons made and stored are those required by the coordinate sequencing block 17 and the functional addressing block 19 to correctly execute the possible operations (rendering of a quadrilateral or image block transfer) and performing the

appropriate framing.

  Comparative control state machine 49 The comparison control state machine 49 is a logic that activates the various comparators, multiplexers, and registers of the comparison logic and result memory 47. Table III below gives a table of truth for the absolute loading of the coordinate and framing registers by the comparison control state machine 49 for the clock cycles n 0 0 and n 1, the comparators 121 to 124 being referenced respectively A, B, C and D. The Table III gives the output of each comparator 121 to 124 for each of the XOL inputs X3L, XClipMin, XClipMax, XTestMin and XTestMax. In this regard, it will be noted that FIG. 8 shows that the outputs of the multiplexers 101, 103, 105, and 107 are input to one side of the comparators 121 to 124, while the output of the comparator 109 is applied to the input of the other side. For homogeneity, it is necessary to memorize comparisons of XOL with XlL, XlL with X2L and X2L with

  X3L, etc. and not the other way around (for example, X1L with XOL).

  For this reason, when the column referenced "inversion" contains a "yes", the outputs of the comparators 121 to 124 are reversed. This is managed by the right input of the multiplexers 131 to 146. The output of the comparators 121 to 124 indicated is directly applied to the input of the left side of the multiplexers 131 to 146. The right input of the multiplexer receives, in the inverse order of the bits, the

  value on two bits at the output of the indicated comparator.

  Thus, the column designated "inversion" becomes the truth table for the multiplexer selection lines of the multiplexers 131 to 146, for a loading in absolute coordinates.

TABLE III

  Comparator Comparison 'Inversion N cycle Inscription in XO B XOL: X1L yes OC XOL: X2L yes OD XOL: X3L yes OA XOL: XClipMin yes 1 B XOL: XTestMin yes 1 C XOL: XClipMax yes 1 D XOL: XTestMax yes 1 I or EX: uTw4SeLX to I uou qIX: UTNqsaLX to 0 uou UEX: UTNdTTOX O uou TlX: UTWdtTOX to 0 uou 7IX: UTWdT DX X 0 uou l0X: UTdTiToX V uTNTITTOX sup uoTqdTZDsuI o I i Fno xefNsaix: úx a t -Fnoa TriFno xeNdTIOX : LX 0 I Tno u- $ sex: q ux ai TFno uTdTIDX: ILX V sz o u or zX: IEX 0 o u or IIX: IUX 0 uou IoX: IUX úX suVp UoTqdToSui I Fno x2dIsoX: ZX to I uFnoTex ^ dx: qzx DI Fno UT qaI @ X: qZX ZI Fno UT dTIDX: ZX V 0 Tfno lxX: ZX to 0 or IIX: ZX 0 uo or loX: ZX ZX suep UOTqdTZDSuI I Fno xedNsaX: lIx to I Fno xexdTiOX: UlX 0 I Tno UTIsaIX: IlX s I Tno uTNdTTIDX: IX V 0 Fno lX: qiX to O fno IZX: IX DS 0 uou qoX: IIX IX suep uoTqdT2DsuI UOTSA oNAUI uosTeuIUOS eduioD ana na-duioD 198tZ9úú

Z98393

  Comparator Comparison Inversion N cycle XClipMax registration XClipMax: XOL no OB XClipMax: XlL no 0 C XClipMax: X2L no OD XClipMax: X3L no 0 A XTestMax: X0L no 1 B XTestMax: XlL no 1 C XTestMax: X2L no 1 D XTestMax The results in Table III are repeated in the same way for YOL at Y3L, YClipMin, YClipMax, YTestMin and YTestMax. Figure 9 shows the relative sequencing of the signals on DataIn and the register loadings performed on the frame shift registers 41, the X / Y coordinate registers 37, the frame coordinate registers

  39 and the comparison logic and result memory 47.

  The comparison control state machine enables indexed loading as described above, using both the index register value associated with a write cycle and the given table IV below. Since the register on which the index register value is pointing is always inscribed independently of the indexed registration type, the appropriate "MUX Enable" control signals of the multiplexers 101, 103, 105 and 107 are selected by the state machine. comparison command assuming that there is only one register record for this coordinate. For example, if we receive an inscription of an X rectangle with an index of 3, the comparison logic will operate as if we had received an explicit order of X3 registration, and will perform, as as needed, comparisons of X3L with respect to (XOL, X1L, X2L, XClipMin, XClipMax, XTestMin, XTestMax). The difference between an absolute loading of a register and an indexed (or indexed) loading is that, in the case of an indexed loading, one can have I Tno SNII úX: ZX to I Tno NI. X: IX to I Tno ENII ZX: IX OI uou 3NIr EX: OX v SI or NII lX: Ox VI or NII IX: 0X VO Fn NIa úX: ZX to 0 Fno SNII eX: IX to Where 0 Fno SNII ZX: IX D 0 mno SNII eX: 0X a O TflO HNII ZX: OX Q 0 Trno xNIUEX: ox OO Fno SNII-IX: OX s SZ Tno LNa úX: ZX a - Tri-Fo INCI EX: X lxc Tno LNd EX: IX at T $ loNa úX: OX a -no JNc ZX: OX 3 oz -Fno iNa IXTXOX xapuI uoTsXAuS dUosTwdwoD naGdwoo wiTh wiTiNg uosUZdwoo ap slanpTATpuT- slelnsTlS suiui sal quolaesT-ouaW (9lu> eu) qe (Slu 'ú1U)' (> 1EU 'Z-) J (ÜEU' -EU) (ZZg u8Il) '(IZE' L / l) sazzsTbaz ap sa-dnoD its' TZU 01 61U F úl '9gH e ClU' úH F? IH (8 sn6T; no II nualq2q ztoA) uosTVwdUIoD ap sG $ STB6aa saT qTDSuT uo 'apapaTe a DoAe X atBu9eoZ a, p uoTqdTJDsuT, T ap 9TDo9d aldUIGX, lon-e * III neelqe only quauiauaouuoz uO3,1 ap naTI do not know that this is the case for 4-year-olds, that is, that it is not possible to use the following methods: Toooe anod s9ATIoe, 4uAno2-eS Tnb seauuopzooo ap uoTqesT = oUam 3p s9ZZsTbal sanassnld Lú ua quauleTanquaAa z 9 8.gg 9E 1 9 8.z 9 Z Tnro AOSU / IUl úX: ZX az uou loú / There úX: IX sz uou IOD / IWT ZX: TX S z uor Zos / IU úX: OX V z ooo loT / Iul ZX: OX V Where I -TFno L0S / IL úX: ZX to I -Fno IDSU / IUZ EX: tIX to I Fno ZD: R / I) IL ZX: IX :) I or aD / IMiZX: OX SZ I uou log / Iul IX: oX VT -FoU Isiu x: lx V o Fn Ds / IEu X: 0 X a ci 0 TFno 10S / Iii ZX: OX D 0 Fno ZS / IMi IX: ox a ú ou x: o o o o o o IX IX IX::::::::::::::::::::::::::::::::::::::::::::::::::::::::: or EXIX: -IX 9 zu or sNII ZX: IX Z -Fno ENII úX: OX to Z - jno SNII ZX: OX SZ Fno ENII IX: ox xapul uoTs1auI GdX uosTGId'oD znaqwed: oo 9e qsa quewenbTqdd aaq.B m; e g e q qo, Ts quenbTpuT! sqTq xnap ns TvuBfs a qsa (-TqTsTA / uappTH) SIA / CIIH '4sTOP eI szeA aqoneB and ap no aqoneb PT szea aqTOp and ap' Jneq eI s = a se seq np 'seq aI smaA nelq np aelnopxa a $ 9 -TFoP uo -FqDado, t

* * * * * * * * * * * * * * * * * * * * * * * * * * *!

  TZBE / dfl) 'I-oq-u / dn * TeIDFBoT med no' uoT-4ueatu aquesaad ee ZuaulawuzoguoD 'tieT2vux ad aanqog ;; gees uoTqzGdo, T Fs quenbTpuF sq-q xnapans reu6Fs a 4se (e-rm: os Where /eP.mph) MS / MH.SIA / GIH q'I-Oq-E / dfl 'MS / MH apu'euuooD ap xnreu.frs sGT q.npozd Tg sqevqp uoqaemuea ap enbIboi ev r s9W, 1p uorqeT u, 9a ap enblT5o7 c uou (Ivigo XEX ú uou CQnO EX: IX D ú uou or avnO úX: OX Z -Fn avno úX: ox a oz z uou aïIg zX: IX E z uou cvnc zx: Ox a Ino oFng úv X: IX a ú TnoE X: IX D Sl I or CY0 IX: OX v 0 Trio GfgO eX: 0X c 0 Tno úIOúX: OX a ú Tno ADEZ / IHL.EX: OX D ú Tno IDSI / IMi IX: OX l xapu UOS UI uoTsTaUI Od C uosTqdmoDnQaedulDoo The active frame, or if it is visible To produce these signals, the state generation logic 51 receives as input the contents of the registers R1 to R22, for the coordinate registers X, and R23 to 44 , for the Y coordinates, and the four four-bit signals indicating that the eighteen upper positions from the

  X / Y coordinates 37 are all fully "1" or "0".

  Reference will now be made to FIGS. 10 to 14 which are truth tables of the logic operations performed by the state generation logic 51, the manner in which the state generation logic produces these control signals; The logic circuits necessary to implement the truth tables of FIGS. 10 to 14 are quite within the reach of the specialist of this

technical.

  Figure 10 is a truth table using the

  comparison results for the X0 coordinate (X0L and XOH).

  The truth tables using the comparison results for X1 to X3 and Y0 to Y3 substitute these coordinates for X0 and, for Y coordinates, use YClipMin, YClipMax, YTestMin, and YTestMax instead of XClipMin, XClipMax, XTestMin, and XTestMax . The left part of the table is constituted by the entries, and the part

  right by the exits. In the table, the symbol "-"

  means "indifferent", O and! O mean that the binary values on the bus are all 1 or, respectively, not all of them at 1 (according to X / Y coordinate registers 37), and Z and! Z mean that the binary values on the bus are all 0 or, respectively, not all 0 (based on X / Y coordinate registers 37). "X0 inside 214" t means that the X0 coordinate on 32 bits can be represented on 15 bits, "X0 inside clip" means that X0 is at the limit of the framing window or inside this window and "X0 inside test "means that X0 is at the limit of the test window or within this window. The output values "X0 <XClipMin", "X0 <XTestMin", "X0> XClipMax" and "X0> XTestMax" are looped back and constitute new input values. To obtain the output values, a logical AND is performed on the input values of a horizontal line, and a logical OR on the output values of a column. Thus, if one refers for example to the first two lines of Figure 10, if XO [31] (that is, its sign bit) is 0 AND if XO [30:14] (c that is, the upper bits 14 to 30) is entirely zero, OR if XO [31] is 1 AND if XO [30:14] is all 1, then XO is within the limits of 214 (" X0 inside 21411 is TRUE.) Similarly, referring to the last line of Figure 10, if X0 <XTestMin is 0 (that is, FALSE) AND X0> XTestMax is 0, then X0 is inside the

  test window ("XO inside test" is TRUE).

  Figures 11a and 11b constitute a truth table using comparisons between each of the four vertices X and each of the four. vertices Y. As in the case of FIG. 10, a logical AND is performed on all the values of a horizontal input line, the result being a logical 1 (TRUE) or a logical O (FALSE), and the outputs indicated (except for "top", "bot", "right" and "left") are obtained by performing a logical OR on the corresponding column. The outputs "top", "bot", "right" and "left", which correspond to the values 0, 1, 2 or 3, are interpreted in the following way: the value 0, 1, 2 or 3

  specifies those of the coordinates XO to X3 or Y0 to Y3 which is -

  the highest ("top"), the lowest ("bot", for bottom), the rightmost ("right") and the most left (I "left" l). The "<", ">", "E", "L" and "G" symbols on the input side indicate that the specified comparison result is, respectively, "less than", "greater than", "equal to" , "less than or equal to" (L for Less), or "greater than or equal to

to "(G for Greater).

  We will now explain the meaning of the output values given by the table: "illegal" means that, if we draw a horizontal line crossing the object defined by the four pairs of vertices, it could cut more than two sides. A bow tie object is an example of an object for which "illegal" would take the value "TRUE"; "horiz" means that the four vertices all have the same Y value; "green" means that the four vertices all have the same value X; "rect" means that the object defined by the four coordinates constitutes a rectangle; "line" means that the object defined by the four coordinates constitutes a segment; "EQ_01" means that vertex 0 is identical to vertex 1 (it defines the same point); "EQ_12" means that vertex 1 is identical to vertex 2 (it defines the same point); "EQ_23" means that - vertex 1 is identical to vertex 3 (it defines the same point); and "EQ_30" means that 'vertex 3 is identical to

  vertex 0 (it defines the same point).

  Figures 12a to 12d define a truth table using comparisons between the four X vertices and the four Y vertices and the framing boundaries. The entries "top", "bottom", "right" and "left" come from the truth table of figures 11a and 11b. When the "top visible", "bottom visible", "right visible" and "left visible" outputs are at 1 (that is, are at TRUE value), the object defined by the four pairs of coordinates is inside the frame window.When "surround clip" (surround the framing) is 1, the object is

  finds out of the frame window but surrounds it.

  "hidden" is only applicable to quadrilaterals and indicates that the vertices are all four on the right, on the left,

  above or below the frame window.

  "hidden_01" (which concerns the source rectangle for an image block transfer) and "hidden_23" (which concerns the destination rectangle for an image block transfer) have

2642'867

  a similar meaning, for image block transfers. Figure 13 defines a truth table using comparisons between the four X vertices and the four Y vertices and the limits of the test window. The "top within test" and "bottoms within test" outputs, when they are TRUE, mean that the edge of the object is within the limits of the test. inside the upper and lower limits,

  - respectively, of the test window.

  Figure 14 defines a truth table showing the direction in which objects are to be traced or to execute image block transfers or BLICs (BLock Image Transfers) in order to minimize page changes and the processing of framed pixels by producing the signals "blit r-to-l" (BLIT from right to left), "blit up" (BLIT upwards), "draw r-to-l" (drawing from right to left) and "draw up" (tracing upwards). These signals constitute the "tracing direction" signal shown in FIG. 2. Further details concerning this aspect of the invention may be found in a patent application.

  currently being issued on behalf of the Claimant.

  According to the truth tables of FIGS. 10 to 14, the state generation logic 51 produces in the following manner the signals HW, SW, HID and VIS shown in FIG. 2: For objects constituted by quadrilaterals: HW = " hidden "OR" surround clip "OR (NOT" hidden "AND NOT" illegal "AND all vertices below 214 AND (all vertices in the test window OR (" line "AND at least one end in the window test) OR (X0 to X3 in the test window AND top or bottom vertex in the test window) OR

"rect t").

SW = NO "HW".

HID = "hidden".

VIS = NO "hidden".

  For image block transfers HW = "hid 23" OR ("hid_01" AND "BLITSRC_CHK" = 10) OR (NOT "hid 01" AND

"BLITSRCCHK" = 10 AND

  NO "hid_23" AND the source rectangle is below 214 AND the destination rectangle is below 24 OR

("BLITSRC_CHK" = 01 AND

  NO "hid_23" AND the source rectangle is below 214 ET

  the destination rectangle is below 214).

  "BLITSRCCHK" (BLIT SouCe CHecK: control of the source of the BLIT) being a two-bit value, given by the central processing unit, which is at "10" when one wishes to consider the report

  between the source rectangle and the frame window.

  This is necessitated by the fact that the various graphics programs that can be used by the present invention do not homogeneously process the source rectangle and framing boundaries. For this reason, in the preferred embodiment the checking of the source rectangle framing for image block transfers is a software selectable option (BLITSRC_CHK = 01 disables source framing verification and BLIT_SRC_CHK = 10 enables framing verification source).

SW = NO "HW".

HID = "hid 23".

VIS = NO "hid 23".

  In the preferred embodiment of the present invention, a step of loading the coordinates on two clock cycles has been used, followed by a step of

  comparison also operating on two clock cycles.

  Although these two steps may, as indicated, overlap, the overall latency is three clock cycles, with the new input data being received (or the new results available) one out of two clock cycles (ie, one elementary rate of two clock cycles.) In the examples, coordinate alignment logic has also been shown which receives data at the highest speed possible for This specialist will note however that the circuits described can handle a slower rate of data arrival (less frequent data) It will also be obvious that, at the cost of additional logic, it would be possible to have a lower overall latency and higher throughput

  simple extension of the circuits of the present invention.

Claims (7)

  1. A device for making comparisons between pairs of coordinates of an object to be displayed by means of a graphic subsystem, this object being either a quadrilateral to be plotted or an image block to be displaced, this device comprising a framing window with predetermined top, bottom, right and left framing coordinates and a test window with predetermined X and Y offsets with respect to said top and bottom, and with respect to said right and left , the coordinates of the object, the framing coordinates and the offsets used for calculations intended to perform the framing of the object before it is displayed, characterized in that it comprises: a) loading means, for loading: (i) a plurality of object coordinate registers (37) by said object coordinates (XO, Y0 to X3, Y3)   (ii) a plurality of framing coordinate registers (39) by said framing coordinates (XClipMin, XClipMax, YClipMin, YClipMax), and (iii) a plurality of shift registers (41) by said predetermined shifts (XRasOff, YRasOff b) comparator means connected to the loading means for performing said comparisons; c) calculating means connected to the shift registers and the coordinate coordinate registers for calculating the limits of the test window relative to at the boundaries of the registration window; d) multiplexer means for selecting some of said comparisons; e) register means (R1-R44) for storing such comparisons as are selected; and f) control means comparison (49) for controlling the operation of the comparator means,   multiplexer means and register means.   2. The apparatus of claim 1 wherein said Loading means include: -   a) load control means (33) connected to an indexing register (43), b) input means connected to the load control means, object coordinate registers and framing coordinates, receiving from a source external to the apparatus the coordinates of the object and the framing coordinates and storing these received coordinates in the object coordinate registers (37) and in the framing coordinate registers ( 39) under the control of the loading control means and the indexing register. The apparatus of claim 1, wherein the comparing means comprises: a) a first set of multiplexers (101, 103, 105, 107) for selecting between object coordinates, framing coordinates and alignment coordinates adjusted by said offsets, b) a multiplexer (109) for selecting between the registration coordinates and the registration coordinates adjusted by the offsets, c) a plurality of comparators (121, 122, 123, 124), connected to said first set of multiplexers and said multiplexer; d) a second set of multiplexers (131 to 146) each connected to at least one of the comparators or register means.   4. The apparatus of claim 1, wherein the calculating means comprise an incrementing register (95) connected to the shift register (41) and the framing coordinate register (39), said incremental register delivering a value greater than said high-frame coordinate (YClipMax) and said right-angle coordinate (XClipMax) as a function, respectively, of the Y offset (YRasOff) and the X-shift (XRasOff), and a decrement register (93) connected to the shift register (41) and the registration coordinate register (39), said decrement register outputting a value lower than said lower registration coordinate (YClipMin) and said left registration coordinate (XClipMin), according to, respectively, the offset Y (YRasOff) and the offset X (XRasOff). i0 The apparatus of claim 1, wherein the multiplexer means comprises a multiplexer:   selects one of eight entries.   The apparatus of claim 3, wherein the register means comprises a plurality of registers (R1 to R44) each connected to one of the multiplexers of the second set of multiplexers (131 to 146), each of which registers memorizing the result of a   predetermined comparison of said comparisons.   The apparatus of claim 3, wherein the comparison control means (49) comprises means for generating control signals for controlling the operation of said first and second sets of multiplexers (101, 103, 105, 107; 131 to 146) and said multiplexer (109), said plurality of comparators (121, 122, 123, 124) and a plurality of registers   comprising said register means (R1 to R44).