FR2640792A1 - CIRCUIT FOR DETERMINING SCANNING LINE POSITIONS FOR DISPLAY AND HANDLING BY AN INFOGRAPHIC SYSTEM - Google Patents

Abstract

This circuit makes it possible to determine the X values of each end of a series of horizontal scan lines connecting a pair of straight line segments each of which is defined by a pair of vertices, the horizontal scan lines defining an area to be restored on a peripheral computer output. It comprises, according to the invention: a first 32 and a second 34 circuit block, each of these circuit blocks comprising means for determining the slope of a line segment and means for determining, as a function of the slope , the start and end X values for each straight line segment of each scan line of the area to be restored, - means for starting to operate the two circuit blocks on the same scan line, and - means to transform the Y value of each circuit block to the Y value of the next adjacent scan line at the same time.

Description

The present invention relates to computer systems

  and more particularly the circuits for determining the position of the different points of a scan line to be displayed on a display at the output of a computer system. One of the major problems when using computers to produce graphic displays is that for a single frame of graphic material to

  restitution on a cathode ray tube, it is usually necessary

  to memorize an indication of the information to be displayed

  expensive in each position (at each pixel) of the cathode ray tube.

  With large and very detailed displays, the number of pixels on the CRT can be around a thousand or more in the horizontal direction and a comparable number in the vertical direction, giving a total of about one million pixels or more for which one must memorize information. In preferred systems, a number of different colors can be produced on the cathode ray tube, each of the pixels having eight bits of digital information specifying the particular color to be outputted. As a result, approximately eight million bits of information must be stored for each

frame to represent in output.

  Not only must the color information be given for each pixel of each frame of the display, but also, when producing graphic displays, the usual method for determining the shapes of the figures requires the application of various algorithms to data to conform these figures. If this information is managed by the system software, the calculation of the positions of each point to be displayed and the determination of the

  data to display at this point slow down the function

  of the system to such an extent that functions such as animation are practically impossible to achieve. For example, if one wants to restore on the output display a polygon, it is necessary to determine each end of each horizontal line constituting the polygon, since the information is delivered to the display line display line of display. In the systems of the prior art, this determination of the ends of each line to be scanned

  on the output display required a logical execution.

  by the central processing unit for calculating the end values of each scan line of each graphical form to be rendered. Such configurations

  increase the time needed to reproduce the

  to such an extent that it results in a slowdown

notable of the display.

  For this reason, it has been proposed various systems using hardware to accelerate these operations. One of the methods for speeding up the operation uses two frame buffers, one of which is loaded while the other is scanned for display. Such a system significantly increases the speed of operation but requires practically twice as much memory for

the storage of data.

  It is for this reason that one of the aims of the present invention is, in this respect, to accelerate the operation of the systems

computer.

  Another object of the present invention is to propose circuits making it possible to manage by material manipulation of graphical material which, in the usual case, would have been

  managed by the computer system software.

  Another object of the present invention is to

  propose circuits for determining the coordination

  X and Y data of the ends of the lines to be scanned on the

output file.

  These and other objects of the present invention are achieved through a new output display system which employs an original concept of representing graphical figures to obtain high speed

  graphs, while using only one display buffer.

exit.

  In order to be able to realize by hardware the restitution of the graphs, it has been found that the information presented to the material will be processed more quickly if it is essentially of the same nature, whatever the form that must be plotted on the display. The system is based on a definition of a graphic figure (a form) according to which one considers that the form is composed of a certain

  number of subsets that are each quadrilaterals.

  Circuits are provided for rapidly displaying images formed of quadrilaterals, managing only the information relating to the four vertices of these quadrilaterals. These quadrilaterals can all be managed in the same way by

  graphical restitution material and recombined on the

  file in order to restore the desired shape.

  The system splits the quadrilaterals into subsets consisting of pairs of line segments that subtend a trapezoidal surface to be rendered on the output display. The X and Y coordinates of the two ends of each scan line of each trapezoid are then determined. The subject of the present invention is circuits which at the same time determine the one and the other end of each scanning line situated inside a FIG.

  quadrilateral to display as output.

  The system and circuits of the present invention are designed to select the optimal decomposition of a shape so that the operation can be performed on the

  as quickly as possible. For example, if a decomposing form

  lay only partially within a

  frame window and partially below or well below

  above the framing window, the operation will be executed more quickly if the portion outside the framing window does not need to be processed. This can be achieved if the decomposition can run from top to bottom or from bottom to top. In addition, the RAM used in computer systems is generally divided into

  partitions called "pages", and memory accesses to the

  on the same page take less time than if you have to go from a first address in a first page to a second address in another page (that is to say if you have to cross a border of page). If the operation is going up from the bottom, we will have to traverse fewer page boundaries if the processing of a given scan line runs from right to left, rather than from left to right like this is usually the case. Crossing fewer page boundaries allows

  also faster operation.

  The decomposition and treatment of scan lines enabled by the system of the present invention and its implementation take place from left to right or from right to left, and from top to bottom or from bottom to top . The circuits are also able to determine the starting point and end point of each scan line even if the figure is formed of line segments intersecting with each other. The aptitude of circuits

  of the present invention to deliver the rectangular coordinates

  gulars allows fast transfers of

  to an output display.

  For this purpose, the invention proposes a circuit for determining

  undermine the X values of each end of a series of horizontal lines connecting a pair of line segments each of which is defined by a pair of vertices, the area defined by the horizontal lines to be presented

  on an exit display of a computer system, which is

  characterized in that it comprises: means for determining the variation of the X value between the vertices of a first line segment; means for determining the variation of the X value between the vertices of a second line segment; means for determining the variation of the Y value between the vertices of the first line segment; means for determining the variation of the Y value between the vertices of the second line segment; means for determining whether the slope of the first line segment is greater than unity; means for determining whether the slope of the second line segment is greater than unity; means for establishing, for the first line segment, an error value equal to the greatest of the variations of X and Y between the vertices; means for setting, for the second right-hand segment, an error value equal to the largest of the variations of X and Y between the vertices; means for incrementing the value of the X or Y term of greatest variation between the vertices from an initial position of that term for the first line segment; means for incrementing the value of the X or Y term of greatest variation between the vertices from an initial position of that term for the second straight segment, the initial positions of each of the line segments having the same value Y; means for subtracting from the error, for the first line segment, the least of the variations of the terms X or Y with each increment of the term X or Y having the greatest variation between the vertices, until the error reaches zero; means for subtracting from the error, for the second straight segment, the least of the variations of the terms X or Y with each increment of the term X or Y having the greatest variation between the vertices, until the error reaches zero; means for incrementing the X or Y term exhibiting the least variation between the vertices of the first line segment in response to the error term becoming zero for the first line segment; means for incrementing the X or Y term exhibiting the least variation between the vertices of the second line segment in response to the error term becoming zero for the second line segment; and means for continuing the operation until the incrementally increased X and Y values are equal to the X and Y values of the vertex

terminal for this line segment.

  It is further preferably provided means for interrupting the operation of the first means for incrementing the value of the X or Y term of greatest variation between the vertices for the line segment for which the error term reaches zero as long as the term error for the other line segment did not reach zero. According to another aspect of the present invention, there is provided a circuit for determining the X values of each end of a series of horizontal scan lines connecting a pair of line segments each of which is defined by a pair of vertices, the lines Horizontal

  scan defining an area to be restored on a peri-

  digital output signal, characterized in that it comprises: a first and a second circuit block, each

  of these circuit blocks comprising means for determining

  undermining the slope of a line segment and means for determining, as a function of slope, the starting and ending X values for each line segment of each scan line of the area to be retrieved; means for starting to operate both circuit blocks on the same scan line; and means for transforming the Y value of each circuit block into the Y value of the

  next scan line adjacent at the same time.

  The aims and features of the invention which have been indicated, as well as others, will be made clear in

  the person skilled in the art upon reading the detailed description

  below, with reference to the various figures of the

  drawings, on which the same references have been

  from one view to another, similar elements.

  Figure 1 is a representation of a graphical form divided into two quadrilaterals which, when displayed

  separately on a computer output device, pro-

  the complete original form.

  Figures 2A to 2D are illustrations of the form

  a simple quadrilateral broken down into line segments.

  FIG. 3 is a block diagram illustrating a computer graphics output system, produced in accordance with FIG.

  to the teachings of the present invention.

  Figure 4 is an illustration of the operation of a

  part of the circuit of the present invention.

  Figure 5 is a circuit diagram illustrating a

  to implement the present invention.

Notations and nomenclature

  Some parts of the detailed descriptions that go

  to follow are presented in terms of algorithms and symbolic representations of operations performed on

  bits of data in a computer memory. These descriptions

  algorithmic representations and these representations are the means used by those skilled in the computer industry to expose in the most effective way their achievements to

other men of the trade.

  In the present case, as in the case of

  ral, an algorithm is conceived as an autonomous sequence of steps leading to a desired result. The steps are those that require physical manipulations of physical quantities. Generally, although not necessary, these quantities take the form of

  electrical or magnetic devices that can be stored, transferred

  res, combined, compared and manipulated in any other way.

  It has proven to be convenient at times, mainly because it is a widespread use, to refer to these

  signals in terms of "bits", "values", "elements", "sym-

  "," characters "," numbers ", etc. However, we will keep

  mind that all these terms, and the terms

  must be associated with the appropriate physical quantities

  requested and are only convenient designations applied to

these quantities.

  Moreover, the manipulations performed are often

  terms, such as "addition" or "compa-

  reason, "which are generally associated with man-made mental operations, however, in most cases it will be neither desirable nor necessary to resort to human skills for the operations described below Of the present invention, these operations are machine-executed operations, and use may be made of machines such as universal computers or other similar apparatus in carrying out the operations of the present invention. the distinction between the method of executing operations on a computer

  and the actual calculation method. This invention

  The invention relates to process steps for operating a computer to process electrical or other physical signals (e.g.

  or other chemicals) to produce other physiological

wanted.

  The present invention also relates to a device

  to perform these operations. This device can be

  especially for the purposes of the invention, or it may consist of a universal computer selectively activated or reconfigured by a computer program stored in this computer. The algorithms that will be presented here are not specific to a particular computer or device. In particular, various universal machines could be used with written programs in accordance with the teachings to be discussed herein, or it might be more convenient to provide a more specialized device for performing the required process steps. The structure necessary for these various

  machines will flow from the description that we will give

below.

  Description of the preferred embodiment

  When designing computer systems, one

  noticed that the display of slow moving graphic images

  significantly woven the operation of most machines. This is because the amount of information that the computer must process for each frame to be rendered on the output display is very high, and because the manipulation of this information to be able to render the graphic image requires an excessive use of

the central processing unit.

  This is especially true for a system using an interface with multiple "windows" on its

  - output display. In such a system, simul-

  several programs in parts of the memory, these programs being available at any time. Textual and graphical information output from each of these programs must appear on the output display

  within a given set of predefined boundaries

  completed called "window" or "frame window". Each window can cover other windows, the "window in

  foreground "corresponding to the current active file.

  the user of the computer does not handle the

  only one window at a time, but can quickly switch to a program in another window to work with this program. In general, windows require a lot more memory and

  time for their handling than for operations

pleading no windows.

  The system of which the present invention is incorporated accelerates the computer graphics display by managing most operations by hardware, so that the information is instantly available. To allow the use of the material for the implementation of the restitution of the graphics, the system splits in quadrilaterals the graphic images to be restored on the display, quadrilaterals which can all be managed in the same way by the

  equipment. The system takes these quadrilaterals and breaks them

  again to give line segments which underlie the corresponding scan lines to be rendered on the output display, the different lines

  scan finally restoring a trapezoid. The coordinators

  X and Y data of the two ends of each scan line are then determined by the circuits of the

  present invention. The system takes these coordinates

  gulars and translates them into serial scan lines that can be stored in a frame buffer and displayed

on an exit display.

  Figure 1 is a representation of a graphical form divided into two quadrilaterals 8 and 9 which, when individually displayed on a computer output device, give the complete original form. Although the form illustrated in FIG. 1 is simple, those skilled in the art will understand that we can restore shapes whose complexity varies infinitely if we choose a number

  large enough individual small quadrilaterals.

  In fact, the system of the present invention has been used to reproduce very dimensional three-dimensional shapes.

nature complexes.

  Figure 3 illustrates in block diagram form a graphical output system 10 made in accordance with the present invention, which may be used with a universal computer system. The system 10 includes a bus interface logic 12 which receives information from the central processing unit of the computer system (not shown in the figures) concerning the graphic form that it is desired to display. The bus interfacing logic 12 receives information on an address line which indicates the particular location of the system where the input data will have to be transferred. The bus interfacing logic 12 receives on a data input line the data

  useful such as the description of the color. The logic

  bus interfacing 12 also receives, on a command line, a control signal indicating the manner in which one

will have to process the information.

  When reconstructing graphical representations from quadrilaterals in accordance with the teachings of the present invention, the input information includes the coordinates of the rectangular area that defines the particular window in which the displayed information should appear, the coordinates ( vertices) of the quadrilateral and the color data for each quadrilateral. The color data that must be presented to the display of the quadrilateral are stored in a routing stage 22

  data and memory interfacing. The summits of the

  latte and the information relating to the registration window is stored in a coordinate staging circuit 14 which includes a material performing comparisons of the incident information by means well known in the prior art such as registers and circuits

with doors.

  The comparisons made include comparing the X value of each vertex with the X value of each of the other vertices, comparing the Y value of each vertex with the Y value of each of the other vertices, and comparing each of the X and Y of the different vertices at the X and Y values of the edges of the window of

  framework in which the information should be presented

  tions. As this is done by hardware, the information

  are immediately available for use by the

  10, without any loss of system clock time.

  Information about the tops of the quadrilateral and

  to the framing window available in the floor circuit-

  14-coordinates are applied to a stage of se-

  coordinate 16 in which the quadrilateral is decomposed into a series of subsets each of which is

  formed of two line segments of the original quadrilateral.

  Each of these subsets is chosen so that the line segments define an area of the quadrilateral that

  can be traced through a series of horizontal scanning lines

  zontales parallel, each with a starting X value on one of the line segments and an X end value on the other line segment. For the most part, the two line segments define a

  trapezium comprising as many scan lines Y (horizontal)

  as possible, taking into account the shape of the quadrennial

  latere. When all the scan lines of all the

  subassemblies will be displayed on the display, the quadrant

Lateral will be defined in full.

  Figures 2A-2B illustrate an isolated quadrilateral

  divided into subsets according to the present invention.

  tion. The quadrilateral that is broken down is illustrated in Figure 2A, and the subsets thereof are illustrated in Figures 2B to 2D. As can be seen in FIG. 2, each subset comprises, when presented on an output display, a series of horizontal scan lines that start on one of the line segments defining the quadrilateral and terminate. on another

  right segment. The scan lines of each subset

  together the quadrilateral represent a trapezoidal

  zoidal of the original quadrilateral. When these horizontal lines

  of all trapezoidal subsets are scanned into the frame buffer for presentation on the output display, the quadrilateral shape is reconstructed.

  staggered in its entirety on the display.

  If we go back to Figure 3, after the four

  latters have been decomposed into subsets, the start and end X values of the various scan lines Y are determined in a functional addressing stage 18. In the preferred embodiment of the present invention, this is achieved by means of of circuits that determine the particular pixels constituting the X-values of beginning and end of

  each scan line inside the decom-

  position in subsets of the quadrilateral. This functional addressing stage 18 also realizes part of the framing necessary to adapt the various quadrilaterals to the framing windows, then transfers the signals to a mask generating stage 20 which configures the information in blocks of sixteen pixels which indicate the beginning and the end of each scan line and which are used to address

  the stage 22 of data routing and memory interfacing.

  The mask generation signals are also applied

  A linear address generator 24 translates the rectangular addresses delivered by the mask generator stage 20 into signals for linearly addressing the frame buffer for outputting. At this point, the color data relating to the quadrilateral to be displayed which had been stored in memory in stage 22 were transferred to the buffer of the output display (frame buffer). Various parts of the system which have just been describe are discussed in more detail in a number of pending patent applications, all of which belong to the Applicant and claim priority of applications filed on the priority date of this application and entitled: Hardware Implementation of Clipping Comparison Logic ( Material realization of a framing comparison logic), in the names of Chris Malachowsky and Curtis Priem, Method and Apparatus for Drawing in any Direction to Minimize Page Crossings (Method and device to perform tracing in all directions while minimizing page changes ), Chris Malachowsky and Curtis Priem's name, Clipping Utilizing Test Window, with the names of e Chris Malachowsky and Curtis Priem, Method and Apparatus for Controlling Index Register in a Graphic Subsystem (Method and Device for Monitoring the Index Register in a Graphic Subsystem), Chris Malachowsky and Curtis Priem, Method and Apparatus for Sorting Line Segments for Display and Manipulation by a Computer System, entitled Chris Malachowsky and Curtis Priem, Method and Apparatus for Translating Rectilinear Information into Scan Line Information for Display by a Computer System, named after Chris Malachowsky and Curtis Priem, and Method and apparatus for Decomposing a Quadrilateral Figure for Display and Manipulation by a Computer System (Method and device for decomposing a quad figured rilater for display and manipulation by a system

  computer), on behalf of Chris Malachowsky.

  The description of the present invention relates to

  the device and the method for determining the

  ends of each horizontal line of each subset

  trapezoidal assembly of the quadrilateral which will have to be produced at the end of the chain on the output display, in the form of scanning lines. Although the present invention is described in connection with the infographic system illustrated in FIG. 3, it will be appreciated by those skilled in the art that it can be applied extensively to other systems for producing displays.

  output graphics of computer systems.

  The circuits of the present invention receive circuitry that decompose each quadrilateral into subset input signals representing the pairs of line segments that underlie a series of common horizontal lines to be displayed on the system output display. computer system with which the infographic system is associated. These signals are applied to the circuits in the form of the rectangular coordinates of the

  vertices of the line segments underlying the trap

  The circuits providing these signals are described in a patent application being issued, belonging to the Applicant and claiming the priority of an application filed on the priority date of the present application and entitled Method and apparatus for Decomposing Graphics for Display and Manipulation by a Computer System, a process and device for decomposing computer graphics for display and manipulation by a computer system, on behalf of Chris Malachowsky. Since the line position information supplied to the circuit of the present invention includes only the

  vertices of the line segments defining the various sub-

  sets of the quadrilateral, while the output display handles the line scan information by line of

  scanning, it is necessary to determine the points of ex-

  each of the horizontal Y scan lines subtended by the straight segments so that the scan lines of the output display can be formed on the output display.

  to give the quadrilateral in question. -

  When drawing a segment on an output display such as a cathode ray tube, the segment is defined by a

  series of pixels on adjacent scanning lines

  Centes. If the segment to be plotted is horizontal, a single scan line is sufficient on the display to plot the segment, if we know the address of the start pixel and the end pixel. If the segment is vertical, a single pixel must be written on the display for each line of a number of adjacent scan lines. The intermediate slope segments between the horizontal and the vertical have a number of pixels per scan line variable depending on the slope of the segment. If the segment has a small slope, a number of adjacent pixels are plotted on each scan line of a plurality of

  adjacent scan lines, to complete the segment.

  If the beginning and ending X values of each series of adjacent pixels of each scan line are known, the pixels on the intercalary display can be filled and

thus complete the segment.

  It is necessary to know the position, on each

  scanning line, of each of the defined line segments

  naming the sides of the trapezes to scan on the display, in order to draw these trapezes. This is the case if we want to start and finish each scan line and frame the scan lines to limit them to a frame window. If there is an intersection of the framing boundary and a straight line segment, a process must be provided to determine the portion of each line segment to be plotted. The general concept of the circuit of the present invention is to determine these start and end points.

end of each scan line.

  The circuit of the present invention comprises two similar parts in order to be able to manage at the same time each of the

  two straight segments defining a subset. Cha-

  one of these circuit parts first begins with one of the vertices of a line segment, calculates the slope of this line segment, determines from this calculation whether it is the X value or the Y value of the segment that increases with the highest growth rate, determines and memorizes a

  initial error value which will have to be decremented

  slope, and starts plotting the values from a first vertex. We choose the error value for

  be a measure of the distance separating,

  to the axis of greatest displacement, the path

  exact right segment of the pixels actually produced

  ucts. If the value of X changes faster than that of Y, we increment (or decrement) by one pixel each step X, while we subtract the variation on Y of the error value

  until the error value reaches or exceeds zero.

  In this way, the value X for which the value Y is to be incremented (or decremented) is determined. This value X is stored as the end value X of the segment of the line in question, and the value is incremented (or decremented). Y. The first encountered value X is stored for the new value Y as the starting value X for the new scan value line associated with the new value Y. The operations continue in this manner, with storage for each value Y of the first and last X values encountered, up to

  reach the end vertex of the right segment.

  Because we have two circuits that function in the same way to simultaneously process the two line segments of each subset of a quadrilateral, the circuit part managing the first line segment ready to change level. It waits, when it is ready, for the circuit managing the other segment on the right to reach the moment when its value Y must change. When this occurs, the X values of a full scan line have been defined and can be processed; as a result, both circuits advance at the same time to the next value Y. The processing of the two start X values and the two end X values identified for each of the scan lines consists in determining the leftmost (minimum) and rightmost (maximum) values of the stored X values to be delivered to the

  mask generating circuit 20 illustrated in FIG.

  To quickly process each quadrilateral, when one

  has reached the end of a straight segment of a sub-

  together, the circuit loads the next straight segment to be processed. As is often the case, one line segment ends before the other. In such a case, there is no need to reload the line segment that does not end, and

264079Z

  This saves a lot of time.

  The circuit continues to process the line segments of the quadrilateral until completion of the figure. At each step, the generated values are transferred to circuitry for sorting the values, to determine the actual start and end values of the scan lines as a function of the operating direction of the circuitry of the present invention and the application. framing window information. This sorting operation must be carried out because, as pointed out above, the system and the

  circuit of the present invention are designed to select

  the best way to break down a shape so that the operation takes place as quickly as possible. By

  example, if a form to decompose is only partially

  within a frame window and parti-

  above or below this frame window, the operation will run faster if you do not need to treat the part outside the frame window. This can be achieved if the decomposition can run either from top to bottom or from bottom to top. In

  Moreover, if the operation takes place from the bottom up, one must

  Store fewer page boundaries in the memory if the operation runs from right to left than if it runs from left to right, as is usually the case

  the case. By crossing a smaller number of pages, we

sure faster operation.

  We will give below an algorithm in a pseudo-code similar to the programming language "C", allowing to

  perform the operations of the present invention. The algorithmic

  rithm uses a modified version of the algorithm of

  Bresenham well known; however, those skilled in the art

  will take that there are many other scan conversion algorithms that could be easily adapted

  to implement the present invention.

  In this algorithm: - "DeltaX" denotes the variation of X from one vertex to another, - "DeltaY" denotes the variation of Y from one vertex to another, - we give to X as initial value the value from the starting vertex, - Y is given as initial value the value of the starting vertex, - "Xterm" is the value X of the terminal vertex, - "Yterm" is the value Y of the terminal vertex,

  - "abso ()" returns the absolute value of the specific arguments

  and "main axis" means either X or Y depending on whether it is

  DeltaX that is greater than DeltaY, or the opposite.

  Initialization DeltaX = abs (X-Xterm) DeltaY = abs (Y-Yterm) main axis = ((DeltaY-DeltaX) ≥0)? Y: X slope = ((X-Xterm) "≥0)? Y: X up = ((YYterm) ≥0)? 0: 1 E =: (Delta (main axis)" 1) cb = Delta (main axis ) [0] / * lowest bit * / Main loop X startpixel (X, Y) as long as (X! = Xterm) {E = E - DeltaY if (testX (E, cb, up)) {finpixel (X Y) Y = Y + (high? 1: -1); X = X + (slope? 1: -1); start_pixel (X, Y) E = E + DeltaX; } else X = X + (slope? 1: -1); } finpixel (X, Y) Main loop test X testX (e, cb, up) = (e <0) Il (top && (cb == 0) && (e == 0) Main loop Y begin_pixel (X, Y ) as (Y! = Yterm) {E = E - DeltaX if (testY (E, cb, slope)) {end_pixel (X, Y) X = X + (slope? 1: -1); Y = Y + (high? 1: -1); pixel start (X, Y) E = E + DeltaY; else Y = Y + (high? 1: 1);) end_pixel (X, Y) Main loop test Y testY (e , cb, slope) = (e <0) Il (slope && (cb == 0) && (e == 0) FIG. 4 illustrates the operation of a part of the circuits of the present invention which has just been described for the management of a straight line segment Fig. 4 shows a line segment beginning at the top (0.5) and terminating at the top (4,6). the circuits first determine the variation of X between the two vertices of the line segment and the variation of Y between the vertices, then determine from these variations the slope of the line segment, determines the main axis (the value presenting the largest variation) and makes the error term equal to half of the value of the variation of X. We choose this value half to balance the pixels defined by the

  circuit for the right segment to give an appearance

  more symmetrical From these values, tracing begins, with the vertex value of X stored as the value of the first X on the scan line for that line segment. The circuit then decrements the error of the value of the variation according to Y and tests two conditions: "is the error term now less than zero?" and "is the tracing direction up and

the error equals zero? "

  If none of these conditions are satisfied, the operation continues until the value of the error term reaches a point such that the tested condition becomes true,

* that is, the error term reaches or exceeds zero.

  The value of the term X is then stored as the last value X for this scan line (for this value Y) of this line segment. The operation continues for the value Y

  next, by memorizing the first value X after the in-

  crement as the starting X value for the scan line, and again adding the value of the variation of X to the error term. The operation continues by following the X-scan increment scan line and reducing the error term until the error term reaches or exceeds zero. Here again, we store the value X as the last value X of the scan line, we add again the variation of X to the error terms and we go to the

next Y value.

  The operation continues to determine the value X equal to the X terminal value for the line segment; we then defined the entire line segment and the circuit can be initialized for a new line segment. Note that although each of the parts of the circuit operates independently to process one of the two straight segments, when each part of the circuit

  who manages a right-wing segment has completed a line of

  Given the data, it tests whether the other line segment has been completely defined for this scan line. If this is not the case, then the circuit waits for the scan line to be finished for the other line segment so that the two circuits can progress together and the complete definition of each can be transferred.

  scan line to subsequent stages at one time.

  FIG. 5 illustrates a circuit 30 constituting a mode of

  preferred embodiment for the implementation of the invention.

  The circuit 30 includes two essentially similar parts 32 and 34, each of which manages one of the two right-hand segments. We will only describe part 32, because of this similarity. When determining the end values of the scan lines, initialize the circuits for each line segment. To achieve this, the party 32 receives, at a first clock cycle, input values representing the X values of the beginning and the end of the first line segment (the line segment A). These values are, respectively, stored in registers 36 and 38 and transferred to multiplexers 40 and 42. Multiplexers 40 and 42

  transfer X values to EXCLUSIVE OR gates 44 and 46.

  These EXCLUSIVE OR gates 44 and 46 also receive input values ("zero" or "one") which make it possible to transfer the value X as it is or complemented, in order to be able to add or subtract the values by means of an adder 48. If, for example, a "zero" is applied to the EXCLUSIVE OR gate 44, the value on the other input of this gate will simply be transferred to the adder 48 while, if a "one" is applied to the gate * 44, the input value will be complemented so that it will be easy to remove (in binary). To determine the variation of the value of X between the beginning and the end, the difference between the terms X is calculated and, by a multiplexer 50, this difference is applied for storage to a register 52 of variation of X. At the cycle of following clock is applied to the multiplexers and the 42 values of Y start and end of the line segment A; similarly, the variation of Y is determined by means of the adder 48 and is stored both in a Y variation register 54 and in a register

Error 56.

  The storage of the variation value of Y in the error register 56 makes it possible to determine the main axis without the need to resort to additional circuits. This is done by transferring to the adder 48 the values stored in the registers 52 and 56, complementing one of them to determine, among DeltaX and DeltaY, the highest value. This highest value is then halved by shifting the value by one unit to the right in the adder 48 and placing it in the error register by means of the multiplexer 50. This completes the initialization of the

circuit 32.

  At the same time, the circuit 34 receives the values of X and Y of start and end and completes their initialization for the other segment of the line to be processed, that is to say the line B. Once the initialization completed, each of circuits 32 and 34 begins processing the right segment information of the line segment that it manages. If only the circuit 32 is considered, the current value of X for the line A is kept in the register 36. The value in the register 36 is tested, by means of a comparator 58, with respect to the terminal value of X stored in the register 38. If the values are not equal, the multiplexers 40 and 42 transfer to the adder 48 the error and the values of variation of Y via the EXCLUSIVE OR gates 44 and 46, so as to subtract from the error of the variation of Y. The reduced error value is stored in the error register 56, and the process continues until the error value reaches or exceeds zero. The ratio between the error and the zero value is tested by a state machine 60 which, when the test condition is satisfied, transfers the current value of X as the end value for that scan line Y, causes the incrementation (or decrement) the value of Y and restores the error register by adding to the current error value a value equal to the value of the variation of X. As was pointed out above, when the one or the other of the circuits 32 or 34 arrives at the moment when a value of Y must change according to the value of the slope of the line segment, the first of the circuits 32 or 34 which reaches the value of change signals it to the state machine 60 and wait that the other of the two circuits 32 or 34 is also ready to change the value of Y. When this is the case, the state machine delivers signals to advance each of the two circuits 32 and 34 at the next line Y. In this way, the two circuits 32 and 34 handle the same scan line Y at the same time, and thus can be transferred to the following stages at the same time.

  values of both ends of a scan line.

  When the circuit 30 of FIG. 5 is processing a line segment to determine the X values of the ends of the horizontal line, and the line segment is a line segment with a slope greater than or equal to unit, that is to say corresponding to an inclination angle of 45 or more, the circuit operates, essentially, in the same way. The starting and ending X values of each line segment are first processed by each of the circuits 32 and 34 to determine, in each case, a change in the value of X. The values of Y of start and end of each line segment are then processed by each circuit to determine, in each case, a change in the value of Y. The change in value of X is then compared to the change in value of Y for each of the two segments of the line, and the error is given a value equal to half of the variation of the value of Y for each line segment having a slope greater than unity. The processing then takes place in the same manner as before, advancing however initially step by step according to the values of Y until a variation of X is encountered. Meanwhile, a circuit 64 is in the process of managing the values The circuit 64 includes a register 66 which initially receives and holds the value of Y, a multiplexer 68 which receives a number of signals including the end of Y value of each line segment and the minimum and maximum values. Y and a Y end register 70. The values of the registers 66 and 70 are compared by a comparator 72 which is able to determine if one value is greater than, less than or equal to the other. This configuration can be used to determine when a line segment has reached its end point, and also to determine if the figure

  is inside the frame window.

  The circuit 64 also includes a Y-register 74 which receives as input values representing the maximum or minimum framing values Y. These values indicate the position of the upper and lower borders of the frame window in which the quadrilateral must be written. The framing register 74 receives one of these values via a multiplexer 76 which passes either the minimum Y value or the maximum Y value of the framing window, depending on the direction in which

  the information is written in the frame buffer.

  In some cases, a particular shape to be restored can be framed both on its upper edge and on its lower edge. The framing at the beginning edge of the shape is determined by comparing the initial value Y of the register 66 with the starting framing value, which is applied to the register 74 by a multiplier 76. If, for example, the information is in progress at the bottom of the screen, the value applied is the minimum framing Y value; if you go the other way, it's the

  maximum framing Y value applied to the register.

  A multiplexer 78 applies the framing value to the comparator 72. The quantity comparator 72 then delivers a signal which inhibits the restitution as long as the value Y

  is not inside the frame window.

  The value of Y placed in the register 70 is the Y value of the last line & traced in the trapezoid or the appropriate framing border Y, depending on the value at which the figure must be completely completed once

  the shape is inside the frame window.

  This value (register 70) is delivered by the circuit (multiplexer 78) which compares the current value of Y (register 66) with this end value of Y. In the case where the form extends beyond the window of framing, the end Y value is placed in the register 70 and compared in the comparator 72 to the actual value Y. In this way, the end value of the part of the shape to be rendered can be determined. This is particularly interesting with the present invention, which is able to write the information in the frame buffer both upward and downward (i.e. in the direction of increasing Y's or decreasing, respectively). This makes it possible to execute the line scan conversion so that the visible (non-framed) information is processed first when

  this operation, before the information that will be framed.

  We can ignore this latest information, this

  which significantly increases the speed of operation.

Claims (3)

PREVENDICATIONS   1. A circuit (30) for determining the X values of each end of a series of horizontal lines connecting a pair of line segments each of which is defined by   a pair of vertices, the area defined by the horizontal lines   zontales to be presented on an output display of a computer system, circuit characterized in that it comprises: - means (32) for determining the variation of the value X between the vertices of a first segment of line, - means (34) for determining the variation of the X value between the vertices of a second line segment, - means (32) for determining the variation of the Y value between the vertices of the first line segment, - means (34) for determining the variation of the Y value between the vertices of the second line segment, - means (32) for determining whether the slope of the first line segment is greater than unity, - means (34) for determining if the slope of the second line segment is greater than unity; - means (32) for establishing, for the first line segment, an error value equal to the greatest of the variations of X and Y between the vertices, - means (34) to establish, for the second segm right angle, an error value equal to the largest of the X and Y variations between the vertices, means (32) for incrementing the value of the X or Y term of greatest variation between the vertices from an initial position of this term for the first line segment, - means (34) for incrementing the value of the X or Y term of greatest variation between the vertices from an initial position of this term for the second segment of right, the initial positions of each of the line segments having the same value Y, - means (32) for subtracting from the error, for the first line segment, the least of the variations of the terms X or Y with each increment of the term X or Y   with the most significant variation between   put, until the error reaches zero, - means (34) to subtract from the error, for the second straight segment, the least of the variations of the terms X or Y with, each increment of the term X or Y   with the most significant variation between   set, until the error reaches zero, - means (32) for incrementing the term X or Y having the least variation between the vertices of the first line segment in response to the error term becoming zero for the first right-hand segment; means (34) for incrementing the X or Y term exhibiting the least variation between the vertices of the second line segment in response to the error term becoming zero for the second line segment, and - means ( 32,34) to continue the operation until the values X and Y reached by incrementation are equal to the values X and Y of the terminal vertex for this right segment.   2. The. circuit for determining the X values of each end of a series of horizontal lines connecting a pair of line segments according to claim 1, characterized in that it further comprises: - means for interrupting the operation of the first means for incrementing the value of the X or Y term of greatest variation between the vertices for the line segment for which the error term reaches zero as long as the error term for the other line segment does not reaches zero.   3. A circuit for determining the X values of each end of a series of horizontal scan lines connecting a pair of line segments each of which is defined by a pair of vertices, the horizontal lines of   scan defining an area to be restored on a peri-   computer output circuit, characterized in that it comprises: - a first (32) and a second (34) circuit block, each of these circuit blocks comprising means for determining the slope of a segment of and means for determining, as a function of the slope, the starting and ending X values for each line segment of each scan line of the area to be restored, - means for starting to operate the two blocks of circuit on the same scan line, and means for transforming the Y value of each circuit block into the Y value of the next scan line adjacent at the same time. 2C