FR2640744A1 - Ratio meter control device comprising digital storage means of limited capacity - Google Patents

Abstract

The present invention relates to a ratio meter control device characterised in that it comprises means 100 capable of generating a digital signal representing the parameter to be visualised, storage means 310 defining a coding of the numerical signal on the basis of a preestablished law of the sine, cosine or tangent type, the storage means 320 being addressed by intermediate-significance bits of the digital signal, and interpolation means 350 capable of correcting the signal output by the storage means 310 on the basis of the least significant bits of the digital signal.

Description

 The present invention relates to the field of logometers, that is to say devices comprising a plurality of crossed coils, preferably two coils crossed at 90, a rotationally guided axis, a magnet secured to the axis placed inside. coils, an indicator needle external to the coils and secured to the axis, and control means applying appropriate electrical signals to the coils.

 Most often logometers also include a fixed cup containing a damping liquid, which bathes the magnet.

 Each of the coils generates a magnetic field proportional to the current flowing through it. The magnet is positioned according to the resultant of these fields. For a two-coil logometer, the angle defined by the indicator pointer, with respect to an original position, is therefore determined by the relation tan 1 li / 12, in which 11 and 12 represent a value proportional to the ampere-turns circulating respectively in the coils.

 In the automotive field, high-deflection logometers are generally used to visualize a speed or the number of revolutions of the engine. The logometers with large deviation generally comprise a spiral of return integral with the axis.

 The structure and operation of the logometers are well known to those skilled in the art and will therefore not be described in more detail later.

 The present invention more specifically relates to the control means designed to apply appropriate electrical signals on the coils of a log.

Numerous control means have already been proposed for this purpose, for example in the documents US-A-2,057,845, DE-A-853 181,
US-A-2,500,628, US-A-3,168,689, US-A-3,327,208, US-A-3,329,893,
US-A-3,624,625, US-A-3,636,447, US-A-3,732,436, US-A-3,946,311,
US-A-4,051,434, US-A-4,070,665, DE-A-2,924,617, US-A-4,230,984 and US Pat.
EP-A-0 218 737.

 The present invention now aims to provide new control means for improving the accuracy of the logometers while being simple structure and reasonable price.

 Another object of the present invention is to provide control means for operating a 360 display.

 According to a first aspect, the aforementioned objects are achieved by means of logometer control means using an input signal whose frequency is proportional to a parameter to be displayed, and comprising for this purpose a counter which receives on its counting input a fixed frequency clock signal, and on its control input a signal whose frequency is related to the frequency of the input signal so that the counter counts the clock signal pulses during the period of the signal applied to its input control unit and a divider which divides a programmable constant by the signal from the counter so that the divider has a digital signal representative of the frequency of the input signal.

 According to a second aspect, these objects are achieved according to the present invention by means of control comprising a module responsive to the slope of the signal representative of the parameter to be displayed.

 According to a third aspect, the aforementioned objects are achieved, according to the present invention, by means of control means comprising means capable of generating a digital signal representative of the parameter to be displayed, memory means defining a coding of the digital signal on the basis of of a preset law, of the sinus, cosine or tangent type, the memory means being addressed by bits of intermediate weight of the digital signal and interpolation means adapted to correct the signal from the memory means, on the basis of least significant bits of the digital signal.

Other features, objects and advantages of the present invention will become apparent on reading the detailed description which follows and with reference to the appended drawings given by way of non-limiting examples and in which - Figure I represents a schematic view, under block shape
functionalities of control means conforming to a mode of
preferred embodiment of the present invention; FIG. 2 represents a table of maximum frequency values;
acceptable based on programmed data on the entries of the
Figure 3 shows a table of minimum frequency values
acceptable based on data programmed on the inputs of the
device, - figure 4 represents, in the form of functional blocks, a smoothing
of samples, - Figure 5 shows, in the form of a flowchart, a limitation
of slope, - Figure 6 represents values, corresponding to a sine / cosine law,
contained in a memory table, FIG. 7 schematically represents the structure of stages of
power attacking the coils of the logometer, - figure 8 represents in tabular form the direction of the currents in
the coils and identifies the power stages made conductive in
function of the quadrant considered, - Figure 9 represents the structure of an output logic block, - Figure 10 represents a flowchart of the general timing of the
device, and - the figure It represents in flowchart form the operation
a hysteresis module.

 The control means according to the preferred embodiment of the present invention, shown in Figure 1 attached essentially comprise an input stage 100 for generating a digital signal representative of the frequency of the input signal Fs, which frequency Fs is itself proportional to the parameter to be displayed, an intermediate processing stage 200, a coding stage 300 and an output stage -400.

 According to FIG. 1, the input stage 100 comprises an input trigger module 110, a pre-divider module 120, a clock frequency divider module 130, a periodemeter counter 140 and a programmable divider 150.

 The input signal whose frequency Fs represents the parameter to be displayed is applied to the trigger module 110.

 The trigger module 110 provides, in a manner known per se, the shaping of the input signal in the form of logical slots of the same frequency Fs.

The signal from the trigger module 110 is applied to the pre-divider module 120. This provides a division of the input frequency Fs A by a factor 2A with A integer between 0 and 2a-1, programmable
A by inputs 122 of the module 120. The division factor 2 can take 2a values. The signal obtained at the output of the pre-divider 120 is at the frequency Fs / 2A.

 According to the example illustrated in the appended FIG. 1, the pre-divider 120 comprises a = 2 programming inputs 122. It can therefore optionally divide the input frequency Fs by 1, 2, 4 or 8.

 The control means exploit a clock signal of fixed frequency Fo. This clock signal can be generated for example by a conventional quartz oscillator, not shown in the accompanying figures.

The input clock signal is preferably applied to a frequency divider 130. This divides the clock input frequency Fo by a factor B so that the output of the divider 130 d is available. an appropriate pilot clock signal of frequency Fe =
Fo / B.

 The pilot clock signal from the divider 130 is applied to the counting input 142 of the counter 140.

The counting periods of the counter 140 are determined by the signal from the pre-distributor 120, that is to say that the counter 140 counts the number C of pulses from the divider 130 at the frequency Fe between two consecutive fronts of the same type. , for example two rising edges, of the signal coming from the pre-distributor 120 at the frequency
Fs / 2A. The counter 140 therefore works periodemeter. It comprises D bits, for example 20 bits; passing the high bit of the highest-order bit of the counter 140 determines that the frequency of the input signal is less than the minimum acceptable frequency.

 The numerical value C presented at the output of the counter 140 is renewed at each active edge, for example each rising edge, of the signal coming from the pre-divider 120, and transferred to the divider 150 at each request thereof.

 The divider 150 divides a programmable constant E by the input quantity C from the counter 140. It provides the result G of the division E / C on its output 152.

 The constant E is programmed by e inputs of the divider 150, 6 inputs for example, so that for the maximum value of the input frequency Fs, the division of E by the numerical value C corresponds to the maximum angle of deviation .

 The divider 150 supplies the signal G on H bits, for example on 10 bits.

 The number H of bits output from the divider 150 is determined by H> log (360 / I) / log2, where I represents the desired display resolution.

 The capacity of the counter 140, and therefore the number of bits D output therefrom, are chosen as a function of the clock frequency Fe and the minimum allowable frequency.

 The number of prefix bits 120, which determines the largest predivision factor 2 (2 2 1>, is chosen according to the range of input frequencies to be processed.

 According to the invention, a minimum number of bits are set at the output of the counter 140, for the minimum counting period Cmin, ie at the maximum input frequency Fs, FsMax, such that d = H + 1.

 According to the above example, if the number H of bits at the output of the divider 150 is equal to 10, this leads to choosing for Cmin a minimum number of 11 bits, namely Cmin # 2048.

 More precisely, the predivision factor 2A is chosen in the pre-divider 120 so that one always has 2H + 1 (Cmin <2H + 2, ie 2048 # Cmin (4096 according to the above example.

 Moreover, we denote E, such that E (e) = 2H2h1 (2h2 + h3)], in which e h3 is an integer between O and 2e-1, h1 and h2 are integers such that h1 + h2 = H +1 and h2 = e.

According to the particular example mentioned above, of course not limiting, we have - a (number of bits of the pre-divider 120) = 2, - possible factors of frequency division in the pre-divider '
120: 2A = 1, 2, 4 or 8, - Fo frequency of the input clock signal: 4,194304MHz, - division factor B of the divider 130 = 8, - Fe frequency of the pilot clock signal: 524288 Hz , - number of bits of the counter 140: 20, - number of bits e for the programming of the constant E-: 6, - number of bits of the divider 150: 10, - value of the constant E:
210L25 (26 + h3)] = 2 (64 + h3), - maximum deflection angle: 360, - resolution: 0.35, - input frequency range that may correspond to a deflection of
360: 129 to 2048 Hz, - full scale deviation accuracy better than +/- 0.75%.

 In the attached table of FIG. 2, the factors 2A and h3 to be imposed with the aid of the bits and e control bits respectively have been given to obtain a full scale deflection of 360 "at the maximum input frequency FsMax. in the context of the above example.

For example, for Fs Max = 655.36 Hz, the bit of module 120, such as 2A = 4, will be programmed and the e bits of module 150 will be programmed, such that h3 = 36.

Such a table can be determined for other exemplary embodiments by calculating the values
FsMax = Fe x 2A / [2hlt2h2 + h3) as a function of a and e.

 FIG. 3 also gives the minimum frequency of the input signal Fs acceptable as a function of the predivision factor 2A. This minimum frequency corresponds to the maximum measurable period determined by the activation of the Dth bit of the counter. 140.

 At the output of the divider 150, an H-bit digital signal is obtained which is proportional to the frequency of the input signal and to the desired deflection angle of the log.

 The signal obtained at the output of the programmable divider 150 is directed to the processing stage 200.

 The latter comprises a module 210 which establishes a rolling average over K bits and a module 250 slope limiter.

 As illustrated in FIG. 4, the module 21G comprises for this purpose K registers 212, 214, 216 and 218, 2 pointers 220, 222 and an adder / subtractor 230. The signals coming from the output of the divider 150 are successively introduced into the registers 212, 214, 216, 218.

The pointer 220 contains the address of the register 212 to 218 having received the last a signal from the divider 150. The pointer 222 contains instead the address of the register 212 to 218 having received the first a signal from the divider 150. The adder / subtracter 130 contains a number equal to the sum of the contents of K registers 212 to 218.

 When a new value is presented at the output of the programmable divider 150, the contents of the register 212 to 218 identified by the pointer 222 are subtracted from the content of the adder / subtractor 230, the addresses of the pointers 220, 222 are incremented by a step, the new value available at the output of the divider 150 is inserted into the register 212 to 218 identified by the pointer 220, and the contents of this same register is added to the content of the adder / subtractor 130.

 Assuming that the programmable divider 150 supplies its output signal on H bits and the module 210 realizes a sliding average over 4 samples and consequently contains 4 registers 212 to 218, the adder / subtractor 230 contains H + 2 bits, or 12 bits in the above example where the divider 150 provides its 10-bit signal. The content of the adder / subtracter 130 is transferred after each said subtraction / addition operation to the module 250, with a k-bit shift to the right such that K = 2k. In other words, the k most significant bits. the content of the adder / subtractor 230 is eliminated during the transfer into the module 250.

 This module 250 serves to limit the slope of the signal. It proceeds as indicated in FIG. 5 by comparing the average value, ie AFm supplied at a given instant at the output of module 210 to the corresponding previous value, which will be called AFmp.

 For this purpose, this value AFmp is stored in a register or an appropriate memory cell. The module-250 provides at its output an AF signal.

If in step 252, the module 250 determines that AFm> AFmp the slope of the signal increases, go to step 254 during which the module 250 compares the difference (AFm - AFmp) to a predetermined threshold
D1.

 If AFm - AFmp Dl, the increasing slope of the signal exceeds the authorized threshold, the module 250 then imposes AFs = AFmp + D1 at step 256.

If against the module 250 determines in step 254 that
AFm - AFmp gD1, we go to step 258 which makes the signal Afs equal to
AFm.

If in step 252, the module 250 determines that AFm <AFmp, the slope of the signal decreases, go to step 260 during which the module 250 compares the difference (AFmp - AFm) to a predetermined threshold
D2.

If AFmp - AFm> D2, the decreasing slope of the signal exceeds the authorized threshold D2, the module 250 then imposes
AFs = AFmp - D2 in step 262.

If on the other hand the module 250 determines in step 260 that AFmp-AFm 4 D2, we go to step 264 which makes the signal AF equal to
AFm.

In step 266 the previous average value stored
AFmp is refreshed at the new AFs value. This value is directed to the coding module 300. This module 300 comprises memory means 310 and an interpolator 350. The memory means 310 are preferably formed of a ROM; they may however be formed of any functionally equivalent means, for example a structure known under the name PLA and described in particular in "Integrated
Circuit Engineering - Glaser and Subak - Sharpe, Addison - Wesley p 726 ", or a combinatorial logical structure with doors.

The value of AFs is provided at the output of module 250 on
R bits, for example 10 bits and applied to the coding stage 300.

 For a full-scale display on 360, the 2 most significant bits of the signal AFs that will be called SQ (1) and SQ (O) thereafter code the quadrant, arbitrarily first quadrant for Su (1) = O and SQ (O) = O, second quadrant for SQ (1) = O and SQ (O) = 1, third quadrant for Su (1) = 1 and SQ (O) = O and fourth quadrant for SQ (1) = 1 and SQ (O) = 1.

 The rl bits of intermediate weight, for example rl = 4, will be used to address the memory means 310.

 The r2 bits of the lowest weight of the signal AFs, for example r2 = 4, will be used to drive the interpolator 350.

Services
The memory means 310 contain 2 words of M bits representing the values of sin L900 x N / 2rl with N integer between 1 and 1.

 We thus have the value of sine [(90 x N) / 2r1 at the address N in the memory means 310 and the cosine value [(90 x N) / 2r1] at the address (2rl-N).

 FIG. 6 shows, in the hypothesis where rl = 4, the 2rl = 16 values stored in the means 310, at the addresses N.

 It will be assumed for the rest of the presentation that the logometer comprises two coils crossed at 90, referenced BI and B2, for respectively receiving signals of the sine and cosine type.

 The means 310 are associated with a pointing logic controlled by the two most significant bits SQ (1), SQ (O) coming from the module 250.

For the determination of the sine-type signals to be applied to the coil B1, the pointing logic reads the value contained in the address N if the penultimate bit of the highest weight, SQ (O) is at 0; on the other hand, it reads the value contained in the address (2rl-N) if the penultimate bit of the highest weight SQ (O) is at 1;
Similarly for the determination of the cosine type signals to be applied to the coil B2, the pointing logic reads the value contained in the address (2rl-N) if the penultimate one reads the highest weight SQ (O) is at O; on the other hand, it reads the value contained in address N if the penultimate bit of highest weight SQ (O) is at 1.

 The values that are read in this way by the pointing logic roughly represent the sine and the cosine, respectively, of the desired deflection angle.

 These values are then refined in the interpolation module 250 on the basis of the r2 least significant bits from the module 250.

The interpolation module 350 proceeds as follows, calling: R (N) the content of the means 310 at the address N; IP the decimal value corresponding to the r2 least significant bits from module 250; Rcs a sine signal and Rcc a cosine signal calculated by the module 350 a) if SQ (1) = O and SQ (O) = O is for the first quadrant or SQ (1) = 1 and SQ (O) = O for the third quadrant
Rcs = R (N) + lP [(R (N + 1) - R (N)] / 2r1 and if N = 1, Rcc = 1 - IP1 - R (2r1 - 12r1, if Nul, Rcc RR (2rl - N) - IP [R (2r-N) - R (2rr-1-N)] / 2r1 b) if SQ (I) = O and SQ (O) = 1 for the second quadrant or SQ (1) = and SQ (O) = I for the fourth quadrant: if N = 1 Rcs = 1 - IPI - R (2rl - 1)] / 2rl if N / I Rcs = R (2rl - N) - IPR (2rl - N ) - R (2rl - 1 - N) 2r
Rcc = R (N) -RR (N + 1) -R (N)] / 2r1.

 The signals representing the sines and cosines, coming from the interpolation module 350, are applied to the output stage 400.

This comprises two modules 410, 420 which will determine cyclic ratios related to the signals applied to the input of
Stage 400, and an output logic module 450.

 The modules 410, 420 are formed of up-down registers. Periodically, at the TRC period, the signals from the interpolator 350 are respectively loaded into these registers 410, 420. These are decremented with a fixed frequency Fdec. The output 412, 422 of the modules 410, 420 is at the high logic level as long as the contents of the up-down registers have not descended to 0. The output 412, 422 of the modules 410, 422, on the other hand, indicates a low logic state if the return to zero of the counter has been realized.

 Thus, on the outputs 412, 422 of the modules 410 and 420, logical signals are obtained whose duration at the high level is proportional to the sine and cosine respectively of the desired deflection angle.

obtient ainsi à la sortie des modules 410 et 420, un signal carré de fréquence l/TRc et de rapport cyclique égal respectivement au sinus et au cosinus de l'angle de déviation recherché.Moreover, we take

thus obtaining at the output of the modules 410 and 420, a square signal of frequency 1 / TRc and duty cycle respectively equal to the sine and cosine of the desired deflection angle.

For example, M = 8 bits, Fdec = 32768Hz and 1 / TRC = 128 Hz.

 The purpose of the output logic block 450 is to control the power stages supplying the coils of the logometer.

 As illustrated in the appended FIG. 7, these stages can be formed of 8 transistors T0 to T7 connected in pairs with their main conduction path between a supply terminal + Vcc and the ground.

 The two coils B1 and B2 are connected between the points common to pairs of transistors To, T4; T1, T5; T2, T6; T3, T7 associated.

 The output logic block 450 receives, on the one hand, the two most significant bits SQ (1) and SQ (O) of the signal coming from the slope limiter module 250, and on the other hand the signals Rcs and Rcc. from modules 410, 420.

 The output logic block 450 will determine the direction of the currents passing through the coils B1 and B2 as a function of the required quadrant identified by the two most significant bits SQ (1) and SQ (O) coming from the module 250.

 For example, if these two bits are at the levels 00, which corresponds to a first quadrant Qo, the block 450 will impose the passage of the current from Blo to B11 and from B20 to B21 according to the representation of FIG. conductors transistors T1, T4, T3, T6.

 If the two most significant bits coming from the module 250 are at the levels 01, which corresponds to a second quadrant Q1, the block 450 will impose the passage of the current from B10 to B11 and from B21 to B20 and make the transistors conductive. T1, T4, T2 and T7.

 If the two most significant bits coming from the module 250 are at the levels of 1.0 which corresponds to a third quadrant Q2, the block 450 will impose the passage of the current from B11 to B10 and from B21 to B20 and make conductive the transistors TO, T5, T2 and T7.

Finally, if the two most significant bits coming from module 250 are at levels 1, I, which corresponds to a fourth quadrant Q3, block 450 will impose the transition from B11 to B10 and from B20 to
B21 and make the transistors TO, T5 and T3, T6 conductive.

 These arrangements are summarized in Figure 8.

The modules of the currents flowing through the coils are given by the temporal modulation of a current lo, passing through the conductive transistors, by the signals Rcs and Rcc coming from the modules 410, 420, which are applied in an appropriate order on the bases or gates GO at
G7 transistors.

 For this, the output logic block 450 can assume the form shown in the appended FIG.

 According to FIG. 9, the module 450 comprises an exclusive OR gate 452 with two inputs, two inverters 454, 456, four AND gates 458, 462, 466, 470 with two inputs and four OR gates with two inputs, one of which is an inverting input.

According to the representation given in FIG.
RCs the signal from the module 410 and representative of a sinus, Rcc the signal from the module 420 and representative of a cosine, SQ (1) the most significant bit from the module 250 and SQ (O) the bit of immediately lower weight from module 250.

The gate 452 receives on its inputs the signals SQ (1) and
SQ (O).

 The inverter 454 receives as input the signal Su (1) while the inverter 456 receives as input the signal SQ (O).

 The inputs of the gate 458 receive the signal Rcs and the signal from the inverter 454. The output of the gate 458 is connected to the gate G1 of the transistor TI.

 The inverting input of the gate 410 receives the signal Rcs while its non-inverting input receives the signal SQ (1). The output of the gate 460 is connected to the gate G4 of the transistor T4.

 The inputs of the gate 462 receive the signal Rcs and the signal SQ (I). The output of the gate 462 is connected to the gate Go of the transistor To.

The inverting input of the gate 464 receives the signal Rcs while its non-inverting input receives the signal coming from the inverter 454. The output of the gate 464 is connected to the gate G5 of the transistor
T5.

 The inputs of the gate 466 receive the signal Rcc and the signal from the inverter 456. The output of the gate 466 is connected to the gate G3 of the transistor T3.

The inverting input of the gate 468 receives the signal Rcc while its non-inverting input is connected to the output of the gate 452. The output of the gate 468 is connected to the gate G6 of the transistor
T6.

 The inputs of the gate 470 receive the signal Rcc and the signal from the gate 452. The output of the gate 470 is connected to the gate Q2 of the transistor T2.

The inverting input of the gate 472 receives the signal Rcc while its non-inverting input receives the signal coming from the inverter 456. The output of the gate 472 is connected to the gate G7 of the transistor
T7.

 The timing of the control device is operated as illustrated schematically in the appended FIG.

 With reference to FIG. 10, FLAGO is called the appearance of a validation signal at the output of counter 140 or pre-distributor 120, indicating that a value C is available at the output of counter 140, and the appearance is called FLAG1. a validation signal at the output of the modules 410, 420 indicating that they are ready to receive new data from the coding stage 300.

In Figure 10, step 500 illustrates an initia step
I isation.

 In the next step 502 the system examines whether FLAGO is enabled.

 If so, it passes successively to the steps 504: loading the content C of the counter 140 in the divider lus0, 506: division operation E (e) / C in the module 150, and 508: progression of the sliding average in the module 210 .

 Step 508 is followed by step 510.

 Similarly, step 502 is followed by step 510 if it is determined in step 502 that the FLAGO signal is not validated.

 During step 510, the module 250 limits the slope of the signal as indicated above. Step 510 is followed by the stamp 512. This corresponds to the calculation of the sine and cosine in the coding step 300.

 Step 512 is followed by step 514. During this, the system examines whether the FLAG1 signal is validated.

 If so, it proceeds to step 516 for loading up-down registers 410, 420. Step S16 is followed by step 502.

 If step 514 determines that the FLAG1 signal is not validated, this step loops back on itself.

 Note that the slope limiter module 250 operates an angular limitation. This is converted into a limitation of the first derivative of the angle with respect to time (or in a limitation of angular velocity) by inserting the stop loop 514 into the branch containing the limiting operation of slope.

 Naturally, the present invention is not limited to the particular embodiment which has just been described but extends to all variants that are in keeping with its spirit.

 In a first variant, the module 210 establishing the sliding average may be placed before the programmable divider 150 and not after it.

 According to a second variant, the module 210 establishing the sliding average can be replaced by a module generating a hysteresis effect, that is to say taking into account the samples of the module that precedes it, only if the samples differ from the immediately earlier samples of a predetermined threshold.

 The operation of this variant of the module 210 is shown schematically in Figure 1 I attached.

 With reference to FIG. 11, Q is the sample from the module (140 or 150) preceding the hysteresis module 210, and Qp the previous sample.

 This sample Qp is stored for this purpose in a register or an appropriate memory cell. The module 210 provides at its output a Qs signal.

 If in step 220, the module 210 determines that Q> Qp the slope of the signal increases, go to step 222 during which the module 210 compares the difference Q - Qp to a predetermined threshold D3.

 If Q - Qp> D3, the increasing slope of the signal reaches the required threshold D3, the module 210 then imposes Q3 = Q in step 226.

 If on the other hand the module 210 determines in step 222 that Q - Qp D3, we go to the step 224 which makes the signal Qs equal to Qp.

 If in step 220, the module 210 determines Q <Qp the signal slope decreases, go to step 228 during which the module 210 compares the difference Qp - Q to a predetermined threshold D4.

 If Qp - Q) D4, the decreasing slope of the signal reaches the required threshold D4, the module 210 then imposes Qs = Q at the step 232.

If, on the other hand, the module 210 determines in step 230 that
Qp - Q sD4, we go to step 230 which makes the signal Qs equal to Qp.

 In step 234, the previous value Qp stored is refreshed to the new value Qs. This value is directed to module 250.

According to one. third variant, it is possible to store in the means 310 sampled tangent values over 45 and not sine-cosine values sampled over 90 "as indicated previously.

 In this case, the maximum deviation of 360 "is coded in 8 octants of 450 by the 3 most significant bits coming from the module 25.

The rl - 1 bits of intermediate weight from the module 250 are used to address the means 310 and thus define a coarse value of the tangent of the desired deviation. The r2 least significant bits are used to refine the value of this tangent by interpolation as previously indicated.

One of the coils receives a current of intensity proportional to the tangent obtained, it will be called Ct thereafter. The other coil receives a current of reference of constant intensity equal to the current applied to the first coil for tan45 ".The current of reference will be called Cr by the Suite.It is necessary to alternate the sense of currents and the nature signals applied to the coil according to the following sequence 1 octant: the coil BI receives Cr in a first direction,
the coil B2 receives Ct in a first direction, 2nd octant: Bt receives Cr in the first direction,
B2 receives Ct in the second direction, 3rd octant: B1 receives Ct in the first direction,
B2 receives Cr in the second direction, 4th octant: 81 receives Ct in a second direction,
B2 receives Cr in the second direction, 5th octant: B1 receives Cr in the second direction,
B2 receives Ct in the second direction, 6th octant: B1 receives Cr in the second direction,
B2 receives Ct in the first direction, 7th octant:: B1 receives Ct in the second direction,
B2 receives Cr in the first sense, eighth octant: B1 receives Ct in the first sense,
B2 receives Cr in the first sense.

 Where appropriate, the functional operations corresponding to the modules 150, 210 in its hysteresis variant, 250 and 350 are performed by digital processing.

 Finally, it will be noted that the values contained in the memory means 310 may not correspond exactly to a sinus / cosine or tangent law, but be substantially offset with respect to these theoretical laws, if corrections are necessary, for example depending on characteristics of the logometer.

Claims (17)

 1. A logometer control device characterized in that it comprises means (100) capable of generating a digital signal representative of the parameter to be displayed, memory means (310) defining a coding of the digital signal on the basis of a pre-established law of sinus, cosine or tangent type, the memory means (320) being addressed by bits of intermediate weight of the digital signal, and interpolation means (350) adapted to correct the signal from the memory means (310) based on the least significant bits of the digital signal.  2. A logometer control device according to claim I, characterized in that the memory means (310) are selected from the group consisting of a ROM, a PAL or a logic combinatorics doors.  3. Logometer control device according to one of claims 1 or 2, characterized in that the memory means (310) contain 16 sine or cosine values sampled in steps of 90/16.  4. A logometer control device according to one of claims I to 3, characterized in that the preset law is of a sine / cosine type and the 2 most significant bits of the digital signal determine the active quadrant of the logometer.  5. A logometer control device according to claim 4, characterized in that the 2 most significant bits of the digital signal determine the direction of the current in the coils (B1, B2) of the logometer.  6. Logometer control device according to one of claims 1 to 5, characterized in that the preset law is of the sine / cosine type and the memory means (310) are associated with a pointing logic which for an address N defined by the intermediate weight bits of the digital signal, reads the value contained at the N address of the memory means (310) if the penultimate least significant bit of the digital signal has a first value, and reads the value contained at the address (2rl - N) if the penultimate bit of highest weight has a second value.  Logometer control device according to one of claims 1 to 6, characterized in that the preset law is of the sine / cosine type and the interpolation means (350) proceed as follows by calling R (N). the contents of the memory means (310) at the address (N), IP the decimal value corresponding to the r2 least significant bits from the module (250), Rcs a sine signal and Rcc a cosine signal calculated by the interpolation means (350), SQ (1) the weight bit the highest of the digital signal, SQ (O) the penultimate bit of the highest weight of this digital signal, and 2 the highest address of the memory means (310) a) if SQ (1) = O and SQ (O) = O for the first quadrant or Su (1) = I and SQ (O) = O for the third quadrant Rc = R (N) + IP (R (N + 1) - R (N)] / 2r1 and if N = 1, Rcc = 1 - 1P [1 - R (2r1 - 12r1, if N = 1, Rcc = R (2l - N) - IPR (2l - N) - R (2l - 1 - N) / 2l. Rcc = R (N) -RR (N + 1) -R (N) / 2r1. b) if SQ (1) = O and SQ (O) = 1 for the second quadrant or SQ (1) = 1 and SQ (O) = I for the fourth quadrant: rl if N = 1 Rcs = 1 - IP [1 - R (2 - if N = 1 Rcs = R (2 - N) - IP [R (2 R - N) - R (2 R 1 - 1 - N)] / 2  8. Logometer control device according to one of claims 1 or 2, characterized in that the preset law is of the tangent type and the 3 most significant bits of the digital signal determine the active octant of the log.  9. Device for controlling a two-coil logometer (B1, B2) according to claim 8, characterized in that it comprises an output logic module (450) which controls the current in the coils (B1, B2). such that one of the coils (B1) receives a current Ct of intensity proportional to the tangent obtained while the other coil (B2) receives a reference current Cr of constant intensity equal to the current applied to the first coil for tangent 45, the output logic module (450) alternating the direction of the currents and the nature of the signals applied to the coils according to the following sequence 1 octant: the coil B1 receives Cr in a first direction,  the coil B2 receives Ct in a first direction, 2nd octant: B1 receives Cr in the first direction,  B2 receives Ct in the second direction, 3rd octant: B1 receives Ct in the first direction,  B2 receives Cr in the second direction, 4th octant: B1 receives Ct in a second direction,  B2 receives Cr in the second sense, Octant se: BI receives Cr in the second sense,  B2 receives Ct in the second direction, 6th octant: Bl receives Cr in the second direction,  B2 receives Ct in the first direction, 7th octant: B1 receives Ct in the second direction,  B2 receives Cr in the first sense, eighth octant: B1 receives Ct in the first sense,  B2 receives Cr in the first sense.  10. A logometer control device according to one of claims 1 to 7, characterized in that the interpolation means (350) are followed by two up-down registers (410, 420) which are periodically loaded at the TRC period. , by sinus and cosine signals respectively from the interpolation means (350) and the two up-down registers (410, 42û) being decremented with a fixed frequency Fdec, the output of the registers changing level when the contents of the up-down registers (410, 420) reaches zero and serves to control the power stages (TO-T7) supplying the coils (BI, B2).  11. Logometer control device according to one of claims 1 to 2 and 8 or 9, characterized in that the interpolation means (350) are followed by a downward register (410) which is periodically loaded, to the period TRC, by a signal of the tangent type, coming from the interpolation means (350) and the up-down register (410) being decremented with a fixed frequency Fdec, the output of the register (410) changing level when the contents of the register up-counter reaches zero and serves to control the power stages (TO-T7) supplying the coils (B1, B2).  Logometer control device according to one of claims 10 or 11, characterized in that

 wherein M represents the number of bits of the loaded signals in each up-down register (410, 420).  13. A logometer control device according to claim 12, characterized in that 1 / TRc = 128 hz.  14. A logometer control device according to claim 10, characterized in that it further comprises an output module (450) formed of a combinatorial logic with doors which receives the signals from the up / down registers (410, 420). as well as the two most significant bits of the digital signal and controls the power stages (TO-T7) which feed the coils (B1, B2).  15. A logometer control device according to claim 11, characterized in that it further comprises an output logic module (450) formed of a combinatorial logic with doors which receives the signal coming from the up-down register (410) and the three strongest bits of the digital signal and controls the power stages (TO-T7) which feed the coils (B1, B2).  16. Logometer control device according to one of claims 14 or 15, characterized in that there is provided 8 power stages (TO-T7) for supplying the coils (BI, B2).  17. A logometer control device characterized in that the memory means (310) are preceded by a slope limiter module (250).