FR2635905A1 - METHOD AND CIRCUIT FOR TRANSMITTING RECORDING CONTROL SIGNALS - Google Patents

Abstract

Disclosed is a magnetic recording apparatus. It relates to an apparatus in which data, clock signals and validation signals are associated, with a mode signal, in an encoder 6 so that they are transmitted by a single line as a signal. single IC ODE to a recording circuit 3 placed in a drum with rotating heads. The single signal is decoded in a decoder 8 and a converter 9 so that it forms control signals of four different heads 1A to 1D via corresponding amplifiers 2A to 2D. The size of the drum with magnetic heads can be reduced. Application to video recorders.

Description

The present invention relates to a method for transmitting

  mission of recording control signals for application to a recording circuit of an apparatus

  magnetic recording system, in which the recording circuit

  recording, having an amplifier connected to a head

  magnet, is placed on the side of a drum with rotating heads.

  and a registration control circuit

  intended to control the operation of the recording circuit

  tration. The present invention can be applied for example

  to a video recorder equipped with a drum with rotating heads.

  In some magnetic-type recording-playback apparatus, for example a video recorder, having a

  drum with rotating heads, a recording amplifier

  and a sense amplifier or the like are

  placed within the rotating head drum, otherwise the frequency response or the transmission efficiency of a rotary transformer placed between the magnetic head disposed in the rotating head drum

  and the processing circuit for recording or processing

  reading on the substrate side 6 could be reduced. In the magnetic recording-playback apparatus

  wherein the recording amplifier, the amplifier

  Readout and the like are placed in the rotating head drum, various control signals are transmitted, for example by means of a slip ring device or an optical transmission system, for controlling the switching. of the recording head in the drum with rotating heads, the command by all or

  nothing of the recording current and the switching control

  the reading head from the outside of the drum to

rotating heads.

  By way of illustration, FIG. 1 represents a system

  recording system for a four-channel digital video recorder, wherein a recording circuit 103 having recording amplifiers of the four

  102A, 102B, 102C and 102D is placed on the drum side.

  rotating heads. These recording amplifiers amplify the REC.AH, REC.BCH, REC.CCH and REC.DCH recording signals of the respective channels, transmitted from the outside by a rotary transformer 100 in the form of four channel recording signals. constituting REC data, and they transmit the amplified signals to

  recording heads 10a, 10b, 100c and 101d corresponding to

  laying on the respective channels. In such a system of registration

  recording, a digital-to-analog converter 104 (N / A)

  four channels is arranged in a recording circuit.

  103 forms the gain control data CNT.ACH, CNT.BCH, CNT.CCH and CNT.DCH, allowing gain adjustment in the channels of the recording amplifiers. 102A, 102B, 102C and 102D. In this recording system, the gain adjustment data CNT.ACH, CNT.BCH, CNT.C CH and CNT.DCH as well as the data represented by the data

  series "Data N / A", the synchronization clock

  "N / A clock" and the "Valid N / A" enable enable signals are transmitted from outside the rotating head drum to the side of the drum by transmission lines 105, 106, 107 having a device 108 with slip rings, for controlling the D / A converter 104 in accordance with the timing clock signals and the enable control signals, so that gain control data CNT.ACH, CNT.BcH, CNT.CcH and CNT.DCH are formed from the D / A data in the converter 104, so that the gain adjustment of each of the amplifiers 102A, 102B, 102C and 102D is ensured and the recording adjustment can be ensured for each

four channels.

  In general, in a serial data transmission system, when the serial data is received on the receiving side by a D flip-flop or a data log.

  synchronized clock signals on these data.

  series or control signals indicating the start and end of the serial data are required. Thus, line 105 of data transmission series N / A, the line

  106 for transmitting the synchronization clock signals

  tion and the transmission line 107 of the validation control signals are placed in parallel, as

  in the aforementioned registration system.

  In an "autodial" type transmission system in which clock signals are superimposed on the transmitted serial data as shown in FIG.

  2, a clock generator 110 formed by a vertical loop

  phase retting (PLL) consisting of a phase-shift comparator 111 and a voltage-controlled oscillator 112 is arranged on the receiving side and the phase of the serial data edge transmitted from the transmission side by a transmission line 120 is compared to the oscillation phase of the oscillator 112 in the comparator 111 so that the oscillation frequency of the oscillator 112

  be controlled and that the synchronizing clock signals

  are formed from the series data, at the level of

  of the clock generator 110. These clock signals of syn-

  are transmitted to a clock input terminal of the flip-flop D 115 on the receive side while the serial data is transmitted to an input terminal of

data from the D 115 flip-flop.

  Heretofore, in a magnetic recording apparatus in which a recording circuit having an amplifier connected to the magnetic head is placed on the drum-rotating head side, when the recording control signals which control the recording circuit is represented by the serial data and data validation signals indicating data start and end points of the serial data, and when the serial data and these data validation signals are serially transmitted simultaneously with the synchronization clock signals, the serial data,

  the validation signals and the clock signals of syn-

  Chronization are transmitted from outside the drum

  to the drum with rotating heads by lines

  This is because, because of the use of slip ring devices as transmission lines, it is necessary to use multi-stage slip rings which prevent a reduction in the size of the magnetic recording apparatus. . Multi-stage slip ring devices are also inconvenient because the torque of the drive motor of the rotating drum is adversely affected and the ratio of

  signal-on-noise is also reduced by the action of

occasional lions of the tree.

  Although the number of stages of slip ring devices can be reduced by transmitting

  series data representing the control signals of

  together with the clock signals of syn-

  In this case, it is necessary to use a phase locked loop type clock generator as previously described on the receiving side or the drum, so that a space is required.

  important for this clock generator.

  The subject of the invention is the reduction of the size

  and increasing the reliability of the recording apparatus

  magnetic circuit in which a recording circuit having an amplifier connected to the magnetic head is

placed on the drum side.

  The invention also relates to the simplification of a transmission system for transmitting signals

  recording control from outside a drum.

  bour to a recording circuit placed on the side of the drum.

  The invention also relates to a method for transmitting

  recording command signals by which control signals of the recording circuit placed on the drum side, according to various modes of operation, can be transmitted by a single transmission line,

  at the same time as the synchronization clock signals.

  The invention also relates to a recording control circuit by which complex operations of

  control of the recording circuit placed on the drum side

  bour can be made from outside the drum,

  according to various modes of operation.

  Other features and advantages of the invention

  will be better understood by reading the description

  which will follow examples of embodiment, with reference to the accompanying drawings in which: FIG. 1 is a block diagram representing

  the layout of a magnetic recording system

  classic toscope; FIG. 2 is a block diagram representing

  provision of the receiving side of a transmission system

  serial data mission; FIG. 3 is a block diagram representing

  the arrangement of the registration system of a

toscope according to the invention;

  FIG. 4 is a diagrammatic plan view

  sensing the arrangement of each head of the rotating drum of the recording system;

  FIG. 5 is a diagrammatic plan view

  sensing the format of the tracks of the DVR; FIG. 6 is a diagram of a circuit representing an exemplary encoder arrangement for carrying out the method according to the invention; Fig. 7 is a timing diagram illustrating the operation of the encoder; Fig. 8 is a diagram of a circuit showing the arrangement of an exemplary decoder associated with the encoder; and FIG. 9 is a timing chart illustrating the

operation of the decoder.

  The block diagram of FIG. 3 represents the arrangement of the recording system of a video recorder

  digital four-channel according to the invention.

  In the recording system represented by the diagram of FIG. 3, a recording circuit 3 having amplifiers 2A, 2B, 2C and 2D recording

  four channels connected respectively to recording heads

  1A, 1B, 1C and 1D are arranged in a rotating head drum 4, provided with amplifiers 2A to 2D as shown in FIG. 4, and recording data of the four REC channels are transmitted to each of the amplifiers 2A. to 2D by a rotary transformer 5. The recording circuit 3 has a decoder 8 which decodes the serial control signals transmitted by a transmission system 7 from an encoder 6 placed outside the drum 4 with rotating heads , and a four-channel digital-to-analog converter (D / A) 9 for forming

  gain control CNT.AcH, CNT.BcH, CNT.CCH and CNT.DH

  setting the gain of the respective amplifier 2A to 2D of the respective channel according to the decoded signal of the

decoder 8.

  The digital video recorder according to the invention is a

  digital video recorder in DII format and having a

  drum machine with rotating heads comprising a drum 4 which has a channel A recording head 2A and a head

  2B recording channel B, and a recording head 2C

  C channel and a 2D D channel recording head, with an angular interval of 1800 between the heads, and

  a head 10A for reading channel A and a head 0lB for reading

  channel B, and a C channel read head 10C and a D channel read head 10D, at

   as shown in Figure 4, the recording data

  channels, ie the video data V0, V1, V2 and V3 and the audio data A0, A1, A2 and A3, are recorded in azimuth on the recording tracks A, B, C, D of the four channels on the magnetic tape 11, by the recording heads 1A to 1D, with the format shown in Figure 5, while the signals of the four channels are reproduced from the tracks A to D by

the heads 10A to 10D.

  In the method of transmitting the recording control signals according to the invention, implementing the aforementioned recording system, the N / A data indicating the gain control signals CNT.ACH to CNT.DCH.

  gain control of the amplifiers 2A to 2D of the

  channels, the N / A validation signals indicating the

  beginning and end of N / A serial data, the hor-

  N / A synchronization box corresponding to the serial data and the transmission mode signals MD, indicating the beginning and the end of the transmission, arrive at the

  encoder 6 as control signals of the function

  recording circuit 3, and the correct impulse

  in the N / A clock is controlled by the D / A enable signals to the encoder 6 and receives the D / A serial data, along with the MD mode signal, indicating the beginning and the end of the D / A signal. transmission, is added to the serial data N / A so that ICODE serial control data is formed, which data is transmitted by the transmission circuit 7 to the decoder 8 placed in the recording circuit 3 on the drum side 5 with rotating heads .

  The encoder 6 intended for implementing the invention

  tion is realized with the layout of the circuit shown

for example in Figure 6.

  The encoder 6 represented by the circuit of FIG. 6 comprises a first and a second D flip-flop 20, 21, three delay circuits 22, 23 and 24, three exclusive OR circuits 25, 26 and 27, an AND circuit 28 with three inputs and

an OR circuit 29 with two inputs.

  The first D flip-flop 20 of the encoder 6 is made and arranged in such a way that the series data representative of the control signals to be transmitted, for example the N / A series data representing the control signals of FIG.

  gain CNT.AcH to CNT.DCH gain adjustment of amplifiers

  recording devices 2A to 2D reach its

  Throughput of data via a signal input terminal 15, the serial data synchronization clock signals are transmitted to the clock input terminal through the clock input terminal 16 and the output signal Q is directly transmitted to input terminals of the first

  and the third exclusive-OR circuit 25, 27, being trans-

  put, via the first delay circuit 22, to

  the other input terminal of the first exclusive OR circuit 25.

  The output signal of the first exclusive OR circuit 25 par-

  to a first input terminal of the AND circuit 28. The second D flip-flop 21 is constructed and arranged so that the data enable signal representing the start and end points of serial data reaches the input terminal 17. signal at its data input terminal while the synchronization clock signals of the serial data are transmitted by the terminal 16 to its clock input terminal, the signal of its output Q arriving at the

  second input terminal of the AND circuit 28.

  The synchronization clock signals of the serial data are transmitted by the signal input terminal 16 to the clock input terminals of the flip-flops 20, 21 and are transmitted to a first input terminal of the second exclusive OR circuit. directly and to the other input terminal of the second exclusive OR circuit 26 via the second delay circuit 23. The output signal of the second circuit

  Exclusive OR 26 reaches the AND circuit 28 via

  of the third delay circuit 24.

  The AND circuit 28 with three inputs is such that its first and third input terminals are inverting terminals, and it receives the inverted signal of the first OR circuit 25, the inverted signal of the Q output of the second D flip-flop. 21, and the output signal of the exclusive OR circuit 26, delayed by the third circuit 24, and it transmits its output signal to the other input terminal of the

third exclusive OR circuit 27.

  The output signal of the third exclusive-OR circuit 27 reaches a first input terminal of the two-input OR circuit 29. This OR circuit 29 is made and arranged

  transmission mode MD signals indicate

  the beginning and the end of the data transmission, reach via the signal input terminal 18 to the other input terminal, and that the output signal of the third exclusive OR circuit 27 and the signal MD are OR and transmitted to terminal 30

  signal output in the form of transmission data.

  mission. In the aforementioned encoder 6, when the serial data

  N / A such as 0011010001110, indicating the communication signal

  to be transmitted, synchronize with the synchronization clock signals during the time interval TEN between the data start point and

  the end point of data indicated by the validity signal

  1, the edge pulses of the ED data, each indicating a change point of the serial data, are formed in the first exclusive OR circuit 25 in the form of a serial data signal transmitted by the flip-flop D 20 at the output Q and an output data signal Q DL which has been delayed by the first delay circuit 22. On the other hand, in the second exclusive-OR circuit 26, the pulses of the flanks ED clock, each representing a side of the synchronization clock signal, are formed by

  the exclusive OR operation of the synchronization clock signal

  tion and the same signal delayed by the second cir-

  Delayed cooking 23. The three input AND circuit 28 transmits clock side signals ED, excluding the clock sides of the aforementioned sidewall portions produced.

  during the period TEN represented by the validity signals

  data generation, by exclusive OR processing of the output signal of the circuit 25, i.e. an inverted pulse

  ED data flank, the output signal of the second cir-

  cooked exclusive OR 26, that is to say the aforementioned pulse of the clock edge ED, delayed by the third delay circuit 24, and the inverted signal of the output Q of the

  second latch 21, that is to say the aforementioned signal of validity

  reverse and delayed data generation of a clock pulse.

  synchronization box. The third exclusive OR circuit 27 forms a signal which represents a superposition of the ED clock signal produced in the AND circuit 28.

  by processing the serial data introduced by

  the first latch 20. The OR circuit 29 forms a signal which represents the sum of the mode signal of

  MD transmission with the PSCR start impulse and the impulse

  end of transmission PEND and the signal produced in the third OR exclusive circuit 27, and transmits the sum signal to its output terminal 30 in form

  ICODE serial control signals.

  In the exemplary embodiment, eight initial PFR pulses are used in the transmission mode signal MD for each of the

transmitted data N / A.

  FIG. 8 represents an exemplary arrangement of the decoder 8 incorporated in the recording circuit 3 on the side of the drum 5 and to which the ICODE series control signals formed at the level of the encoder 6 are transmitted by the only

transmission circuit 7.

  The decoder 8 shown in FIG. 8 has a cir-

  cooked buffer 32 to which control signals are transmitted

  ICODE series via the input terminal 31.

  The ICODE series control signals undergo a phase inversion in the buffer circuit 32 before being transmitted by a low-pass filter 33 to the first and second circuits

And 35 and 36.

  The low-pass filter 33 is formed of a resistor R, a capacitor C and a buffer circuit B and it transmits an output signal which is devoid of the signals of the clock sides ED or the like contained in the signals ICODE control unit, at an inverting input terminal of the first AND circuit 35, at a non-inverting input terminal

  of the second AND circuit 36 and a data latch 60.

  The ICODE series control signals having undergone the phase inversion in the buffer circuit 32 undergo a new phase inversion in the buffer circuit 34 before transmission to a non-inverting input terminal of the first AND circuit 35 and to a terminal of inversion input

of the second AND circuit 36.

  The first AND circuit 35 extracts the signals from the ED clock flanks or the like existing during the period in which the ICOD series control signals are at the low logic level, and an output signal obtained by an AND operation of the DC output signal. pass filter

  33 and ICODE series control signals and it transmits

  puts the signal which has undergone the AND operation to a terminal of

  clock of a counter 41 of a circuit 40 for detecting

  mode and at a clock input terminal of a first flip-flop D 51 of a clock demodulation circuit 50, with transmission of the aforementioned signal having undergone the processing AND to an erase input terminal of the first D latch D 43 of the clock detecting circuit 40 and a first input terminal of a NAND circuit 53 of the clock demodulation circuit 50 via

an inverter 37.

  The second AND circuit 36 extracts clock edge signals ED or the like existing during the period in which the ICODE series control signals are at the high logic level, in the form of the signal obtained by processing AND the filter output signal. 33 and the ICODE series control signal, and transmits this AND signal to a clock input terminal of a second D flip-flop

  52 of the clock demodulation circuit 50, with transmission

  the output of the processing output signal ET to a terminal of

  erase of the first flip-flop D 51 of the circuit 50

  demodulation, via an inverter 38.

  The mode detection circuit 40 has a decoder 42 for decoding the number signal of the counter 41 which is set to zero by the AND signal obtained by processing in the second AND circuit 36 so that the output signals of the first AND circuit 35 be counted. The mode detection circuit 40 has an arrangement and a construction such that the decoded output signal Q9 of the decoder 42 which goes to a high level when the number of the counter 41 is equal to 9 is transmitted to a decoding input terminal of the first flip-flop D 43, and that a decoded output signal Q1 of the decoder 42 which passes to a high level

  when the number of the counter 41 is equal to one, is trans-

  set to the data input terminal of the second flip-flop D 44. The output signal of the low-pass filter 33 is transmitted by an inverter 45 to the clock input terminals.

flip-flops D 43 and 44.

  The first D flip-flop 43 retains a decoded output signal Q9 from the decoder 42 whenever the counter 41 has nine pulses comprising eight start pulses PFTR 'transmitted in the form of the transmission mode signal MD for each data transmitted, and a pulse of ED flank taken from the output of the low-pass filter 33, at the time tf of the falling edge of the output signal of the low-pass filter 33, and transmits a signal at its output Q. passing to a low level until the flip-flop 43 is restored by the output signal of the first AND circuit 45, reaching an erase input terminal

of the third flip-flop D 46.

  The second D flip-flop 45 retains a decoded high-level output signal QI which is transmitted by the decoder 42 at the tE time of the falling edge of the transmitted PEND final pulse for each data transmitted as the transmission mode signal MD, and transmits the output signal Q at the clock input terminal of the third

flip-flop D 46.

  The third D flip-flop 46 constantly receives data of high logic level at its data input terminal and is reset by the output signal Q of the first flip-flop D 43 at the time ts of the falling edge of the signal. output of the low-pass filter 33, so that the

  signal from the Q output which passes to a unique high level

  during the TSE period which ends when the high logic level data are stored at time tE of the falling edge of the final pulse TEND under the control of the output signal Q of the second flip-flop D 44, is transmitted to the data entry terminal of the

  fourth latch D 47 and to the other input terminal of the circuit

  N-cook 53 of the clock demodulation circuit 50,

  with transmission of the aforementioned Q output signal from the base

  Fig. 46 at signal output terminal 49 as N / A data enable signals.

  The fourth flip-flop D 47 receives, at its terminal

  clock, the aforementioned ICODE series control signals from the buffer circuit 34 and retains the output signal Q of the third D flip-flop 46 at the time of the falling edge of the ICODE series control signal so that the

  output signal Q reaches the respective terminals of

  erase of the third flip-flop 56 of the demodulation circuit 50 and a flip-flop D 61 of the circuit 60 of

data retention.

  The first flip-flop D 51 of the circuit 50 of demodulation

  The clock terminal has its output terminal Q connected to its data input terminal and provides a two-fold frequency division of the signal transmitted by the first AND circuit 35 to its clock input terminal when the D flip-flop 51 is reset by the output signal of the second OR circuit 36. The second D flip-flop 52 is connected by its output Q to a terminal

  data entry and receives, at its input terminal of reten-

  the output signal of the NAND circuit 53. The flip-flop 52 provides a halving of the frequency of the output signal of the second AND circuit 36 transmitted to its

  clock input terminal, when the flip-flop 52 is

  by the output signal of the first AND circuit 35 and by the output signal Q of the third flip-flop D 53 of the mode detection circuit 40, these signals being

  transmitted to the entrance terminal of recovery of the

  52 and constitute the output signal of the NO circuit.

  ET 53, receiving these output signals.

  The half-output signals of the outputs Q of the flip-flops 51 and 52 reach via an OR circuit 54 to a first input terminal of the AND circuit 57 and to a clock input terminal of the flip-flop D 61 of the circuit 60. of data storage, and they are simultaneously transmitted by the OR circuit 54 and the inverter circuit 55 to a terminal

  clock input of the third D flip-flop 56. The third D flip-flop 56 constantly receives logic level data

  raised to its first data input Do and its first data output terminal Q0 is connected to its second data input terminal D1. The third flip-flop 56 transmits a gate control signal that goes to a high logic level whenever two rising edges of the clock pulses from the OR circuit 54 through the inverter 55 are counted from the second data output terminal Q1 and reaching the input terminals of the AND circuit 57, so that said AND gate 57 transmits a number of synchronization clock pulses which coincide with the number of transmission data at the terminal of

signal output 59.

  The flip-flop D 61 of the circuit 60 has its first data output terminal Q0 which is connected to its second data input terminal D1 and retains twice the data signal.

  output of the low-pass filter 33 which is transmitted to its first

  first data input terminal D with the clock pulses transmitted by the OR circuit 54 of the clock demodulation circuit 50 so that the output signals are shifted by one clock pulse backwards, in coincidence with output control data which corresponds to the synchronization clock pulses demodulated by the demodulation circuit 50, to the terminal of

signal output 65.

  The aforesaid digital-to-analog converter 9, receiving the control data, the data validation signals and the synchronization clock signals obtained by decoding the ICODE series control signals

  from the encoder 6, by the decoder 8, executes a

  digital-to-analog version of the control data, according to the data enable signals and the timing clock signals so that it forms the gain adjustment signals CNT.A CH to CNT.DCH, for each of the channels, With the gain control of the amplifiers 2A to 2D recording, for each channel, with its gain control signals CNT.ACH to CNT.DCH 'In the described DVR, the gain adjustment signals CNT.ACH to CNT. DCH corresponding to the above-mentioned ICODE series command signals transmitted by the

  encoder 6, are formed in the digital converter-

  analog 9 placed in the recording circuit 3 which is itself arranged in the drum 4 with rotating heads, so that the gain adjustment of amplifiers 2A to 2D

  recording is set in each channel, with

  variable signal of the recording current for each channel using the above-mentioned ICODE series control signals transmitted from outside to the drum 4. Data can be transmitted in a similar manner to provide a write setting operation independent

  recording data for each channel, that is,

  video data V0 to V3 and audio-visual data

  quences A0 to A3, setting the decoder in each of the various modes so that a setting operation can be performed, for example a recording

editing with insertion.

  Although the aforesaid operation of gain adjustment of the recording amplifier 2A to 2D by the converter

  9 has been described for illustrative purposes only, it is pos-

  to designate a reading mode, a recording mode,

  or a test mode to check the operation of the record-playback mode and the execution of various

  control operations by changing the number of

  initial TFTR statements as an MD mode control signal to the serial transmission data, indicating the

beginning of the transmission.

  On the other hand, when a read amplification circuit is placed in the rotating head drum in addition to the recording circuit, the above method can be used for adjusting the sense amplifier circuit in addition to the sense circuit. recording, so that the channel of

reading is selected.

  It should be noted from the foregoing description that

  The invention relates to a method for transmitting recording control signals by which the control signals of the operation of the recording circuit, placed on the side of the drum with rotating heads of the apparatus.

  magnetic recording and playback and having the amplification

  connected to the magnetic head, are represented by serial data and data validation signals.

  representative of the starting point and the end point of the

  series, the flank pulse of the sync clock

  The serial data transmission is transmitted by the data validation signals and is appended to the serial data, and the recording control signals are serially transmitted from the outside of the drum to the side of the drum as serial control signals. comprising the serial transmission data to which transmission mode signals representative of the beginning and the end of the transmission are appended. Thus, the recording control signals can be transmitted from outside the drum by a single transmission line together with the timing clock signals or the like and the recording control signal transmission circuit is simplified. Furthermore, in the recording control circuit according to the invention, the control signals of the recording circuit are formed by a corresponding device according to the signals of

  data validation and sync clock signals

transmitted from the head drum side at the same time as the serial transmission data, representing the recording control signals in the form of

  serial control data which controls the function

  of the recording circuit, so that it is possible to transmit the serial control signals

  from the outside of the drum by a single line of trans-

  mission with synchronization clock signals, when performing a complex command operation in

  function of various modes of operation.

  Thus, the invention permits an increase in reliability and a reduction in the size of the magnetic recording apparatus in which the recording circuit, provided with an amplifier connected to the magnetic head, is placed on the side of the magnetic recording apparatus. of the drum, a complex operation of controlling the recording circuit being

however permitted.

  Of course, various modifications can be made by those skilled in the art to the methods and transmission circuits which have just been described as non-limiting examples without departing from the scope of the invention.

Claims (4)

  1. Method of transmitting control signals   registration to a registration circuit of an   the magnetic recording circuit, the recording circuit   having a connected amplifier & a magnetic head   placed on the side of a drum with magnetic heads, rised in that it includes:   the indication of the recording control signals   serial data signals and data enable signals representative of the beginning and the end of the serial data, the transmission of the edge pulses of the serial data synchronization clock signals under the control of the data validation signals and the annexation of the pulses of the flanks thus formed to the series data and furthermore the annexation of mode signals of   transmission, indicating the beginning and the end of the transmission   serial data so that serial control signals are formed, and the serial transmission of the recording control signals as serial control signals from outside the rotary head drum to   the side of the drum with rotating heads.   2. A control circuit of a recording circuit of a magnetic recording apparatus in which the recording circuit, provided with an amplifier connected to a magnetic head, is placed on the side of the rotating head drum, characterized in that it comprises: a serial control signal generating device (20-28) placed outside the head drum   magnetic signals and transmitting control signals of   in the form of serial control signals, and in   recording control signals which control   The recording circuitry is indicated by serial data signals and data enable signals representing the start of the data and the end of the serial data, with pulses of the flanks of the synchronization clock signals associated with the serial data being transmitted. under the control of the data validation signals and being appended to the serial data, transmission mode signals indicating the beginning and the end of the transmission being further appended to the serial data, a serial control signal transmission device of the device generator of rotary drum drum series control signals, and a control signal forming device (33-60) on the rotating head drum side and forming the recording control signals for the recording circuit from the serial control signals transmitted by the transmission device of signals.   3. Circuit according to claim 2, characterized in that the serial control signal generating device comprises: a device (20, 21) for detecting the flanks of the serial data, a gate device (22-26) for transmitting   the pulses of the flanks of the clock signals of synchro-   under the control of edge detection pulses and data enable signals, and an exclusive OR gate (27) receiving   gate device output and serial data.   4. Circuit according to claim 2, characterized in   what the device intended to form the signals of com- Mande comprises:   a low-pass filter (33) for removing the   of the sidewall pulses appended to the series control signals, a first and a second gate device (35-38) controlled by the output signal of the low-pass filter, with opposite phases, so that the sidewall pulses appended to the signals serial control means, a device (40) for forming data enable signals from each of the edge pulses obtained by the first and second gate devices and the output signal of the low-pass filter, the signals data validation means indicating the start and the end of the series data representative of the recording control signals, a device (50) for demodulating the synchronization clock signals for the serial data, from each edge pulse. obtained using the first and the second door device and from the   clock validation signals obtained with the aid of the   the training of data validation signals, and   a data storage device (60) of   synchronized clock data from the output of the low-pass filter, data enable signals obtained from the   data validation, and sync clock signals   obtained using the demodulation device clock.