FR2633777A1 - EPROM cell utilising a trench insulation and its method of manufacture - Google Patents
EPROM cell utilising a trench insulation and its method of manufacture Download PDFInfo
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- FR2633777A1 FR2633777A1 FR8908469A FR8908469A FR2633777A1 FR 2633777 A1 FR2633777 A1 FR 2633777A1 FR 8908469 A FR8908469 A FR 8908469A FR 8908469 A FR8908469 A FR 8908469A FR 2633777 A1 FR2633777 A1 FR 2633777A1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title claims abstract description 5
- 238000009413 insulation Methods 0.000 title abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- 239000010703 silicon Substances 0.000 claims abstract description 3
- 238000002955 isolation Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 239000002784 hot electron Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
Description
Cellule EPROM utilisant un isolement de tranchée et son procédé de fabrication.EPROM cell using trench isolation and its manufacturing process.
La présente invention a trait à une cellule
EPROM utilisant un isolement de tranchée et à son procédé de fabrication, et plus particulièrement à une cellule EPROM possédant une couche polycristalline I (ci-après appelée "poly") en tant que grille flottante et possédant également une zone de diffusion de type N qui est reliée à une couche poly-II par l'intermédiaire d'un contact enterré en tant que grille de commande.The present invention relates to a cell
EPROM using trench isolation and its manufacturing process, and more particularly to an EPROM cell having a polycrystalline layer I (hereinafter called "poly") as a floating gate and also having an N-type diffusion zone which is connected to a poly-II layer via a buried contact as a control grid.
La cellule EPROM peut être utilisêeen tant que cellule de mémoire utilisant deux états ; l'un est l'état 0 dans lequel des électrons sont accumulés dans une grille flottante en programmant la cellule, l'autre est l'état 1 dans lequel des électrons sont libérés dans une grille flottante en effaçant la cellule en utilisant de la lumière ultraviolette. D2 façon détail lee, pour programmer la cellule, des'électrons chauds engendrés depuis la zone de drain d'un transistor utilisé en tant que cellule de mémoire sont injectés dans une grille flottante qui est introduite dans une couche d'oxyde (l'injection est commandée par une grille de commande), et pour effacer la cellule, des électrons sont libérés à partir de la grille flottante par irradiation à la lumière ultraviolette à travers la fenêtre sur la partie supérieure du module. The EPROM cell can be used as a memory cell using two states; one is state 0 in which electrons are accumulated in a floating grid by programming the cell, the other is state 1 in which electrons are released in a floating grid by erasing the cell using light ultraviolet. D2 in detail, to program the cell, hot electrons generated from the drain area of a transistor used as a memory cell are injected into a floating gate which is introduced into an oxide layer (the injection is controlled by a control grid), and to clear the cell, electrons are released from the floating grid by irradiation with ultraviolet light through the window on the top of the module.
Une cellule EPROM classique, qui est conçue pour avoir les fonctions précitées, est constituée de couches poly doubles comme représenté sur la Figure 1. A conventional EPROM cell, which is designed to have the aforementioned functions, consists of poly double layers as shown in Figure 1.
Une disposition d'une cellule classique est représentée sur la Figure 2, et les vues en coupe selon les lignes a-a' et b-b' sont représentées sur la Figure 1(A) et la Figure 1XB) respectivement. Dans cette-structure, la première couche poly 1 et la seconde couche poly 2 sont utilisées en tant que grille flottante et en tant que grille de commande respectivement, et les cellules sont divisées par un oxyde de champ 5 qui est habituellement déposé entre les deux cellules. Egalement une source 6 et un drain 7 sont représentés sur la Figure 1(B). Par conséquent, la fiabilité de la cellule classique dépend de la qualité et de l'épaisseur de la première couche d'oxyde de grille 3 et de la couche d'oxyde interpoly 4 sur la Figure 1.An arrangement of a conventional cell is shown in Figure 2, and the sectional views along lines a-a 'and b-b' are shown in Figure 1 (A) and Figure 1XB) respectively. In this structure, the first poly 1 layer and the second poly 2 layer are used as a floating grid and as a control grid respectively, and the cells are divided by a field oxide 5 which is usually deposited between the two. cells. Also a source 6 and a drain 7 are shown in Figure 1 (B). Consequently, the reliability of the conventional cell depends on the quality and the thickness of the first gate oxide layer 3 and of the interpoly oxide layer 4 in FIG. 1.
Généralement, deux états sont utilisés dans une cellule EPROM ; le premier état présente une tension de seuil faible (VT) avant programmation de la cellule, et le second état présente une tension de seuil élevée (VT) ensuite. Afin de programmer la cellule, une tension élevée est appliquée à la grille de commande 2 et à l'électrode de drain 7, de sorte que des électrons sont accumulés dans la grille flottante 1 par injection par avalanche d'électrons chauds autour du drain canalisé de la cellule. Lorsque des électrons sont accumulés de cette manière, la cellule est programmée, et à cet instant, la tension de seuil de la cellule devient élevée. Ainsi il existe une différence de tension de seuil entre l'avant-programmation et l'apres-programma- tion, et cette différence de tension permet à la cellule d'être utilisée en tant que cellule de mémoire. Generally, two states are used in an EPROM cell; the first state has a low threshold voltage (VT) before programming the cell, and the second state has a high threshold voltage (VT) afterwards. In order to program the cell, a high voltage is applied to the control grid 2 and to the drain electrode 7, so that electrons are accumulated in the floating grid 1 by injection by avalanche of hot electrons around the channeled drain of the cell. When electrons are accumulated in this way, the cell is programmed, and at this time, the threshold voltage of the cell becomes high. Thus there is a threshold voltage difference between the pre-programming and the post-programming, and this voltage difference allows the cell to be used as a memory cell.
Dans la cellule EPROM précitée, il est important de commander la croissance d'un oxyde interpoly de bonne qualité 4 du fait que l'épaisseur de l'oxyde interpoly est liée à la capacitance de la première couche poly et de la seconde couche poly. Egalement, la croissance d'oxyde interpoly détermine simultanément la croissance du second oxyde de grille. Par conséquent, il est difficile de commander la croissance de l'oxydeinterpoly 4. Et la fiabilité de la cellule est réduite par le courant de fuite généré depuis le bord de la première couche poly vers la seconde couche poly. In the above-mentioned EPROM cell, it is important to control the growth of a good quality interpoly oxide 4 because the thickness of the interpoly oxide is linked to the capacitance of the first poly layer and of the second poly layer. Also, the growth of interpoly oxide simultaneously determines the growth of the second gate oxide. Therefore, it is difficult to control the growth of the oxide interpoly 4. And the reliability of the cell is reduced by the leakage current generated from the edge of the first poly layer to the second poly layer.
Le but de la présente invention est de résoudre les problèmes précités et de proposer une cellule
EPROM de fiabilité élevée et son procédé de fabrication.The aim of the present invention is to solve the aforementioned problems and to propose a cell
High reliability EPROM and its manufacturing process.
Les vues en coupe de la cellule EPROM de la présente invention sont représentées sur la Figure 3. The sectional views of the EPROM cell of the present invention are shown in Figure 3.
En référence à la Figure 3, cette nouvelle EPROM divisée par un oxyde de champ 5 est caractérisée par une grille de commande 11 dans la zone de canal divisée par un isolement de tranchée 10 et est également caractérisée par une grille flottante 13 constituée par une unique couche poly-I réalisée sur un premier oxyde de grille et un oxyde interpoly 12. Une cellule EPROM de haute fiabilité est fabriquée en utilisant l'isolement de tranchée en faisant croître simultanément le premier oxyde de grille et l'oxyde interpoly lors d'une étape de procédé et en faisant croître également l'oxyde épais entre la couche poly-I et la couche poly-II.Referring to Figure 3, this new EPROM divided by a field oxide 5 is characterized by a control grid 11 in the channel area divided by a trench isolation 10 and is also characterized by a floating grid 13 consisting of a single poly-I layer produced on a first gate oxide and an interpoly 12 oxide. A high-reliability EPROM cell is manufactured using trench isolation by simultaneously growing the first gate oxide and the interpoly oxide during a process step and also growing the thick oxide between the poly-I layer and the poly-II layer.
Comme représenté sur la Figure 3, un silicium de type N fortement dopé est utilisé en tant que grille de commande 11 et une couche poly-I est utilisée en tant que grille flottante 13. Et la zone de tranchée est remplie d'oxyde épais et est transformée en isolateur de tranchée. Par conséquent, la zone de canal 14 de la cellule est complètement isolée de la grille de commande et d'un oxyde mince 12 qui est utilisé en tant que premier oxyde de grille et est également réalié en tant qu'oxyde interpoly. Sur l'oxyde mince est déposée la couche poly-I utilisée en tant que grille flottante. As shown in Figure 3, heavily doped N-type silicon is used as the control gate 11 and a poly-I layer is used as the floating gate 13. And the trench area is filled with thick oxide and is transformed into a trench isolator. Therefore, the channel area 14 of the cell is completely isolated from the control gate and a thin oxide 12 which is used as the first gate oxide and is also made up as the interpoly oxide. On the thin oxide is deposited the poly-I layer used as a floating grid.
Sur la couche poly-I, l'oxyde épais est déposé et un contact enterré 20 est également réalisé dans une partie de la grille de commande pour constituer une ligne de transmission de mots appliquée à une cellule de mémoire. Une cellule est réalisée en déposant une couche poly-II 22 sur ledit oxyde épais.On the poly-I layer, the thick oxide is deposited and a buried contact 20 is also made in a part of the control grid to constitute a word transmission line applied to a memory cell. A cell is produced by depositing a poly-II layer 22 on said thick oxide.
Les Figures 1(A) (B) représentent des coupes à grande échelle d'une cellule EPROM classique. Figures 1 (A) (B) show large-scale sections of a conventional EPROM cell.
La Figure 2 représente une vue en plan à grande échelle d'une cellule EPROM classique. Figure 2 shows a large-scale plan view of a conventional EPROM cell.
Les Figures 3 (A) (B) représentent des vues en coupe à grande échelle de la cellule EPROM selon la présente invention. Figures 3 (A) (B) show large-scale sectional views of the EPROM cell according to the present invention.
La Figure 4 représente une vue en plan à grande échelle de la cellule EPROM selon l'invention. Figure 4 shows a large-scale plan view of the EPROM cell according to the invention.
Les Figures 5 (A)-5(G) représentent des vues en coupe à grande échelle qui illustrent les étapes de fabrication de la cellule EPROM selon la présente invention. Figures 5 (A) -5 (G) show large-scale sectional views which illustrate the steps of manufacturing the EPROM cell according to the present invention.
Les Figures 1(A) (B) sont des vues en coupe de la cellule de la Figure 2, prises selon les lignes a-a , b-b respectivement. Figures 1 (A) (B) are sectional views of the cell of Figure 2, taken along lines a-a, b-b respectively.
Les Figures 3(A) (B) sont des vues en coupe de la cellule de la Figure 4, prises selonsles lignes a-a, b-b respectivement. Figures 3 (A) (B) are sectional views of the cell of Figure 4, taken according to lines a-a, b-b respectively.
Pour programmer la cellule EPROM de la présente invention, une tension élevée, de préférence d'environ 12 V, est appliquée à la grille de commande 11 constituée par une couche poly-II reliée à la zone de diffusion de type N par l'intermédiaire du contact enterré, et une tension élevée est également appliquée à un drain 7 sur la Figure 3 de sorte que des électrons sont accumulés sur la grille flottante 13 par injection par avalanche des électrons chauds autour du drain canalisé de la cellule. Par conséquent, une cellule de mémoire est produite en utilisant deux états différents, l'un est une tension de seuil élevée de la cellule pro grammée, et l'autre est la tension de seuil faible de la cellule non programmée. To program the EPROM cell of the present invention, a high voltage, preferably around 12 V, is applied to the control gate 11 constituted by a poly-II layer connected to the N-type diffusion zone via of the buried contact, and a high voltage is also applied to a drain 7 in Figure 3 so that electrons are accumulated on the floating gate 13 by avalanche injection of hot electrons around the channeled drain of the cell. Therefore, a memory cell is produced using two different states, one is a high threshold voltage of the programmed cell, and the other is the low threshold voltage of the unprogrammed cell.
Du fait que la croissance d'oxyde entre la couche poly-I et la couche poly-II peut être augmentée indépendamment de l'épaisseur du second oxyde, cette nouvelle cellule EPROM peut résoudre complètement les problèmes qui se posent par suite d'un courant de fuite depuis le bord de la première couche poly vers la seconde couche poly dans une cellule classique. Conformément à la présente invention, une cellule EPROM de fia bilité élevée peut être réalisée, et une cellule de mémoire et logique de haute fiabilité peut également être fabriquée avec cette cellule EPROM
Pour réaliser la nouvelle cellule EPROM, les étapes de fabrication suivantes sont nécessaires. Selon les techniques de fabrication classique, un oxyde tampon 31 et une couche de nitrure 3? sont déposés sur le ou les substrats (s) qui possèdent une zone de cellule divisée par un oxyde de champ pour réaliser une cellule telle que représentée sur la Figure 5(A). Une gravure de tranchée avec un masque de tranchée est effectuée en se référant à la structure telle que représentée sur la
Figure 5(B). La zone de tranchée est remplie d'une couche d'oxyde et la couche d'oxyde est gravée jusqu'au point terminal (P) de la couche de nitrure tel que représenté sur la Figure 5(B). Après que la couche d'oxyde ait atteint le même niveau que l'oxyde tampon 31, la couche de nitrure est éliminée comme représenté sur la Figure 5(C).Because the oxide growth between the poly-I layer and the poly-II layer can be increased regardless of the thickness of the second oxide, this new EPROM cell can completely solve the problems that arise as a result of current leakage from the edge of the first poly layer to the second poly layer in a conventional cell. According to the present invention, a high reliability EPROM cell can be produced, and a high reliability memory and logic cell can also be produced with this EPROM cell.
To make the new EPROM cell, the following manufacturing steps are necessary. According to conventional manufacturing techniques, a buffer oxide 31 and a nitride layer 3? are deposited on the substrate (s) which have a cell area divided by a field oxide to make a cell as shown in Figure 5 (A). A trench engraving with a trench mask is made with reference to the structure as shown in the
Figure 5 (B). The trench area is filled with an oxide layer and the oxide layer is etched to the end point (P) of the nitride layer as shown in Figure 5 (B). After the oxide layer has reached the same level as the buffer oxide 31, the nitride layer is removed as shown in Figure 5 (C).
Ultérieurement, la grille de commande de la cellule est fortement dopée pour être de type N avec le masque de cellule comme représenté sur la Figure 5(D). En référence à la Figure S(E), (F), l'oxyde tampon est éliminé, et l'oxyde de grille 12 et la couche poly-I sont déposes, et la zone de couche poly-I est délimitée en masquant la couche poly-I, et l'on fait croître un oxyde épais sur la couche poly-I entre la couche poly-I et la couche poly-II afin de résoudre le problème du courant de fuite. Ensuite, la couche poly-II est déposée avec le contact enterré 20, et la zone de la grille de commande pour le fil de mot de la cellule de mémoire est délimitée en masquant la couche poly-II. Par con séquent, une source/drain dopés de type N sont réalisés par une implantation ionique N avec un masque N . Un oxyde BPSG 23 est formé, et après masquage de contact, une couche de métal 24 est déposée et une couche de passivation 25 est réalisée. La cellule EPROM de l'invention avec la structure telle que représentée sur la Figure 5(G) est réalisée. Subsequently, the cell control grid is heavily doped to be of type N with the cell mask as shown in Figure 5 (D). Referring to Figure S (E), (F), the buffer oxide is removed, and the gate oxide 12 and the poly-I layer are deposited, and the poly-I layer area is delimited by masking the poly-I layer, and a thick oxide is grown on the poly-I layer between the poly-I layer and the poly-II layer in order to solve the problem of leakage current. Then, the poly-II layer is deposited with the buried contact 20, and the area of the control grid for the word wire of the memory cell is delimited by masking the poly-II layer. Consequently, an N type doped source / drain is produced by an N ion implantation with an N mask. A BPSG oxide 23 is formed, and after contact masking, a metal layer 24 is deposited and a passivation layer 25 is produced. The EPROM cell of the invention with the structure as shown in Figure 5 (G) is produced.
Claims (2)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019880007986A KR970000652B1 (en) | 1988-06-30 | 1988-06-30 | Eprom cell & method of manufacturing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2633777A1 true FR2633777A1 (en) | 1990-01-05 |
| FR2633777B1 FR2633777B1 (en) | 1993-12-31 |
Family
ID=19275680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR8908469A Expired - Lifetime FR2633777B1 (en) | 1988-06-30 | 1989-06-26 | EPROM CELL USING TRENCH ISOLATION AND MANUFACTURING METHOD THEREOF |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH02119185A (en) |
| KR (1) | KR970000652B1 (en) |
| DE (1) | DE3920451C2 (en) |
| FR (1) | FR2633777B1 (en) |
| NL (1) | NL194183C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0354457A2 (en) * | 1988-08-08 | 1990-02-14 | National Semiconductor Corporation | A bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3083547B2 (en) | 1990-07-12 | 2000-09-04 | 株式会社日立製作所 | Semiconductor integrated circuit device |
| DE4200620C2 (en) * | 1992-01-13 | 1994-10-06 | Eurosil Electronic Gmbh | Floating gate EEPROM cell with sandwich coupling capacitance |
| KR100790044B1 (en) * | 2006-03-09 | 2008-01-02 | 엘지전자 주식회사 | Cooling apparatus of electric hob |
| KR100701179B1 (en) * | 2006-03-24 | 2007-03-28 | 주식회사 대우일렉트로닉스 | A device for cooling convection motor of microwave range |
| KR101684116B1 (en) | 2015-05-26 | 2016-12-08 | 현대자동차주식회사 | Method for controlling air flow for vehicle |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0138517A1 (en) * | 1983-10-11 | 1985-04-24 | AT&T Corp. | Semiconductor integrated circuits containing complementary metal oxide semiconductor devices |
| US4698900A (en) * | 1986-03-27 | 1987-10-13 | Texas Instruments Incorporated | Method of making a non-volatile memory having dielectric filled trenches |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60260147A (en) * | 1984-06-06 | 1985-12-23 | Fujitsu Ltd | Semiconductor device |
-
1988
- 1988-06-30 KR KR1019880007986A patent/KR970000652B1/en not_active IP Right Cessation
-
1989
- 1989-06-20 NL NL8901545A patent/NL194183C/en not_active IP Right Cessation
- 1989-06-22 DE DE3920451A patent/DE3920451C2/en not_active Expired - Lifetime
- 1989-06-26 FR FR8908469A patent/FR2633777B1/en not_active Expired - Lifetime
- 1989-06-28 JP JP1166474A patent/JPH02119185A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0138517A1 (en) * | 1983-10-11 | 1985-04-24 | AT&T Corp. | Semiconductor integrated circuits containing complementary metal oxide semiconductor devices |
| US4698900A (en) * | 1986-03-27 | 1987-10-13 | Texas Instruments Incorporated | Method of making a non-volatile memory having dielectric filled trenches |
Non-Patent Citations (2)
| Title |
|---|
| 1986 IEDM International Electron Devices Meeting, 7-10 december 1986 Los Angeles, CA, US; pages 592 - 595; J.ESQUIVEL et al.: "High Density Contactless, Self Aligned EPROM Cell Array Technology" * |
| IEEE ELECTRON DEVICE LETTERS. vol. ED-8, no. 4, avril 1987, NEW YORK US pages 146 - 147; A.L.ESQUIVEL et al.: "A Novel Trench-Isolated Buried N+ FAMOS Transistor Suitable for High-Density EPROM's" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0354457A2 (en) * | 1988-08-08 | 1990-02-14 | National Semiconductor Corporation | A bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture |
| EP0354457A3 (en) * | 1988-08-08 | 1990-10-17 | National Semiconductor Corporation | A bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3920451A1 (en) | 1990-01-04 |
| FR2633777B1 (en) | 1993-12-31 |
| NL194183B (en) | 2001-04-02 |
| DE3920451C2 (en) | 1993-12-02 |
| NL8901545A (en) | 1990-01-16 |
| KR970000652B1 (en) | 1997-01-16 |
| KR900001023A (en) | 1990-01-31 |
| NL194183C (en) | 2001-08-03 |
| JPH02119185A (en) | 1990-05-07 |
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