FR2630877A1 - Circuit element-crossover point between two bus lines - Google Patents

Abstract

The crossover point is intended for the ATD multiplexing of digital information in the form of fixed length packets between two buses A-B and C-D; it consists of: a first shift register RAB, a first buffer register RTE, a RAM memory MRAM, a second buffer register RTS, a second shift register RCD, and logic circuits consisting of a decision unit for packet extraction DE and insertion DI, associated with a decision table TEX and TIN, and a unit for managing the RAM GM. The extraction and insertion of packets are effected asynchronously with respect to one another. Application to the ATD multiplexing of digital information.

Description

DESCRIPTION circuit-cross point element between two. bus lines ".

 A point of intersection between two digital independent ATD multiplexing ionodirectional buses consisting of consecutive fixed length data packets carried by said buses, which packets include a tag field of n bits and an information field of i bits n and i being fixed and such that n + i = d, to selectively transmit digital information from one bus to another.

 There are many methods and devices for switching information from one line to another. Methods and devices specifically adapted to ATD (Asynchronous Time Division) packet switching are much less numerous because of the novelty of the information multiplexing ATD concept. ATD multiplexing of information is currently being input into the CCITT for standardization and can be characterized in that the information is divided into fixed-length packets, a fixed-length tag being associated with each packet and to identify the communication to which each packet belongs. On the transmission line the packets are consecutive, that is to say that in the absence of information, the line vehicles. empty packages (of the same length as the others), containing no information but each punished with a label, to ensure the filling. The ATD technique has the main goal of achieving the highest flow rates possible; this introduces the problem of signal propagation delays, which is not negligible when it is desired to maintain correct synchronization between the information-carrying signals, their respective clock signals and the logical decision signals.

 The specific technical problem to be solved by the invention is to be able to switch the information packets defined above from one line to another as quickly as possible, that is to say from a bus starting at an arrival bus, taking care not to delay the propagation of information on the departure and arrival buses.

It will be noted that the packets are provided of a fairly large length, of the order of 256 bits for the information field (i = 256) and 16.32 or 48 bits for example for the tag (n = 16, 32 or 48). Moreover, to obtain high information rates on buses, these buses generally consist of several conductors in parallel, for example 16 conductors.

 In a technical field quite different from that of the invention, namely the field of digital graphics systems, it is also necessary to obtain very high information rates at certain points of the system. From the publication "Electronics, Techniques and Industries" No. 31 of March 17, 1986, a dual-network RAM memory is known, which makes it possible to avoid a bottleneck limiting the flow of the graphics system. The first zone is a 256K dynamic RAH memory used as a visualization memory and the second zone is a static RAM memory of i K addressed by a counter integrated on the chip which allows access to a single chip. These two zones work independently via separate input-output ports, except during the transfer cycles in which the data of the second zone is transferred entirely in parallel from the second to the first memory zone. in less than 200 ns The structure of this memory is however not designed and is therefore not able to transfer information from one bus to another.

 An object of the invention is to provide in integrated circuit (s) a crossover point for multiplexing ATD digital in formation between two buses, very fast, to allow a high information rate.

 Another aim is to allow the realization of important switches using various architectures using as basic elements of the modular crossover points according to the invention rapid between buses taken in pairs, which corresponds to a concern for extensibility.

These goals are achieved by virtue of the fact that the crossing point defined in the first paragraph of the description is remarkable in that it is constituted by the combination of two functional blocks of an integrated circuit. A first functional block consisting of the succession in
waterfall between one of said buses, said bus departure, and the
bus, called arrival bus
a) a first shift register with input (s) series-d sor
parallel lines arranged in a break on the bus of departure,
b) a first buffer register with parallel inputs
parallel
c) a RAM memory at m bit locations with a bus
addresses for m locations,
d) a second buffer register with parallel inputs
parallel
e) a second shift register with parallel inputs
output (s) series arranged in a cutoff on the arrival bus, - and a second functional block logic decision com
mutation involving, arranged symmetrically with respect to
departure and arrival buses, an extrac
package insertion, respectively associated with each
to a pre-made decision table, which receives the donations
born of label packages on the. departure bus (respecti
on the arrival bus) and who are each driving an orga
management of RAM connected to it by said bus
addresses, the management body managing the RAM as at least
a queue for packets, syn drivers
clock tick bit, clock label and clock
package being provided, and the non-destructive extraction of
quets of the departure bus as well as the insertion of packages on
the arrival bus being done asynchronously
one with respect to the other.

 The structure of the crossover point defined above is original by its buffer registers which make it possible to adapt the writing (respectively the reading) of whole words in parallel in a RAM, at high information rates on a bus. departure (respectively arrival). This structure is also original in that the RAM is managed as one or more queue (s) and in that, still to maintain a high speed of information transfer, this transfer takes place unidirectionally to across the crossing point.

 The "crossover point" feature is an analogy to spatial architectures. Indeed, a crossing point can be considered as a minimum switch between two buses or lines. However, according to the ATD technique, the switched information is not constituted by analog information but by digital packets of information bits. This feature, which exploits fully the crossover point according to the invention, combines the advantages of space architectures with those of time architectures either to recreate known switch architectures or to create new architectures only possible by this combination space- time.

A crossing point consists of the two functional blocks defined above. These blocks can be made in the form of a single integrated circuit or in the form of two integrated circuits. In both cases, the number of trees-outputs of these circuits is high, especially for buses with 16 or more conductors, since each of these circuits necessarily includes a number of inputs-outputs equal to twice the number of drivers of each bus plus other inputs-outputs that are specified below. Preferably, the crossing point is made in C-MOS technology and its different parts can be designed in the dynamic and / or static form. The shift registers, the buffer registers and the
For example, the crosspoint RAMs are designed to handle packets whose length is equal to or greater than 288 bits in parallel. For example, the RAM has 128 or 256 word slots of 288 bits or more.

It should also be noted that the information rates on the departure and arrival buses can be different and even very different. The logical decisions of extraction or insertion of packet are always carried by labels because the decision time must be short compared to the bit time given the high flows sought. For this reason, when the crossing point is made in the form of two separate circuits, the latter must be placed a few centimeters apart from each other only for the purpose of proper operation, that is to say say so as not to interfere with the synchronization between the information signals and the logical decision signals. In this way, package extraction or insertion decisions are fully distributed over the crossover points.

 The following description with reference to the accompanying drawings, all given by way of example will make it clear how the invention can be realized.

 The single figure is a functional block diagram of the crossing point according to the invention.

In the figure, the term
AB a first one-way bus called departure bus
CD a second one-way bus called arrival bus
MRAM an RAH memory plane whose word width is equal to
that of a packet is d bits.

GM a management body of HRAM
Of a packet extraction decision organ since the
bus AB to the MRAM memory plane
TEX a decision table associated with DE
DI a packet insertion decision organ since the
MRAM memory map to the CD bus
TIN a decision table associated with DI
RAB a first shift register A to B and parallel output
to RTE
RTE a first buffer register between RAB and MRAM KCD a second shift register C to D and parallel input
lele from RTS
RTS a second buffer register between MRAM and RCD
HAC the clock input of the GM management body
HBAB AB bus bit clock wire
HPAB AB bus packet clock wire
HEAB the AB bus label clock wire
HBCD bit clock of the CD bus
HPCD the CD bus packet clock wire
HECD the CD bus label clock wire.

The functional links and the operating principle are as follows
To avoid complicating the presentation, it is considered that the shift registers RAB and RCD have the same length of d bits as the packets although this is not imperative, the length of these registers may indeed be greater than d.

Operation on the AB bus side
The information is propagated on the AB bus at the rhythm of the HBAB clock which is supplied to the register RA8. The register
RAB is arranged in break on the bus AB. For each wire of the bus AB (this bus can at least theoretically be reduced to a single wire), the bits of the packets enter, leave and shift inside the register, in series. The son of clocks
HEAB and HPAB are connected to the packet extraction decision device DE as well as the bus driver (s) A which are related to the tag field. The clock HPAB determines, in DE, the time t2 at which the entire packet from the bus A (information plus tag) is in the register RAB.

The clock HEAB determines, in DE, the time t1 at which the organ
DE has received the entire label-of each packet. It will be noted that the tag is arranged, chronologically speaking, at the head of each packet, which amounts to saying that the instant t1 precedes the instant t2. The duration t2-t1 is used to make the decision to extract or not extract the packet contained in the RAM register at time t2 and to perform this transfer in case of a decision to extract, in less than a clock period HBAB, i.e. less than one bit time, of the register RAB in parallel to the buffer register
RTE.In other words, when the DE has received the entire label, it is able, on the basis of the content of the label and according to its internal logic, to take one of the following two decisions: : either, in a first case, the packet must be copied from the RAB register to the MRAM memory plane, or in a second case the packet must not be copied to the MRAM memory plane. In both cases the packet considered continues, after time t2, to flow on the bus B. The packet transfer order from RAB to MRAM is effected by means of a given command, on a driver 1 by 1 DE member to the buffer register RTE for it first stores the contents of the register RAB and the GM management unit of MRAM.This command results in a write command of the content of the buffer register RTE in
MRAM to an address pointing to an empty word slot in
MRAM. This address is carried by an address bus 2 which connects the GM member to MRAM and which also serves as read address bus.

CD side operation
It is important to note that the operation of the CD bus is completely independent of the operation of the bus
AB from the point of view of the synchronism as the flow of information or decisions of extraction, respectively insertion. The information is propagated on the CD bus to the rhythm of the HBCD clock which is supplied to the RCD register. The register
RCD is arranged in break on the CD bus. The son of clocks
HECD and HPCD are connected to the packet insertion decision unit DI as well as the bus conductor (s) which is (are) relative to the tag field. The clock HPCD determines, at DI, the time t4 at which the entire packet from the bus C (information plus tag) is in the register RCD.The HECD clock determines, in DI, the time t3 at which the DI organ received the entire label of each packet. As on the bus AB, the label is arranged at the head of each packet, which implies that t3 is prior to t4.

The duration t4-t3 is used to make the decision to insert or not to insert a packet, contained in the RTS register that contains it, into the RCD register at time t4 and to perform this transfer, in case of insertion decision, in less than a clock period HBCD, of the register RTS, in parallel, to the register RCD.In other words, when the organ
DI has received the entire label, it is able, based on the content of the label and according to its internal logic, to take one of two decisions: either, in a first case, the packet from the bus C which bears this label is a non-empty packet and in this case the decision is not to insert and leave the packet contained in the RCD register out on the bus D; either, in a second case, the packet from the bus C is empty, that is to say that its information field is meaningless and in this case the decision taken between the instants t3 and t4 will be to copy the packet that is in the RTS register, from the MRAM memory plane, in the RCD register and thus overwrite the empty packet therein. Of course, the fact that the packet entering the bus C is empty is not necessarily sufficient to cause its crash in the RCD register; the decision-insertion member DI may in fact take into account other information contained in the packet label to decide whether to overwrite the packet. The action is actually undertaken only when the packet is completely contained in the RCD register by an order sent, on a conductor 3 by the insertion decision body DI to the RTS buffer register and to the management body GM of the MRAM memory map. This order results in a read command in
MRAM at an address pointing to a location occupied by a word (packet) in MRAM and transferring that word, in parallel, to the RTS buffer register. This address is carried, in turn, by bus 2.

The management unit of the memory array GM receives commands from the two decision logic contained in the registers DE and DI in a totally asynchronous manner. The organ GM is designed to adjust in time conflicts of access to the MRAM memory plane, more precisely, to organize, over time, the write and read cycles in MRAM. It is known that it is not possible to register and read a RAM memory simultaneously. If a reading order of HRAM in
RTS, following the transfer of the contents of RTS in RCD, arrives on the driver 3 while MRAM is being registered, the reading order in question is stored in GM, until the order of writing is completed at a time t5 and starts after a timer initiated in t5.The operation, symmetrical, is identical for a write order of the contents of RTE in MRAM arriving during the execution of a reading cycle. The necessary memorizations and delays are carried out in a known manner in GM by means of logic circuits controlled by the clock BAC. It should be noted in this regard that the frequency of the clock HAC is equal to or greater than the highest clock frequency bit HBAB or HBCD.Other the conflict resolution write! read in MRAM, to ensure the asynchronism between the RAB and RCD serial registers which operate on a HBAB and HBCD bit clock and the memory
MRAM that runs at the pace of an HPAB packet clock or
HPCD, the RTE and RTS buffer registers, which operate entirely in parallel, have been associated with each serial register. In addition, they allow the isolation between the address bus of the memory plane and the parallel accesses of the serial buses, in other words, the transfers in parallel in less than one bit time of the contents of the register RAB to RTE and in less a packet time from RTE to MRAM and a word from MRAM in the RCD register are thus made possible, and compatible with MRAM write and read cycles from the same address bus 2.La KRAM memory is managed by one or more queues by the management unit GM and, in both cases, each queue only exchanges in the direction of the bus AB to the bus CD. This makes it possible to simply perform the crossing point from a memory plane and a management unit. The use of a random access memory array, MRAM, provides a maximum memory capacity with equal component area. The memory plan management unit GM transforms MRAM into one or more queues. On the other hand, since the access time to the memory plane is the critical element of the crossing point, the length of the words is as great as possible. Thus, for the same number of switched bits given, the number of accesses will be inversely proportional to the length of the word. In these conditions, the preferred word length is the length of a packet. The fact that the queue only exchanges in one direction corresponds to the most common operation provided for the crossing point. This arrangement simplifies several critical points of the realization, namely: in the first place, the access time to the memory plane is limited and this time would be double if we had to introduce queues with opposite directions, second In this way, the power consumed by the access to the memory plane is reduced. This unique sense of the queue simplifies the creation of buffer registers and serial registers, which facilitates integration and increases the speed of operation. Note that when, in the preferred case, MRAM has only one queue, this memory is organized as a FIFO.For this purpose, the addresses in writing and in reading are, for example generated respectively by pointers d address ses, that is to say by counters which are incremented by one unit after each write, respectively each reading in the RAH. The memory locations of MRAM are thus cyclically ex- ploited by the two pointers, the read pointer naturally having to be late on the write pointer. Prohibitions can result from a blocking configuration such as: MRAM full during a write request or, conversely, MRAM empty during a read request. In both cases, the command must not not be executed and for this purpose, the management member GH may include a filling rate measurement device which continuously receives the addresses of the address pointers in writing and reading, which establishes the difference between these addresses and which generates a write inhibit signal, respectively reading, when MRAM is full, respectively empty. The design of this device for measuring the filling ratio, not shown, is within the reach of those skilled in the art.

 The purpose of the multiplexing function of the crossing point according to the invention is to mix with the packet stream arriving on the bus C the packet stream coming from the MRAM queue. The resulting flow goes out in D. The implementation of the multiplexing carried out exploits the peculiarity that the ATD packets have, to be of constant and consecutive length. In the absence of information there are packages whose information field is meaningless. The multiplexing method is very simple and simply consists of the RCD serial register between buses C and D with parallel input from the queue and the length of a packet. The multiplexing consists, at the moment when the RCD register contains exactly one empty packet, to overwrite it by the packet which is at the head of the queue, more precisely the packet which is preloaded in the buffer register RTS. Since this replacement is totally within the RCD register, there is no conflict of access to the C-D bus with another crossing point. Because of its great simplicity of design, the aforementioned multiplexing method, implemented by the crossing point according to the invention is very easy to integrate and allows high flows.

 The decision logic for extracting or inserting the packet is constituted by the blocks DE, TEX, respectively the blocks DI, TIN. It is this logic that makes the decision to transfer one bus (A-B or C-D) to the other (C-D or A-B).

This logic is totally distributed, that is to say that not only is it associated with each crossing point and independent of that of the others, but it is also composed of two independent devices for the bus AB and the bus CD. Both devices use the same hardware solution and are fully programmable. It will be noted that, in order to produce a very high-power switch, centralized decision logic is inconceivable given the very high data rates sought which leave too little time to find the output line associated with each incoming packet, all the more so. more than this time must be reduced to take into account the signal propagation time. In the chosen solution, the decision logic is associated not only with each crossing point but also with each bus whose distances to be traveled by the signals. The decisions are negligible and the decisions only concern AB bus or CD bus packets and do not depend on any decision from another crossing point. In principle, all the information necessary for the decision is conveyed with the packet itself in a field of the label. However, it can be envisaged that signals coming from outside the crossover point are combined with the contents of the packet labels to confirm or otherwise inhibit the decisions. The solution adopted here, which is a distributed solution makes it easy to organize crosspoints in different architectures; this is all the easier as the solution chosen, according to the figure, allows in a single cycle to analyze all the possible combinations of the label field which is used for the decision. The practical realization of this decision logic in the crossing point is very simple since it is, in the simplest case to consider, a table of 2n bits addressed by the decision field of the label which includes n bits. At the value O or 1 of the addressed bit, there is the decision whether or not to store this packet in memory, respectively to replace it or not by a packet of the MRAM. On the figure, the organ
DE is connected to the TEX table by an n-conductive address bus, 4. The label of each packet on the bus A is transmitted to the bus 4. The TEX decision table comprises 2n locations, addressed by the bus 4 and whose content is preprogrammed to O or 1. The content of the location addressed by the bus 4 is transmitted from TEX to DE by a driver 5. This last information, possibly supplemented by information from the outside, no represented, translates into DE by a command to extract or not to extract a packet from the register RAB.

 The organs DI and TIN have a structure and a functioning identical to DE and TEX; they are interconnected by the bus 6, a counterpart of 4, and the driver 7, a counterpart of 5.

 MRAM memory can be organized for example as two queues in order to give priority totally or partially the second. queue compared to the first. The second queue is then the one that is emptied first, for a total priority.

For a partial priority corresponding to a mixed logic, one skilled in the art ensures that, for example, the second queue is emptied first but for a limited time after which the first queue can to empty in turn. For a subscriber who wishes to be able to transmit or receive information at the same time, the equipment for connecting this subscriber to a bus of the network requires two crossing points operating one in the direction of reception (of the bus AB to the CD bus), the other in the direction of transmission (from the CD bus to the AB bus), which results in a permutation of the start and end buses for the switching of the packets.

 The information rates on buses A-B and C-D can be comparable or very different and can be counted in Mbps on one bus and in kbits / s on the other bus.

 Note finally that if the shift register RCD is necessarily cut off on the arrival bus, as the arrival register of information from another information bus, it is not the same the RAB register on the bus, whose position in cut is not essential. In fact, the register RAB could be arranged in derivation with respect to the bus AB, in the same way as the organs DE and DI with regard to the labels of the packets, which would have the advantage of saving, on the bus AB, the filling time of the RAB register for the propagation delay of the packets. However, it is preferred according to the present invention to keep the off-shift register on the start bus for better signal regeneration and good resynchronization of these signals with their bit clock.

Another advantage that appears in the figure is to keep the component a certain symmetry.

The crossing point can be embodied as one or two integrated circuits. For an embodiment in two integrated circuits, the broken line 8 indicates the separation between the two circuits, on one side the subset or functional block constituted by the cascade succession of the information storage elements: RAB, RTE,
MRAM, RTS and RCD, and on the other side the subset or functional block constituted by the logic part of the switching decision constituted by the elements: DE, TEX, DI, TIN and
GM.

Claims (7)

A point of intersection between two mutually independent one-way buses for digital information ATD multiplexing consisting of consecutive fixed-length data packets carried by said buses, which packets comprise an n-bit tag field and an information field of i bits n and i being fixed and such that n + i = d, to selectively transmit digital information from one bus to the other, characterized in that it consists of the combination of two integrated circuit functional blocks - A first functional block consisting of the succession in  waterfall between one of said buses, said bus departure, and the  bus, called arrival bus  a) a first shift register with input (s) series-d sor  parallel lines arranged in a break on the bus of departure,  b) a first buffer register with parallel inputs  parallel  c) a RAM memory at m bit locations with a bus  addresses for m locations,  d) a second buffer register with parallel inputs  parallel  e) a second shift register with parallel inputs  output (s) series arranged in a cutoff on the arrival bus, - and a second functional block logic decision com  mutation involving, arranged symmetrically with respect to  departure and arrival buses, an extrac  package insertion, respectively associated with each  to a pre-programmed decision table, which receives the donations  labels on the starting bus (respecti  on the arrival bus) and who are each driving an orga  management of RAM connected to it by said bus  addresses, the management body managing the RAM as at least  a queue for packets, syn drivers  clock tick bit, clock label and clock  packet being provided, and the non-destructive extraction of  starting bus packages as well as inserting packages  on the arrival bus being done asynchronously  one with respect to the other. Crossover point according to claim 1, such as: d> 144. 3. crossing point according to claim 1 or 2, characterized in that said first and second functional blocks are each made in the form of an integrated circuit component. 4. crossing point according to claim 3, characterized in that said first and second integrated circuit components are, for their operation, implanted a few centimeters relative to each other. Crossover point according to claim 1 or 2, characterized in that it is embodied as a single integrated circuit component. 6. Crossover point according to one of claims 1 to 5, characterized in that it is made in C-MOS technology. 7. Crossover point according to one of claims 1 to 6, characterized in that it comprises first, respectively second shift registers with 16 inputs and 16 serial outputs, designed to contain packets of length d at least equal to 288 bits and whose RAM has at least 128 word slots of 288 bits or more.