FR2628552A1 - CHARGE TRANSFER DEVICE FOR PROCESSING ANALOG DATA BLOCKS - Google Patents

Abstract

The invention relates to the processing of analog data in blocks. It relates in particular to image processing. One seeks for example to carry out a treatment of each pel by convolution of the neighboring pels of a block of 5 × 5 pels with a convolution kernel. Delay lines are used in the form of charge transfer shift registers and cut-electrode charge transfer filters. To save space, the invention proposes to carry out filtering of the type with cut electrodes by cutting certain electrodes of the shift registers themselves. For example, the image to be processed comprises lines of P points and the shift registers are registers with P stages. Among these P stages, 5 electrodes will be used (since it involves processing 5 × 5 blocks) which will be cut and which will be connected to the inputs of an amplifier AMP. Several different convolutions can also be provided on the same integrated circuit chip by using other electrodes of the registers and by connecting these other electrodes to other amplifiers.

Description

CHARGE TRANSFER DEVICE

  FOR PROCESSING ANALOG DATA BLOCKS

  The present invention relates to the processing of analog data in the form of electrical signals. It concerns the processing of data arriving in blocks of n rows of m data, and it is applicable

  in particular analog processing of images.

  By way of example, the invention applies to the processing of images using a convolution function on a data block, that is to say an operation consisting of making for each block of nxm data the sum of

  products of each given by a respective coefficient.

  FIG. 1 represents a diagram of an analog image processing device able to perform a processing of an image by a block of 5 × 5 coefficients, each elementary image point, hereinafter referred to as pel, being represented by a signal analogue whose amplitude is proportional to a quantity of

light received by this image point.

  It is assumed that the image's pels arrive line by line and sequentially in each line, that the entire image has N lines of P points each, and that the analog processing is a convolution of a square block of 5x5 adjacent pixels of the image by a matrix of 5x5 coefficients. This convolution provides a new signal representing a pel value which is for example intended to be substituted for the value of the central pel of the 5x5 block. The convolution processing can be performed on all the pixels of the image (NxP pels), that is to say that the value of each image pel will be replaced by the result of the convolution function executed on the 25 pels of a centered block

on this pel.

  The block of peels is represented in FIG. 1 in the form of adjacent boxes divided into five lines Li to L5 of five boxes each; the central pel is represented in black. Each box is assigned a value represented by an analog signal and this signal must be multiplied, to convolution, by a

  well-determined coefficient of a set of coefficients.

  A circuit that can be used to make this treatment

  signal is shown in Figure 1.

  This circuit has an analog signal input E, four delay lines LR1, LR2, LR3, LR4, and five

  analog filters F1, F2, F3, F4, F5.

  Pels are introduced at a frequency

  fixed sampling rate.

  Each filter processes five pels of the same line simultaneously and provides an analog signal which is a sum of the five weighted pels values by five coefficients (in line) of the convolution coefficient matrix. Each filter therefore performs a part of the convolution and the global convolution consists in adding the results of the partial convolutions

  performed on the pels of the five lines of a block.

  For the addition of the results of the convolutions to be meaningful, these results must be added in phase, ie the summed results must correspond to groups of pels in the same block. treat. As the pels arrive sequentially not by lines of five pels but by lines of P pels (P can classically be of several hundred or thousands of points), one delays by a duration of four complete lines of P pels each the pels of the first line Li of the block to be treated before treating them; the Pels of line L2 are delayed by a duration of three lines of P pels; two lines are delayed by those of line L3; the line L4 is delayed by one line, and finally the line L5 is processed directly without delaying them. It is the role of LR1 & LR4 delay lines to slow down the arrival of the pels to the respective filters that have to deal with them. This is why the filter F5 which performs the partial convolution of the pels of the line L5 of the block is directly connected to the input E of the device; the filter F4 is connected to the output of the delay line LR1 whose input is connected to the signal input E; the filter F3 is connected to the output of the delay line LR2 whose input is connected to the output of the delay line LR1; the filter F2 is connected to the output of the delay line LR3 whose input is connected to the output of the line LR2; finally, the filter F1 is connected to the output of the delay line LR4 whose input is connected to the output of

line LR3.

  The outputs of the filters F1 to FS are applied to the inputs of an adder ADD whose output S is the output of the convolution processing device. This output provides analog signals sampled at the insertion frequency of the pels on the input E. It is known to make delay lines and filters under

  form of charge transfer devices.

  The delay lines are then charge transfer shift registers constituted by a succession of groups of electrodes (four for example) each constituting a stage of the register. The electrodes are arranged transversely to the direction of shift of the transported charges, and they succeed one another

  next to others in this direction of shift. The.

  electrodes of a group are brought to levels of potentials periodically varying according to well-defined phases relative to each other, the phases being the same for the corresponding electrodes of the different stages. For example, in a two-phase charge transfer shift register, each stage comprises four consecutive electrodes which are successively a first transfer electrode, a first storage electrode, a second transfer electrode, and a second storage electrode. The potentials applied to the electrodes can take either a high level or a low level. In a first phase 41 a first potential level is applied to the first transfer electrode and the first storage electrode (for all the stages of the register), and the other level is applied to the other two electrodes of all the stages; in a second phase 42, the potentials are inverted, which ensures the shift of the charges from the first storage electrode to the second storage electrode of the same stage; in a third phase e3 the potentials are applied again as in the first phase, and in a fourth phase 44 they are applied as in the second phase, which ensures the shift of the charges from the second storage electrode to the first electrode of storage of

the next floor.

  There are also known charge transfer analog filters, called transverse cut electrode filters, whose structure is very close to that of a two-phase charge transfer shift register. The general structure of such a filter is shown schematically in FIG. 2 for a five-point transversal filter; for each stage of the filter, the construction still has consecutively a first transfer electrode, a first storage electrode, a second transfer electrode, and a second storage electrode; but: on the one hand, one of the two storage electrodes of each stage is cut transversely into two portions of different surfaces, the sum of the surfaces being the same for all the storage electrodes cut off from the different stages; the relative proportions of the two portions vary between 0 and 1 depending on the stage considered, relative to the overall surface of the electrode; these proportions define convolution coefficients for the filter; if it is the first storage electrode of a stage of the filter which is cut off, it is then the first electrode which is cut off for all the stages of the filter; for a five point filter, there are five stages so five storage electrodes are cut off; they are designated ES1, ES2, ES3, ES4, ES5 in Figure 2; the second storage electrodes, uncut, interposed between the cut electrodes, are designated ES'1 to ES'5 respectively; the transfer electrodes between a cut electrode and an uncut electrode are not shown so as not to overload the figure; on the other hand, all the upper parts of the cut storage electrodes are connected to a first input of a differential amplifier AMP, and all the lower parts of these electrodes are

  connected to a second input of this amplifier.

  The input signal is constituted by load quantities sampled at a constant frequency, which go under the first storage electrode ES1 and then are shifted as in a shift register; at a given moment, five signal samples corresponding to five points of a pixel block of an image line can therefore be processed; the amplifier provides a signal which is proportional to the weighted sum of the five charge samples located under the cut electrodes, the weighting coefficient being between -1 and i and being defined, for a given sample, by the difference (signed) between the surfaces of the two pieces of electrodes under which this

signal sample.

  The output signal of the amplifier is obtained during a phase I'1 between two charge transfer phases, at a time when charges are stored under the cut electrodes; for example, in a possible reading mode, the reading is made at the end of the phase I1 for which the potential applied to the cut electrodes is a high level potential; at this time, the application of the high level potential to the cut electrodes is interrupted and the potential of these electrodes is allowed to float; the potential of the cut grates then takes a value proportional to. the quantity of charges located under these grids, that is to say both proportional to a signal sample and to the surface of the cut gate considered; after summation, the potentials of the transfer and storage grids are re-imposed in accordance with a conventional cycle 42, 3, 4, 11, etc.,

  load transfer shift register.

  Other reading modes are also possible.

  According to the invention, it is proposed to provide a data block processing device using both charge transfer delay lines and cross-cut electrode filters. But instead of using a processing circuit structure such as that of FIG. 1, the invention proposes using certain stages of the delay line as filters by cutting off the electrodes of these stages and by controlling them appropriate, to achieve a more compact and homogeneous structure, taking advantage of the remark that a transversal filter & cut electrodes does not alter the signal samples that pass through it but delays these samples of the same

  way a charge transfer delay line.

  More specifically, the invention proposes a charge transfer device for the nxm block processing data of an NxP matrix analog data, comprising n-1 cascaded delay lines, each delay line being constituted by a shift register P load transfer stages periodically actuated at a data input frequency in the first of the lines, each stage consisting of the succession of at least one transfer electrode and a storage electrode, characterized in that m electrodes of storage of each delay line, located between the input and the output of the line at locations which are the same for all the lines, are electrodes cut into two parts of respective relative surfaces x and lx, with x variable between O and 1 depending on the electrode considered, and are connected to the input of an amplifier common to all mx (n-1)

  Electrodes cut from n-1 delay lines.

  Preferably, the amplifier is a differential amplifier, a first portion of each cut electrode is connected to a first input of the amplifier, and the second portion of each cut electrode is connected to a second input of the amplifier. Upstream or downstream of the cascade of delay lines, an additional transversal filter with m cut electrodes connected to the same amplifier will be provided for the simultaneous processing of m additional signal samples, ie a total of one block of n × m data. If the additional filter is upstream, then the m cut electrodes of the different delay lines are in principle the last m electrodes of the lines; if it is downstream, the m cut electrodes are, on the contrary, in principle the m

first.

  It is therefore particularly advantageous to provide on the same integrated circuit chip multiple processing devices performing simultaneously (or almost) several different convolutions on the blocks of nxm data, or even on different blocks of n'xm 'data. For this purpose, it is expected that out of the no delay lines, none of these delay lines each comprise cut electrodes, other than the m already in use, situated between the input and the output of the line at locations predetermined ones which are the same for the n 'lines, and connected to another amplifier. For example, on the same integrated circuit chip, with a limited space requirement, two different convolutions of 5 × 5 blocks given on the same image, or a convolution of data blocks and a convolution of blocks can be realized on the same same chip. of 3x3 data. It will be noted that the entire device performs a direct processing on an analog signal consisting of charge quantities, minimizing the number of conversions voltage / charge and charge / voltage

  necessary, therefore the noise introduced by the treatment.

  Other features and advantages of the invention

  will appear on reading the detailed description

  which follows and which is made with reference to the accompanying drawings in which: - Figure 1, already described, represents a structure

  known image processing device.

  - Figure 2, already described, shows a known structure of charge transfer filter with cut electrodes. FIG. 3 schematically represents a structure of a block image processing device

according to the invention.

  - Figure 4 shows an embodiment for performing multiple simultaneous treatments. The processing device shown in FIG. 3 therefore comprises, by way of example, four charge transfer shift registers LR1 to LR4, cascading one behind the other. Each register includes P

  stages if images of P points are processed per line.

  In a current embodiment, each stage comprises a first transfer electrode adjacent to a first storage electrode, followed by a second transfer electrode and a second storage electrode, as explained above, and the application phases of the potential to these grids are those which have been explained above: phases 91,% 2, 93, 14 o in practice phases 91 and 13 are identical, and phases 42 and 44 are identical and complementary

phases 41 and 43.

  The first transfer electrodes of the four registers are all interconnected and carried simultaneously to the same potentials; the second transfer electrodes of the four registers are all interconnected and controlled in phase opposition

with the first ones.

  The second storage electrodes are all interconnected and controlled in phase with the second

transfer electrodes.

  But among the first storage electrodes ,. only P-m electrodes are all interconnected and connected to those of the other registers to be controlled in phase with the first transfer electrodes. The other storage electrodes, which are electrodes cut according to what has been explained with reference to FIG. 2 and which are at locations which correspond from one shift register to another, are interconnected but controlled. differently from the others: in the example described, they are controlled in phase with the first transfer electrodes except for a time interval (phase I'1) during which they are left at a floating potential; this time interval takes place at the end of a charge dumping phase f1 under the cut electrodes, as explained in FIG.

reference to Figure 2.

  As in FIG. 2, the m electrodes are connected to the inputs of a differential amplifier AMP. An input el is connected for example to the upper part of the m cut electrodes of all the registers, and another input e2 is connected to the lower part of the m

electrodes of the m registers.

  Each set of cut electrodes acts as a m-point filter and has been designated by the references F1 & F4 respectively in FIG. 3 for the four registers LR1 to LR4. In addition, a group of additional filter stages F5, also with cut electrodes connected to the inputs of the amplifier AMP, were added to also filter a sample of m image points that have not undergone a transformation.

  delay of one or more lines of P points.

  The output S of the amplifier provides the weighted sum of the samples of a block of five by five data of the image of N lines of P data, the weighting coefficients being, for each datum, the difference (with its sign) between the lengths of the upper part and the lower part of the cut electrode under which is at a given moment the quantity

  loads representing this data.

  FIG. 4 represents another embodiment of the invention, in which we benefit even more from

  the reduction in size provided by the invention.

  In this other embodiment, it is desired to simultaneously perform another convolution processing of the signal. Next to the cut electrodes of each register, there are provided further cut electrodes in each register. These m 'electrodes constitute m' filters designated in Figure 4 by F'Il F'5. The positions of the m cut electrodes correspond between them from one register to another. These m 'electrodes are controlled in the same way as the m electrodes, but they are connected to the inputs of another differential amplifier AMP' which provides on its output S 'another convolution result. The result of this other convolution is obtained with a delay of m sampling periods with respect to the result S relating to the same signal samples. This delay may be greater if my cut electrodes do not immediately follow the group of first m

cut electrodes.

  Of course, there may be a third, a fourth group of cut electrodes, etc. Each group provides a result on a respective output amplifier, with a time lag

between each result.

  If there are only two groups and we want to obtain the convolution results practically at the same time (within half a sampling period), we can predict that for the first group of m electrodes the cut electrodes are the first storage electrodes of m stages of the register and that for the second group, the cut electrodes are the second storage electrodes of the same stages and not of a different group of stages. This then assumes that the first group provides a reading result during a I'1 phase at the end of a charge storage phase under the first storage electrodes, and that the second group provides a result during a V'2 phase. at the end of a charge storage phase

  under the second storage electrodes.

  The different convolutions performed by the different groups of cut electrodes do not carry

  necessarily on blocks of data of the same size.

  The maximum size in number of points per block line is however limited by the number of registers to

  offset (n-1) of P points that we expected.

Claims (5)

  1. Device & charge transfer for data processing by nxm blocks data of an NxP matrix analog data, comprising n-1 cascaded delay lines, each delay line (LR1 to LR4) being constituted by a register shifted P charge transfer stages periodically actuated at a data input frequency in the first delay line, each stage consisting of the succession of at least one transfer electrode and a storage electrode, characterized in that m storage electrodes of each delay line, located between the input and output of the line at locations that are the same for all lines, are electrodes cut into two parts of relative surfaces x and lx, with variable x between 0 and 1 depending on the electrode in question, and are connected to the input of an amplifier-summator (AMP) common to all   mx (n-1) electrodes cut from the n-1 lines.   Data processing device according to claim 1, characterized in that upstream or downstream of the delay line cascade (LR1 to LR4) is provided a transverse filter (F5) with cut electrodes actuated at the same frequency that the shift registers, the cut electrodes of this filter being   connected to the input of the same amplifier.   3. Data processing device according to one of the   claims 1 and 2, characterized in that among the   n-1 delay lines, there are provided n-I lines (no less than or equal to n) having m 'cut electrodes other than the m electrodes already mentioned, located between the input and the output of the lines at locations which are the same for all lines and connected to the input of another amplifier-summator. 4. Device according to claim 3, characterized in that each stage of the load transfer registers comprises a succession of four electrodes which are respectively a first transfer electrode, a first storage electrode, a second transfer electrode and a second electrode. storage, and in that the m cut electrodes are first storage electrodes and the m 'cut electrodes are second storage electrodes of the same stages than the m cut electrodes.   5. Device according to one of claims 1 to 4,   characterized in that the cut electrodes have a relative top surface portion x and a relative surface bottom portion 1x, in that the top portions of all cut electrodes of the different registers are connected to a first input of a differential amplifier, and the parties   less than a second input of this amplifier.