FR2617310A1 - Centralised metering device especially for electrical energy consumption - Google Patents

Abstract

The invention is intended particularly for metering electrical energy. In this case, the metering device comprises a plurality of current measurement probes 11, 1j equipping subscriber installations. Time multiplexing means 2, 3, 4 sample measurement currents i1j, i2j, i3j delivered by the current probes. A voltage measurement probe 3 delivers a measurement signal v representing a phase voltage. A calculating circuit 6a supplies digital words representing products of a voltage U multipled by active power factors (cos psi ) and reactive power factors (sin psi ) in a subscriber installation. A digital calculator 6c receives digital samples of measurement current MI, MC and the digital words supplied by the calculating circuit and delivers digital words PA, PR of instantaneous active and reactive electrical energy consumption. Energy meters 8 total the instantaneous consumptions. A tester 9 periodically checks the correct operation of the device.

Description

Centralized metering device in particular
of electrical energy consumption
The present invention relates generally to the consumption of devices or subscriber installations connected to a distribution network of energy product, such as a distribution network of electricity, gas, or water.

 There are currently individual metering devices, such as electricity, gas or water meters. These individual meters are installed at subscribers' homes and record their respective consumption. Agents are responsible for periodically collecting consumption data provided by the meters and transmitting them to a data entry and billing center. The consumption data are then introduced by operators in a calculator in order to establish corresponding invoices. These human interventions for the collection of consumption data and for their entry into the calculator entail operating costs all the more high as the periodicity of the readings is reduced.

 The present invention aims to provide an electronic metering device centralizing the consumption data of a plurality of subscriber installations, in particular to facilitate the survey operations by reducing the duration of these operations and, if desired, to allow a teletransmission of this centralized data, for example via the switched telephone network or specialized telephone lines, to a data entry and billing center.

For this purpose, a counting device according to the invention is characterized in that it comprises
measuring probes respectively equipping the subscriber installations to each produce an analog measurement signal proportional to an instantaneous product consumption by the subscriber installation,
sampling means for cyclically sampling the measurement signals produced by the probes into temporally multiplexed measurement signal samples in time intervals having a predetermined duration,
analog-to-digital converting means for converting the multiplexed samples into instantaneous digital words, and
consumption meters respectively assigned to the subscriber installations and cyclically addressed by the sampling means to totalize the consumption by the subscriber installations, each of the counters being incremented cyclically by a value indicated by the corresponding instantaneous consumption word word at the subscriber facility to which the meter is assigned.

According to another aspect of the invention, since the amplitude of the measurement signals is not compatible with the operating limits of electronic circuits intended to precisely evaluate the consumptions of the installations, it is preferable to provide an analog-digital conversion of the samples. multiplexed, in different quantization ranges.In this case, the digital-to-analog conversion means comprise
quantizing means defining quantization ranges having increasing widths in a predetermined linear progression for compressing each of the multiplexed measurement signal samples into a calibrated sample having an amplitude proportional to the quotient of lp division of the difference between the amplitude of the the measurement signal sample and the sum of the widths of the successive quantization ranges smaller than the amplitude of the measurement signal sample by a rank of the range framing the amplitude of the measurement signal sample, said calibrated sample having amplitudes less than the smallest width of the quantization ranges,
means connected to the quantization means for detecting the ranks of the quantization ranges respectively flanking the amplitudes of the multiplexed measurement signal samples, and
means for converting the calibrated samples into digital words,
said ranks and digital words forming said instantaneous consumption digital words incrementing consumption counters.

 According to a preferred embodiment, in a counting device according to the invention for measuring electrical consumption of subscriber installations connected to an electrical distribution network, for example single-phase or three-phase, the measurement probes each deliver as many measurement signals as phase wires distributed to the subscriber installations, each measurement signal being taken from a respective phase wire and having an amplitude proportional to a current supplied by the phase wire.

In order to measure in practice the electrical consumption as a function of the active power and, where appropriate, the reactive power, the counting device comprises
an additional measurement probe connected to the distribution network for cyclically producing samples of voltage measurement signals proportional to the voltages of the phase wires of the network,
first calculating means receiving the current measurement signal samples and the voltage measurement signal samples for producing during each time interval a digital word of value proportional to a phase wire voltage and to a sinusoidal function of a current-voltage phase shift in a subscriber installation, and
second calculation means for calculating during each time interval the instantaneous consumption digital word from the digital word and the rank provided by the analog-to-digital conversion means and the digital word provided by the first calculation means.

In such a counting device, it is desirable to continuously check the correct operation of the count. Indeed, the counting errors due for example to drifts of preset parameters or to defective circuits of the device are likely to cause significant billing errors, because a single device ensures the counting of consumptions for a large number subscriber installations
To prevent these operating anomalies, the present invention also aims to provide test equipment that can be permanently included in a counting device in order to control its operation and to facilitate the location of one or more circuits included in the device that is the cause of faulty operation.

For this purpose, a test equipment for a counting device according to the invention is characterized in that it comprises
means storing a test algorithm and cyclically controlled by the sampling means of the device for providing data and control words relating to test sequences determined according to the algorithm, and predetermined result words of the corresponding test sequences has a perfect operation of the counting device,
means receiving data words for producing test signals and injecting them at predetermined terminals of the counting device,
means receiving control words for taking from the counting device response words produced in response to the injected test signals respectively,
means receiving the result words and control words for comparing the response words taken from result words corresponding to the test signals to indicate a malfunction of the counting device when a difference between said response words and result is greater than a predetermined threshold, and
means controlled by the means for comparing and the means for providing for storing in chronological order index words supplied by the means for supplying and indicating faulty circuits in the counting device.

A counting device according to the invention has the advantage of counting the consumption for a number of high subscriber installations, of the order of 600 in the case of the counting of electrical energy consumption in a network. A single-phase distribution device A device according to the invention can be used for the counting of consumptions varying very significantly from about 1 to 104 and this with a relative accuracy that can be greater than 10 4. Moreover, the same counting device according to the invention comprising suitable measurement probes can be used to account for different types of consumption, such as for example consumption of electricity, gas, water etc.
Other advantages and features of the invention will appear more clearly on reading the following description of several preferred embodiments of a counting device according to the invention with reference to the corresponding appended drawings in which
FIG. 1 is a block diagram of a metering device according to the invention for a three-phase electrical distribution network
FIG. 2 shows a sequencing performed in the device to sample measurement signals provided by the probes;
FIG. 3 shows in detail a preferred embodiment of a current measuring probe and a current switch included in the device.
FIG. 4 shows in detail an embodiment of a voltage measuring probe and, in the form of a block diagram, a circuit for calculating U. cos W and U sin F included in the device
FIG. Figure 5 shows waveforms of signals produced in the computing circuit of U. cos W and U. sin W
FIG. 6 shows a preferred embodiment of a calibration and analog-to-digital conversion circuit included in the device.
FIG. 7 shows a simplified equivalent schematic of a current calibrator included in the calibration and analog-to-digital conversion circuit shown in FIG. 6;
FIG. 8 shows the response of said calibrator as a function of the amplitude of an incoming measurement current sample;
FIG. 9 is a block diagram of a digital computer included in the device; and
FIG. 10 is a block diagram of the test equipment according to the invention.

With reference to FIG. 1, the counting device according to the invention for a three-phase electrical distribution network comprises
J current measuring probes, 71 to 1J, where J is a predetermined integer, a current switch 2, a sampling address decoder 3, a sampling bit counter 4, a voltage measuring probe 5, an active and reactive power calculation circuit 6, energy consumption counters and associated fault memories 7 and 8, and a tester 9.

Each of the current measuring probes has a subscriber installation connected to a three-phase line AT of the electrical distribution network and is placed in the head of the installation, in the same way as the individual electricity meters are at present. For each subscriber installation, phase wires P1, P2, and P3 and a neutral wire N are distributed through a current measurement probe to the installation. Each of the probes 1 to 1J, such as the probe 1j, where j is an integer between 1 and J, comprises three measurement outputs 11 ;, 12j, and 13. respectively supplying three measurement currents i1j, i2j, i3j constituting current measurement signals representative of the phase currents in the wires P1, P2, and
P3.The measuring currents ilj, i2j, and i32 are provided by the probe and respectively represent the current in the wire P1, the current in the wire P2, and the current in the wire P3. The measurement outputs 111, 121, 131, 11j, 12j, 13j, ... 11J, 12J, 13J, probes 11 to 1J are connected to corresponding current inputs of the switch 2.

The function of the current switch 2 is to switch to a current output 23 a single selected measuring current i among the possible current currents, at 11 to 13, delivered respectively by the probe outputs 111, 121, 131, ... 11j, 12j, 13j, ... 11J, 12J, 13J at current inputs 2111, 2121, 2131, ... 211j, 212j, 213j, ... 211J, 212J, 213J of switch 2. The Measuring currents supplied by the probes at 15 are successively selected each one during a time interval IT approximately equal to 1/10 s. Selection inputs 2211, 2221, 2231, 221j, 222j, 223j, ... 221J, 222J, 223J respectively respectively and cyclically select the current inputs 2111, 2121, 2131, ... 211j, 212j, 213j, ... 211J, 212J, 213J.A logic determined "0" applied for example to the selection input 22 1j controls the passage of the measurement current ilj from the input 211J to the
Output 23. A selected current sample i is provided during the time interval IT at inputs 61Ea and 61Eb of the active and reactive power calculating circuit 6. The selection inputs 2211 to 223J are respectively connected to BS11 wires to BS3J of a current sample selection bus BS. The bus BS carries MS selection words having 3J bits. The words MS have. all one bit in active state "0"; the position of this bit in an MS word determines the current input of the selected switch 2. The words MS are delivered in the bus BS by 3 J parallel outputs, 31 to 3135, of the sampling address decoder 3.

 The decoder 3 is of known type. It receives by parallel inputs 32 consecutive MA address bit words, supplied by the sampling counter 4 through an address bus BA, and recognizes 3 J consecutive bit combinations each causing the active state to be set. 0 "of one of the selection inputs 2111 to 213J of the switch 2.

The sampling counter 4 is a modulo 3 (J + 1) binary counter. The counter 4 receives at a clock input 41 a pulse clock signal He at frequency Fe. The counter 4 has K outputs 421 to 42K connected to the address bus BA, K being an integer directly greater than or equal to log2 ( 3 (J + 1)). An address word MA comprises K bits, B1 to BR, which are respectively delivered by the outputs 421 to 42K. The bit B1 is the least significant bit of the word
MY ; the bit BK is the most significant bit of the word MA. The bits B 1 and BK determine, among the phase wires P1, P2 and P3, the one to which the measurement relates. the word MA selects each of the current probes through the decoder 3 and the switch 2, and is also applied to the tester 9. The tester 9 is cyclically addressed, like a current probe, during time intervals of the same duration. The counter 4 directly supplies the word MA to parallel inputs 91E of the tester 9 through the bus BA.

A timing diagram of an addressing sequence defined by the counter 4 is shown in FIG. 2. The clock signal He, shown at the top of the
Fig. 2, defines time intervals IT = 1 / Fe. J outputs I11 to 11J of probes 11 to 1J are successively selected for a duration equal to J.IT, and respectively during time intervals IT1l to IT1J.J outputs 121 to 12J are selected respectively during consecutive intervals IT21 to IT2J The J outputs 131 to 13J are selected respectively during consecutive intervals 1T31 to IT3J The tester 9 is addressed during time intervals ITt1, ITt2, and ITt3, respectively between the intervals IT1J and 1T211
IT2J and IT31, and after IT3J The sum of the intervals IT11 to IT3J and intervals ITt1, ITt2, ITt3 is equal to 3 (J + 1) .IT, duration of the addressing sequence defined by the counter 4.

 The voltage measuring probe 5 is connected in shunt to the three-phase artery AT and receives the three voltage phases and the neutral through the wires P1, P2, P3, and N, in order to produce three voltage measurement signals v1, v2, v3 each indicating a voltage amplitude in the phase wires P1, P2, and P3 respectively, as well as a phase reference. The probe 5 receives in parallel the bits Bu ~ 1 and BK of the address word MA by inputs 52 connected to the outputs 42K-1 and 42K of the counter 4.The state of the bits BK 1 1 and BK allows the probe 5 determine the phase being measured; a sample of a voltage measurement signal v corresponding to a signal v1, v2, or v3, is selected by the bits BK-1 and BK and supplied via an output 51 of the probe 5 to an input 62Ea of the circuit 6.

 The active and reactive power calculation circuit 6 comprises a digital computation circuit 6a of U.cos W and U sin W, a calibration and analog-to-digital conversion circuit 6b, and a digital computer 6c. The computing circuit 6a receives respectively at the inputs 61Ea and 62Ea the samples i and v, and supplies respectively by the outputs 61Sa and 62Sa to the computer 6i, digital words representing products U. sin W and U. cos W, where U is the voltage of the phase being measured and E a current-voltage phase shift in the subscriber installation for this same phase. A period control on a pulse signal generated in the circuit 6a from current i makes it possible to check for proper electrical insulation between the current probes.

An output 63Sa of the circuit 6a delivers an alarm pulse when an insulation fault introducing a mixture of two or more measurement currents, for example at the outputs 11j and 12, of the probe 1j, is detected.

 The calibration circuit and analog-to-digital conversion 6b performs a calibration of the measurement current sample i previously to its analog-to-digital conversion. This calibration is made necessary by the wide range of measurement to be covered by the counting device. Indeed, the device must measure, for example in the case of a domestic installation, powers up to several tens of kW and that with an accuracy of 1/10 W. Such values impose a very wide range of quantification excluding the ability to simply use a conventional analog-to-digital converter.

 The circuit 6b delivers by outputs 61Sb and 62Sb respectively unmaxic words MC and MI. The words MC and MI represent the measurement current sample i converted into digital form. An output 63Sb supplies a calculation control pulse CAL to the computer 6C when the words MC and MI are presented by the circuit 6a to the outputs 61Sb and 62Sb. The word MC indicates a quantization range in which the word MI is located. which represents the value of the current sample i in this quantization range. Outputs 64Sb and 65Sb respectively indicate for the phase of the subscriber installation concerned, an overload fault and a lack of electrical continuity. This lack of electrical continuity can be due to, for example, an attempt by the subscriber to disconnecting from an output of the probe, a wire conducting a measurement current.

 The digital computer 6c delivers respectively by outputs 61Sc and 62Sc a digital active power word PA and a digital reactive power word PR representative of the products of the various parameters, current, voltage and cosW, and current, voltage and sinI.

The power words PA and PR are transmitted respectively in the buses
BPA and BPR to energy consumption meters 7.

 Each of the current probes 11 to 11 is associated with six energy consumption meters, at the rate of two counters per phase wire to total respectively the active energy consumed and the reactive energy consumed. The energy meters are addressed two by two by the words MA identifying the probe and the phase wire to which the measurement relates. In parallel with the words FA and PR, the computer 6c supplies the counters 7, via outputs 63Sc, the corresponding MA word, the latter having been previously read in the bus BA and stored temporarily during the duration of the calculation of the words PA and PR.

Fault memories 8 associated with the energy meters are also provided. Each of the current probes 11 1J also corresponds to three fault memories corresponding to the three phases and each memorizing the defects indicated by the outputs 65Sa, 66Sb, and 67Sb of the active and reactive power calculating circuit 6. The probe selection words MS are distributed through the selection bus
BS to the fault memories 8 to select, at each time interval fT the corresponding fault memory.

 The function of the tester 9 is to check the correct operation and the absence of drift of electronic elements included in the calculation circuit 6. A test algorithm is implemented in the tester 9 to control the execution of test sequences allowing the selection and identification of operating anomalies.

 The tester is optional and can be permanently included in the counting device. Execution of the test sequences takes place during time intervals ITt1, ITt2, and ITt3 However, other time intervals can be assigned to the tester to test the device with increased periodicity.

 In the tester 9, a clock pulse is generated during each of the time intervals ITt1, ITt2, and ITt3. This pulse is generated from the address word MA applied to the parallel address inputs 91E and advances the execution of the test sequences.

The tester 9 may be removable; it is then connected to the counting device only during maintenance operations. A clock input 92E is provided in the tester 9 to receive the bit
B1, delivered by the output 421 of the sampling counter 4, to control a fast execution of the test sequences during a maintenance operation. In this case of operation, the addressing inputs 91E are not connected to the bus BA and the inputs 32 of the decoder 3 are disconnected from the bus BA.

 During the time intervals ITt1 to ITt3 or during a connection of the tester for a maintenance operation, the tester replaces a subscriber installation and injects into the elements to be tested simulation test signals inducing known responses in the case of correct operation. An operating anomaly is detected by comparing the responses obtained and the expected responses stored in the tester 9.

 The test signals are delivered by outputs 93S of the tester 9 to be connected to various terminals of the circuit 6. An input port 94E of the tester is intended to receive corresponding response signals from the circuit 6.

In FIG. 1, are also shown a teletransmission link
Ld and a control wire Lc connected to the tester 9 as well as the energy consumption counters and fault memories 7 and 8. Indeed, the counting device can be managed by a management and maintenance center which controls, via the wire Lc, a reading of the counters and memories 7 and 8 and a retransmission of the measurement data and fault data in the link Ld.

 With reference to FIG. 3 are now described in detail a current measuring probe 1j and the current switch 2.

 In the probe 1j, three resistive shunts 141, 142, and 143 are placed in series respectively in the phase wires P1, P2, and P3 and each provide between their terminals a voltage proportional to the current in the phase wire. Primary isolating transformer windings 151, 152, and 153 are respectively connected in parallel with shunts 141, 142, and 143. Secondary windings of transformers 151, 152, and 153 feed conventional four-diode full-wave rectifier bridges. 161, 162, and 163 respectively. Positive voltage outputs (+) of the rectifier bridges 161 to 163 deliver rectified signals which are applied to PNP bipolar transistors transmitters 171 to 173, respectively. Transistors 171 to 173 have the function of avoiding any potential probe load adjustments to compensate for the resistivity of electrical connections between the probes and the circuit 6 through the switch 2, converting the signals provided by the bridges into measurement currents independent of link lengths. The measuring currents i1j, i2j, and i3j have rectified alternating current waveforms and are respectively provided by collectors of the transistors 171, 172, and 173 at the inputs 211j, 222j, and 223j of the switch 2 via the outputs 11j The polarization resistors 181, 182, and 183 respectively connect the bases of the transistors 171, 172, and 173 to a zero voltage reference terminal of the counting device.

 For each of the wires of the phases P1 to P3, a capacitor 191 to 193 is placed downstream of the shunt 141 to 143 between the phase wire P1 to P3 and the neutral wire N on the side of the subscriber installation so as to shunt 141 to 143 is crossed by a minimum i min current when the subscriber installation consumes no current. This arrangement is intended to obtain a measurement current i1j, i2j, or i3j greater than or equal in amplitude to a minimum current imini. A current i below this minimum current i is detected in the circuit 6b to signal, via the output 67Sb, a lack of electrical continuity in the corresponding phase wire.

 The current switch 2 comprises J elementary switches 241 to 24J respectively connected to the current probes 11 to 1. The elementary switch 24 is shown in detail in FIG. 3.

J
The elementary switch 24. essentially comprises three
J PNP type bipolar transistors, 241 to 243, associated with the phase wires P1 to P3. A resistor 951, 252, 253 connects an emitter of the transistor 241, 242, 243 to the reference terminal. A resistor 261, 262, 263 connects a base of the transistor 241, 242, 243 to the reference terminal. A diode 271, 272, 273 is connected directly between a collector of the transistor 241, 242, 243 and a connection conductor 28.

The conductor 28 connects all the collectors of the transistors in the elementary switches 241 to 24J at the output 23 of the switch 2. The base of the transistor 241, 242, 243 is directly connected to the selection input 221j, 222j, 223j. the emitter of the transistor 241, 242, 243 is directly connected to the current input 211; 212j, 213j, and receives the measurement current ilj, i2 ;, i3j A logic state "1" at the selection input 22 222j , 223j, blocks transistor 241, 242, 243; a logic state "0" at the input 221j, 222; 223je correctly polarizes the base of the transistor 241, 242, 243 which, unlocked, allows the passage of a current sample i proportional to the measuring current i1j> i2; , i3j to exit 23.

 With reference to FIG. 4, the voltage measuring probe 5 comprises three voltage transformers 531, 532, and 533 associated with the phase wires P1, P2 and P3 respectively.

 A primary winding of the transformer 531, 532, 533 is connected between the neutral wire N and the phase wire P1, P2, P3. A secondary winding of the transformer 531, 532, 533 feeds a four-diode rectifier bridge 541, 542, 543. A positive voltage output (+) of the rectifier bridge 541, 542, 543 is connected to a transmitter of a transistor 551, 552, 553, PNP type. A negative voltage output (-) of the bridge 541, 542, 543, is connected to the reference terminal. A base of the transistor 551, 552, 553, is connected to the reference terminal through a resistor 561, 562, 563, and to an output 571, 572, 573, of a decoder 57 through a resistor 581, 582, 583. A collector of transistor 551, 552, 553 is connected to the output 51 of the probe through a directly polarized diode.

 Rectifier bridges 541, 542, and 543 respectively produce measurement voltages v1, v2, and v3 having rectified AC voltage waveforms. The decoder 57 receives, through the inputs 52, the most significant bits BK 1 and BK of the address word MA supplied by the sampling counter 4. As a function of the pair of most significant bits, "00", or "01 ", or" 10 ", one of the outputs 571, 572 and 573 is activated by the decoder 57 to the state" 0 ". An "O" state at the output 571, 572, 573, controls the passage of a transmitter-base current in the corresponding transistor 551, 552, 553, which then operates in linear mode. A state "1" at an output 571, 572, 573, blocks the corresponding transistor 551, 552, 553. Thus during the addressing sequence thirds each having a duration equal to (J + 1) .IT, the transistors 551 , 552, and 553 are active and deliver samples v of voltage measurement signals v1, v2 and V3, respectively. A sample v represents the voltage of the phase being measured.

 The computing circuit 6a also shown in FIG. 4 comprises a shaping circuit 61a, an analog-to-digital converter 62a, a # / 2 63a phase shifter, two buffer memories 64a and 65a, and a period control circuit 66a.

The shaping circuit 61a receives through the input 61Ea the measurement current sample i. The shaping circuit 61a delivers an IP conversion control pulse whenever
The amplitude of the sample i supplied to the input 61Ea of the circuit 6a passes through a minimum. the circuit 61a is for example constituted by a voltage threshold comparator. An output 611a of the circuit 61a delivers the pulses IP. The pulses IP are applied through a
ss OR, OR6a, to a conversion control input 621a of the converter 62a and to an input 661a of the circuit 66a, and directly to an input 631a of the w / 2 63a phase shifter and to a load control input 641a of the buffer memory 64a.

The n / 2 phase shifter 63a is a known circuit. I1 delivers by an output 632a IP impulse corresponding to IP pulses
cs out of phase by n / 2. IP pulses are applied through the door
c
OR, 0U6a, at the input 621a of the converter 62a and at the input 661a of the circuit 66a, and directly at a load control input 651a of the buffer memory 65a.

 The analog-to-digital converter 62a receives at an input 622a the voltage measurement signal sample v. A digital word representing an instantaneous amplitude of the sample v is delivered by parallel outputs 623a of the converter 62a each time an IP or IP pulse is applied to the control input 621a.

sc
This digital word is provided through a BN bus at inputs 642a and 652a respectively buffer memories 64a and 65a. The memory 64a stores a digital word SIN delivered by the converter 62a consecutively to an IF pulse. The memory 65a stores a word
s digital COS issued by the converter 62a as a result of an IF pulse
c
the period control circuit 66a can be realized on the basis of a pulse detection device according to their duration as described in the patent application FR-A-2588965 of October 17, 1985 in the name of the current applicant. the circuit 66a supplies the output 63Sa with a logic state determined when the IP and IP pulses applied by
SC OU6a gate occur at an abnormal period, for example different from 5 ms in the case of a 50 Hz power distribution network.

In FIG. There are shown waveforms of a sample i, IP and IP voltage sampling control pulses, and
sc of a sample v. Samples i and v are shown respectively at the first and last lines of FIG. 5. Samples i and v are out of phase by an angle W. Each of the IP pulses, shown at
s second line of FIG. 2, control in the converter 62p the sampling of a voltage level proportional to U.sin W .Each of the pulses IPc, shown in the third line in FIG. 2, control in the converter 62a the sampling of a voltage level proportional to U.sin (W + n / 2) = U.cos W. The words SIN and COS therefore respectively represent the products U sin T and U.cos W
As shown in FIG. 6, the calibration circuit and analog-to-digital conversion at 6b comprises a current integrator 61b, a current calibrator 62b, and an analog-to-digital converter 63b.

In the circuit 6b, the integrator 61b receives the sample i as input and outputs a corresponding sample i
moy having the average amplitude of a sample i during the period 1 / Fe. It is recalled that the sampling period is chosen so that it covers several alternations of the measured alternating current in order to obtain a stabilized sample value. Sample i is provided
switcher avg 62b whose role is to reduce the amplitude of the sample i to a value falling within the limits of
operating mode of the analog-to-digital converter 63b.

 Calibrator 62b consists essentially of a cascade of P cells 62C1 to 62Cp, where P is a predetermined integer. The cell 62Cp is the last cell of the calibrator 62b and differs somewhat from the 62C1 cells at 62Cp11 which are identical.

Cell 62C, where p is an integer between 1 and P-1, offers
p an input 621C connected to an output 622C of the previous cell
p-1 622C and an output 622C connected to a. entry 621C of the
p-1 p + 1 next cell 62Cp + 1 A Zener diode 623C is connected between
p the input 621C and the output 622C, a cathode of the diode 623C being
P pp connected to input 621C. Three resistors in series 625c, 626c, and
ppp 627C constituting a voltage divider bridge are connected in series
p in this order from the input 621C to the reference terminal. A terminal
p common to the resistors 625C and 626C is connected to a transmitter of a
PP bipolar transistor 628C, PNP type. A base of transistor 628C
pp is connected to the output 622C. A collector of transistor 628C is
pp connected through a diode 629C forward biased to a link of
p output L62 of the calibrator 62b to which are connected, similarly, all the cells 62C1 to 62cep A first input of an AND gate 621 associated with the cell 62C is connected to a common terminal
pp to resistors 626C and 627C. A logic inverter 622 is connected
ppp between a first input of the AND gate 621 + 1 associated with the cell
p + 1 following 62C + 1 and a second entrance of gate 621
p + i p
The first cell 62C1 receives the current i at the input 621C A
the cell 62C1 is associated, not an AND gate, but a logic inverter 622 having an input connected to the common terminal to the resistors 626C1 and 627C1, and an output merged with the output terminal 65Sb of the circuit 6b. Between the input of inverter 622 and the reference terminal is a protective Zener diode 623.

In the last cell 62Cp, the anode of the Zener diode 623Cp is connected directly to the base of the PNP transistor 628Cp, and to the reference terminal through a resistor 624Cp and a diode of
Zener 624 in parallel. The anode of the diode 623Cp and the cathode of the diode 624 are connected to the input of the inverter 662Cp associated with the cell 62Cp, constituting the output 64Sb.

The invertor 622 delivers at the fault signaling output 65Sb a state "1" when a sample of the average current of measurement i is
This is less than the minimum current that must be supplied by a probe having a correct operation. A sample i equal to or greater than
maximum current i is detected by a state "1" appearing at the
Zener diode 624, which is connected to the fault signaling output 64Sb in order to write in the corresponding error memory 8 this state "1" signaling an overload of the subscriber installation concerned.

 All the elements common to the different cells 62C, that is to say the Zener diodes 623C, the transistors 628C, the resistors 625C, 626C and 627C, have the same characteristics and ohmic values. Zener diodes 623C have the same avalanche voltage Vz. The bridges formed by the resistors 625C, 626C and 627C have the same resistance value R equal to the sum of the resistance values of the resistors 625C, 626C and 627C.

The 628C transistors of the 62C cells have a negligible influence on the current balance of the 62C cells. Transistors 628C inject into line L62 a calibrated current sample i of which
c the amplitude is deduced from that of the sample i by a function
linear compression means predetermined by the characteristics of the elements components 62C cells.

In a state of equilibrium where p successive cells 62C1 and 62C2 to 62C are activated and receive respectively samples of
p incoming currents 1moy and ie2 to iep, the following cells 62Cp + 1 to 62Cp receiving no current sample at their input, the calibrated current sample i is injected in its entirety in the
c line L62 by the transistor 628C- of the last activated cell 62C
pp
The calibrated sample ic is then equal to K.iep, where K is a coefficient of proportionality of the same value for all the cells 62C, very small compared to 1, and fixed by the values of the resistors 625C, 626C and 627C and the gain of the transistors 628C very close to 1 (common base assembly).

In the cell 62C, injecting the calibrated sample i into the
pc line L62, the incoming sample has an amplitude less than one
current threshold i of the same value for all 62C cells. The
Zener diode 628C is not biased to the avalanche voltage Vz and
p blocks the passage of a current to the next cell 62C. The
p + i transistor 628C is forward biased, through resistor 625C,
p and injects into line L62 the calibrated sample i = Ki
c ep
The cells 62C1 and 62C2 at 62Cp-1 all receive, at their inputs, current samples i and i of greater amplitude.
mean e2 e (pi) at the threshold i. Zener diodes of these cells are all polarized
s to the avalanche voltage Vz. Transistors 628C1 to 628Cp-1 are not biased by base currents of sufficient amplitude and are blocked.

An equivalent pattern of cells 62C1 to 62C in this state
p of equilibrium is shown in FIG. 7.

As a function of the samples of current I1 to ip respectively crossing the resistance bridges R in the cells 62C1 to 62C
p can be deduced the following equalities i + i + i + + i + i = i
i 2 3 ft p av
il - i2 = Vz / R
i2 - i3 = Vz / R i3 - i4 = Vz / R i -i = VzIR
p-2 ft
i - i Vz / R,
where pz / r = i represents the current threshold of the cells 62C.

où encore, compte tenu que :

s
From these equals, follows the following expression imoy = ip + (ip + is) + (ip + 2is) + ... + (ip + (pl) is)

where again, considering that:

 The response of the calibrator 6b as a function of the amplitude of the imoy current sample is shown in FIG. 8, for P = 5.

The calibrated current sample i provided by the calibrator is always
including, regardless of the equilibrium state of the calibrator 6c, between O and
K.is; P = 5 consecutive compression ranges P i to P5 are defined in the calibrator 6b.

In the calibrator 6b, the compression ranges P1, P2 ..., Pp,... PP respectively have widths equal to is, 2is ... pi5, ... Pi. The
The plots P1 to Pp have increasing widths in a linear progression P1 P.

From the above, it appears that a current sample i
Avg is compressed into a calibrated current sample having an amplitude
c is the product of the quotient of the division of the coefficient of proportionality K by a rank p of the range P enclosing the amplitude of
p the current sample i and the difference between the amplitude of
av the current sample i and the sum-widths is, 2is, ... pis
with successive compression ranges smaller than the amplitude of the current sample i
Avg
The cell 62C delivering the calibrated sample i is detected at
Using the ET 6211 to 621P doors The ET 621 door associated with the cubicle
p 62C is the only one to supply a respective output with a logic state "1",
p the previous doors 6211 to 621P-1 being blocked respectively by the inverters 6221 to 622P-1 The AND gates 6211 to 621p deliver in a BC bus to P-1 son, the digital word MC indicating the range of quantification in which is located the word MI supplied to the computer 6c via the outputs 62Sb of the calibration and analog-to-digital conversion circuit 6b. The word MI represents the digital conversion of the calibrated current sample i. This conversion is carried out by
c the analog-digital protector 63b.

The inverter 622 delivers at the fault signaling output 65Sb a state "1" when a sample of the average current of measurement i is
lower than the minimum current i which must provide a probe having a correct operation. A sample i equal to or greater than the current
max imax i is detected by a state "1" appearing at the cathode of the Zener diode 624, which is connected to the fault signaling output 64Sb in order to write in the corresponding error memory 8 this state "1" signaling an overload of the subscriber installation concerned.

The calibrator 62b defines for the analog-digital converter 63b, P consecutive quantization ranges having increasing widths in a linear progression such that i8, 2i8, ..pi5,
s
Pi8, and corresponding to the P consecutive compression ranges of the calibrator 62b.

The analog-to-digital converter 63b comprises a sequencer 631b, D gates AND has two inputs 632b1 to 632bd D gates OR two inputs 633b1 to 633bd, D flip-flops 634b1 to 634bd of type RS, where D is a predetermined integer as a function of accuracy required for analog-to-digital conversion> 635b digital-to-analog converter> 636b current comparator, and 637b buffer
The sequencer 631b serves to produce a sequence of
D + 2 binary words MS1 to MSD + 2 necessary for the fast analog-to-digital conversion of the calibrated sample i provided by the
c calibrator 62b, in the representative digital word MI.

 The words MS1 to MSD + 2 are composed of D + 2 bits each and take respectively the values 1000 ... 00 to 000 ... 01 in which a single bit is in the state "1". The words MS1 to MSD + 2 are successively delivered by the sequencer 631b at the rate of a clock signal Hm, a word MSd delivered by the sequencer 63 lob, where d is an integer between 1 and D + 2, having state "1" only the (D + 2 - d) th bit from the lowest bit of weight. The clock signal Hm is synchronous with the sampling clock signal 11e and at a frequency Fm equal to (D + 2) .Fe, Fe being the frequency of the signal He controlling the sampling of the measurement currents supplied by the probes. During an IT sampling time interval of a probe measurement current, a sequence consisting of the words MS1 to MSD + 2 is thus outputted by the sequencer 631b.

 the sequencer 631b may for example consist of a modulo log2 binary counter (D + 2) receiving the clock signal Hm and successively addressing the words MS1 to MSD + 2 in a ROM-type memory, or more simply be constituted by D + 2-step shift register in which a single bit at state "1" is shifted one stage at each pulse of clock 11m.

Sequencer 631b provides the words MS1 to MSD + 2 by D + 2 outputs. First and second lowest weight outputs of the sequencer 631 respectively deliver a state-to-state pulse FC 1 to a load control input 6371b of the buffer memory 637b and the calculation control pulse CAL to the state "1". The pulse CAL is applied to reset inputs "O" R of the flip-flops 634b1 to 634bD and is supplied to the computer 6c through the output 63Sb of the calibration and analog-to-digital conversion circuit 6b. The remaining D outputs are connected respectively to first inputs of the AND gates 632b1 to 632bD and to the first inputs of the OR gates 633b1 to 633bD Second inputs of the AND gates 632b1 to 632bD are all connected to the output of the current comparator 636b. Outputs of the D AND gates 632b1 to 632bD are respectively connected to inputs of the state "I" S of the D flip-flops 634b1 to 634bD Outputs Q of the D flip-flops 634b1 to 634bD are respectively connected to the second inputs of the D gates OR 633b1 to 633bD Outputs of the D OR gates 633b1 through 633bD are respectively connected to D parallel inputs of the digital-to-analog converter 635b and to D parallel data inputs 6372b of the buffer memory 637b. A current output 6351b of the converter 635b is connected to an inverse input (-) of the comparator 636b and delivers a current level ir proportional to the digital value of the bit combination applied to the inputs of the converter 635b by the OR gates 633b1 to 633bD. direct input (+) of the comparator 636b receives the calibrated current sample i
c provided by the calibrator 62b. The buffer memory 637b provides the computer 6c the digital word MI representing the calibrated sample ic, by D parallel outputs connected to the outputs 62Sb of the circuit.
c calibration and analogue-to-digital conversion 6b.

The word MI is determined by successive approaches using D comparisons between D current levels ir delivered by the digital-to-analog converter 635b and the amplitude of the calibrated sample i
c
Since all the flip-flops 634b1 through 634bD are initially in the "0" state, in a first comparison, the word MS1 = "100 .. .000" is first provided by the sequencer 631b. The word MS1 is applied through the OR gates 633b1 to 633bD to the converter 635b and this then delivers via its output 6351b a corresponding current level ir1. If the current level iri is greater than the amplitude of the sample ic , the comparator 636b applies a state "O" to the second inputs of the gates 632b1 to 632bD, the AND gate 632bD is closed and prohibits the loading of the state "1" of the D + 2nd bit of the word MS1 = "100 ... 000 "in the 633bD flip-flop. If the current level ir1 is less than or equal to the amplitude of the sample ic, the comparator 636b delivers a state "1" which opens the AND gates 634b1 to 634bD and the flip-flop 634bD is consecutively written in the state "1""During a second comparison, the sequencer 631b delivers the word MS2 =" 010 ... 000 "and according to the result of the first comparison, the word MS2 =" 010 ... 000 "or the word MS2 + MS1 = "110 ... 000" is provided at the inputs of the 635b converter. The converter 635b delivers at the input (-) of the comparator a current level ir2 which is compared to the amplitude of the sample ic. The 633bD-1 flip-flop remains at
c D-1 state "0" or is written in state "1" according to the result of the comparison. The sequencer 631b then successively delivers the words
MS3 = "001 ... 000" to MSD = "00 100" and the remaining D-2 comparisons are made analogously. At the end of the D comparisons, the D flip-flops 634b1 to 634bD respectively contain the D bits of the word MI, from the least significant bit to the most significant bit. The sequencer 631b delivers the word MSD + 1 = "000 ... 010" in order to produce the pulse FC at state "1" controlling the loading in the buffer memory 637b of the word MI contained in the flip-flops 634b1 to 634bD
At the end of the sequence, the word MSD + 2 = "000 ... 001" is provided by the sequencer 631b in order to produce the CAL pulse at the "1" state.

The pulse CAL = "1" initializes the flip-flops 634b to 634bD for the next conversion. The calculator is informed by the impulse
CAL = "1" that the word MI is loaded in the buffer memory 637b and is present at the outputs 62Sb of the calibration circuit and analog-to-digital conversion 6b.

 With reference to FIG. 9, the digital computer 6c comprises a controller 61c, a time base 69c, an input buffer 63c, an arithmetic calculation unit 64c, and an output buffer 65c.

 The controller 61c receives at an input 611c the calculation control pulse CAL supplied by the calibration and analog-to-digital conversion circuit 6b. The controller 61c can be made for example from a 4-bit microprocessor. An internal memory of the controller 61c contains a program for managing the input buffer memory 63c, the arithmetic calculation unit 64c, and the output buffer memory 65c. The progress of the management program is synchronized with the reception of the CAL pulse. The time base 62c supplies the controller 61c with a clock signal H of a frequency much higher than the sampling frequency Fe. The clock signal H controls the execution of the management program.

Upon receipt of the pulse CAL, the controller 6c provides a control signal SC1 to write control inputs of the input buffer memory 63c. The signal SC1 commands the writing in the buffer memory 63c of the words SIN and COS supplied by the computing circuit of U.sin W and U.cosT 6a, words MI and MC supplied by the calibration and analog conversion circuit. -numerical 6b, and the address word
MA provided by the sampling counter 4 and indicating the probe and the phase wire to which the words SIN, COS, MI and MC written relate.

 The buffer memory 63c consists of 5 cells respectively containing the words SIN, COS, MI, MC and MA. The reading of these cells is controlled individually by the controller 61c. Under the control of signals SC2, SC3, SC4.and SC5 delivered by the controller 61c: the words SIN, COS, MI and MC are supplied to the arithmetic calculation unit 64c by the buffer memory 63c.

At first, the words MI and MC are transmitted to the unit 64c and this unit calculates the value of the current sample i from
Average of equality:

K and i being known constants of the unit p being given by
s the word MC and iC by the word MI.

The words SIN and COS are then transmitted to the unit 64c and this unit calculates the active and reactive powers PA and PR from the equalities: PA = Ci .U.cos W, and
Avg
PR = C.imOy.U.sin +
Avg
C being a known proportionality coefficient of the unit 64c and whose value has been determined following a calibration operation, U.cosT and U.sinY being given respectively by the words
COS and INS.

 The controller 61c provides the unit 64c with instructions and commands through an INS bus. When the calculation of the words PA and PR is completed after a maximum calculation time tc known to the controller 61c, a control signal SC6 is applied by the controller 61c to the input buffer 63c and to the output buffer 65c . The signal SC6 controls in the buffer memory 63c the reading of the word MA.

When the signal SC6 is supplied by the controller 61c, the words PA, PR and MA are loaded into the output buffer 65c to be transferred to the energy meters 7 via respectively the. 6jSc> 62Sc and 63Sc outputs of the 6c calculator.

 With reference to FIG. 10, the tester 9 comprises a test controller 91, a test sequence binary counter 92, a tester address decoder 93, an instruction word decoding and referral circuit 94, a first digital converter. current-output analog converter 95a, a second current-output digital-to-analog converter 95b, a digitally programmable phase shift circuit 96, a programmable threshold digital word comparator 97, a switch circuit 98, and a fault memory 99 .

 The test controller 91 may be a microprocessor type controller. In this controller 91 is included a program memory storing a test algorithm. This algorithm is composed of different successive test sequences for locating one or more defective electronic circuits in the counting device. Sequences make it possible to test, for example, the operation of the calibrator 62b, the analog-to-digital converter 63b (FIG.6), the calculation circuit of U.cos W and U.sin Y (FIG.4), and the calculation circuit. of active and reactive powers 6 in its entirety.

For each test, a test signal simulating the measurement current sample i, the calibrated sample i, or the sample i is
c moy injected into the calculation circuit 6. At least one of the words MI, MC, SIN,
COS, PA and PR, according to the circuit or the group of circuits to be tested, is read in the buses of the active and reactive power calculation circuit 6 and constitutes a response word RE to the test signal injected.

The word RE is compared with an expected response word stored in the controller 91.

A test of the calibrator 62b (Fig. 6) is based, for example, on the input injection 621CL of a direct current I constituting a
moy test signal whose amplitude is adjusted successively to be included in the different compression ranges defined by the cells 62C1 to 62Cp. By comparison of the MC words delivered and the expected words are determined the defective cell (s) of the calibrator.

A complete test of the analog-to-digital converter 63b (FIG 6) is performed by injecting into the link L62 leaving the calibrator 62b a current I adjusted successively to different levels and
c constituting a test signal. MI delivered words are compared to expected words. A test of the calculation circuit 6a (FIG 4) is performed by injecting at the input 61Ea a pulse current I constituting a test signal in order to simulate a measurement current sample i. The programmable phase-shifting circuit 96 makes it possible to phase out the current I of different angles 1>, ... ttc.

 Numeric words SIN and COS corresponding to the injected current I are delivered by the calculation circuit 6a and are compared with expected words to verify the operation of the circuit 6a. Pulse current I may also be modified in frequency to ensure correct operation of the period control circuit 66a included in the computing circuit 6a.

 In general, the localization of a defective circuit is performed following a direct test of the circuit or following a series of tests to locate the defective circuit by eliminating the circuits tested not defective.

 The controller 91 receives by parallel inputs 911 instruction word addresses stored in the controller 91. Each of the addresses is taken into account on receipt of a read command CL applied to an input 912. These addresses are supplied to the controller. controller 91 by the test sequence counter 92 at the rate of a clock Ht applied to a clock input 921 of the counter 92. The clock Ht can be provided by the tester address decoder 93 or be constituted by the bit B1 provided by the output 421 of the sampling counter 4 (Fig. 1) via the input 92E according to the operating mode. A three-way manual switch C93 is provided in the tester 9 to direct the appropriate clock signal to the clock input 921.

 The tester address decoder 93 receives via the inputs 91E the address word MA and delivers by an output 931 a clock pulse for each of the test time intervals ITt1, ITt2 and ITt3 (FIG.

2).

The test controller 91 delivers by parallel outputs 913 test instruction words MI to parallel inputs 941 of a decoding and switching circuit 94. An instruction word MT is divided into two fields a field of control. address and a data field respectively comprising an address word AD and a data word DO or command
CO. The address word AD selects in one of the output buses 942 to 947 of the addressing circuit 94 connected to the circuit of the tester 9 recipient of the data word DO or command CO. The decoding and switching circuit 94 also provides an output 948 with a control signal SC when a determined test command word is detected at the inputs 941.

The digital-to-analog converter 95a comprises parallel inputs 951a connected to the bus 942 of the switching circuit 94 for receiving DO1 words intended for it. A current output 952a of the converter 95a is connected through a diode D9a to the inverse input (-) of the current comparator 636b included in the analog-to-digital converter 63b (FIG.6) .When a word DO1 is applied to the inputs 95the test current I simulating the sample i
c is injected at the input (-) of the comparator 63b. This current I has a
c amplitude proportional to the numerical value of the word DO1.

The digital-to-analog converter 95b comprises parallel inputs 951b connected to the bus 943 of the circuit 94 for receiving DO2 words intended for it. A current output 952b of the converter 95b is connected through a diode D9b to the input 621C1 of the first cell 62C1 of the calibrator 62b (Fig. 6). The test current I simulating sample i is injected into the calibrator
moy moy when a word D02 is supplied to the inputs 951b.

The programmable phase-shifting circuit 96 receives, by parallel delay programming inputs 961, words DO3 supplied by the switching circuit 94 via the bus 944. An input 962 receives from a local oscillator, not shown, an OSC pulse signal at the same frequency as sample i, ie at least 100 Hz for an electrical distribution network at 50 Hz. The OSC signal is used to simulate a measurement current sample i provided by a probe. The signal
OSC is out of phase with an angle W depending on the word DO3. An output 963 of the circuit 96 provides the out of phase OSC signal to a transmitter of a PNP type bipolar transistor T96. A base of the transistor is connected to a control output 964 of the circuit 96. A collector of the transistor T96 is connected through a diode D96 to the input 61Ea of the calculating circuit of U.cos E and U.sin W (FIG. 4) and at the input 61Eb of the calibration and analog-to-digital conversion circuit 6b (Fig. 6).
T96 is unblocked and supplies by its collector the measuring current I when a given bit of the word DO3 in the "O" state is supplied by the control output 964.

The comparator 97 is a comparator as described with reference to FIG. 14 in the patent application FR-A-8614734 filed October 23, 1986 in the name of the current applicant. Inputs 971 and 972 receive data words DO4> called test sequence result word, and control words CO1 respectively provided by output buses 945 and 946 of the decoding and switching circuit 94. A word DO4 applied to the inputs 971 represents an expected response, for a correct operation of the device, following the injection of the current Ic, Imoy, or
I.The word CO applied to the inputs 972 programs in the comparator 97 a comparison threshold such that a difference of the current amplitudes represented by two words to compare D04 and RE is reported only if it is greater than the programmed threshold. Following a test selected via the circuits 95a, 95b and 96, a response word RE is delivered to parallel inputs 973 of the comparator 97 by parallel outputs 981 of the switching circuit 98. The words RE and DO are compared, and a state "1" is output from an output 974 of the comparator 97 when they differ beyond the programmed threshold.

The switching circuit 98 receives as input the words MI, MC, SIN,
COS, PA and PR. A selection control word C02 is supplied via the output bus 947 of the circuit 94 to selection inputs 982 of the switching circuit 98. The word C02 commands in the switching circuit 98 the selection of one of these words present at the input of the circuit 98 and its transfer to the parallel outputs 981. The word transferred by the switching circuit 98 constitutes the response word RE.

The memory 99 is of the FIFO type. The memory 99 receives by parallel inputs 991 the instruction word addresses delivered by the test sequence counter 92. The address present at the inputs 991 is stored in the memory 99 when a state "1" is supplied to a memory. write control input 992. This state "1" is delivered via an AND gate with three inputs ET9. The inputs of the AND gate 9 are connected to the output 974 of the comparator 97, to the output 948 of the circuit 94> and to the input 921 of the counter 92 to receive the clock Ht for synchronization purposes, respectively. The ET9 gate is opened by the signal
SC supplied by the circuit 94.

 The FIFO memory 99 stores in chronological order the addresses delivered by the test sequence counter 97 when a malfunction is detected. Since the test sequences take place in a chronological order programmed in the controller 91, it is easy from the addresses stored in the memory 99 to deduce the test sequence having detected a defective circuit. These stored addresses therefore constitute index words indicating one or more faulty circuits of the counting device. The control line Lc is connected to a read control input 993 of the memory 99 for controlling, on request from the maintenance center, the transmission of the stored index words to the remote transmission line Ld.

Claims (17)

 1 - Counting device for individually measuring consumption of a product by a plurality of subscriber installations, granted to a distribution network (AT) of said product, such as electrical energy, characterized in that it comprises  measurement probes (11 to 1J) respectively equipping the subscriber installations to each produce an analog measurement signal (il to iJ) proportional to an instantaneous consumption of product by the subscriber installation,  sampling means (2, 3, 4) for cyclically sampling the measurement signals (11 to 11) produced by the probes (11 to 11) into time-multiplexed measurement signal samples (i) in time intervals having a predetermined duration (IT)  analog-to-digital converting means (6b) for converting the multiplexed samples (i) to instantaneous consumption digital words (PA, PR), and  consumption counters (7) respectively assigned to the subscriber installations and cyclically addressed by the sampling means to total the consumption by the subscriber installations, each of the counters (7) being incremented cyclically by a value indicated by the digital word of instantaneous consumption- (PA, PR) corresponding to the subscriber installation to which the counter is assigned.  2 - Device according to claim 1, characterized in that the sampling means (2, 3, 4) comprise addressing means (3, 4) for cyclically providing addresses assigned respectively to the probes (11 to 1J) and a plurality of switching means (241 to 24J) controlled by the addressing means (3, 4) and respectively receiving the measurement signals (i1 to iJ) for cyclically sampling said samples in the measurement signals respectively, each of addresses cyclically addressing the consumption counter and the switching means assigned to the probe corresponding to the address during a predetermined time interval (IT) of the sample multiplexing cycle.  3 - Device according to claim 1 or 2, characterized in that the analog-digital conversion means (6b) comprise  quantization means (62C) defining quantization ranges (P1 to Pp) having increasing widths in a predetermined linear progression; for compressing each of the multiplexed measurement signal samples (i) into a calibrated sample (ic) having an amplitude proportional to the quotient of the division of the difference between the sample amplitude of the measurement signal (i) and the sum widths (i 2i65 ... (p-1) i5) successive quantization ranges (P1 to P1) smaller than the amplitude of the measurement signal sample (i) by a rank (p) of the the range (Pp) surrounding the amplitude of the measurement signal sample (i), said calibrated samples having amplitudes smaller than the smallest width (is) of the quantization ranges,  means (621) connected to the quantization means for detecting the ranks (p, MC) of the quantization ranges (pis) respectively framing the amplitudes of the multiplexed measurement signal samples (i) and  means (63b) for converting the calibrated samples (ic) into digital words (Ml),  said ranks (MC) and digital words (MI) forming said instantaneous consumption digital words (PA, PR) incrementing the consumption counters (7).  4 - Device according to claim 3, characterized in that the quantization means comprises a cascade of P analogous cells (62C1 to 62Cp) where P is a predetermined integer, receiving as input the multiplexed measurement signal samples (i), said cells (62C1 to 62Cp) respectively defining said quantization ranges (P1 to Pp) s the width of the quantization range defined by a p-rank cell (62CP), where p is an integer between 1 and P counted from the input (621C1) of the set of cells, being equal to the product of the rank p by the width (is) of the quantization range (P1) defined by the rank 1 cell (62C1).  5 - Device according to claim 4 characterized in that the cell (62C) defining a range of quantification (pop) framing  p p the amplitude of a measurement signal sample (imoy) applied to the input of the rank 1 (62C1) cell provides the corresponding calibrated sample (ic) to the means for converting the calibrated samples (63b).  6 - Device according to any one of claims 3 to 5, characterized in that the means for converting the calibrated samples (63b) comprise a fast D-type analog-digital converter successive compafaisons, where D is the number of bits the digital word output, at the end of each of the comparisons being determined the logic state of a bit of said digital word.  7 - Device according to any one of claims 1 to 6, for measuring electrical consumption of subscriber installations connected to an electrical distribution network, characterized in that the measurement probes (11 to 1J) each deliver of measurement signals (ilj to i3j) than of phase wires (P1 to P3) distributed to the subscriber installations, each measurement signal (i1j to i3j) being taken from a respective phase wire (P1 to P3) and having an amplitude proportional to a current supplied by the phase wire (P1 to P3).  8 - Device according to claim 7, characterized in that each of the measuring probes (11 to 1j) equipping the subscriber installations comprises by phase wire (P1 to P3), a shunt (141 to 143) in series in the phase wire (P1 to P3), a transformer (171 to 173) connected across the shunt (141 to 143), a voltage rectifier bridge (161 to 163) supplied by the transformer, and a transistor (171) powered by the rectifier bridge (161 to 163) and having a high output impedance electrode providing the current measurement signal (ilj to i3j) having a rectified AC waveform.  9 - Device according to claim 7 or 8, characterized in that each of the measuring probes (11 to 1J) equipping the subscriber installations comprises phase wire means, preferably in the form of a capacitor (191 193) connected between the phase wire and a neutral wire (N) of the installation for imposing on the corresponding current measurement signal (i1; i3j) an amplitude greater than a minimum amplitude (min)  10 - Device according to any one of claims 7 to 9, characterized in that it comprises  an additional measuring probe (5) connected to said distribution network (AT) for cyclically producing samples (v) of voltage measurement signals (v1, v2, V3) proportional to the voltages of the phase wires of the network,  first calculating means (6a) receiving the current measurement signal samples (i) and the measurement signal samples  voltage (v) for producing during each time interval (IT) a digital word (SIN, COS) of value proportional to a voltage (U) of  phase wire and to a sinusoidal function (sin W, cos W) of a  current-voltage phase shift (W) in a subscriber installation, and  second calculating means (6c) for calculating during each  time interval (IT) the digital instantaneous consumption word  (PA, PR) from the digital word (MI) and the rank (MC) provided by the analog-to-digital conversion means (6b) and the digital word (COS, SIN) provided by the first calculation means (6a). ).  11 - Device according to claims 8 and 9, characterized in  what the additional measuring probe (5) also provides by wire  of phase (P1 to P3) voltage measurement signals (V1 to V3) having a  rectified AC waveform.  12 - Device according to claim 10 or 11, characterized  in that the first calculation means (6a) comprise  means (61a) for producing, when the consumption to be measured  is a reactive power consumption, control pulses of  conversion (they) in response to amplitudes of substantially zero current measurement signal samples (i) to measure  reactive energy consumption (PR) of installations,  means (63a) for phase shifting said first pulses of  in second pulses (IPc) to measure consumption  active energy (PA) in installations, and  an analog-to-digital converter (62a) receiving a sample  of voltage measuring signal (v) and said first and second  control pulses (IPs, IPCs) to produce at each interval of  time (IT) said digital word (SIN, COS) of value proportional to a phase wire voltage (U) and to a sinusoid function (sin Y, W)  cos W) of a current-voltage phase shift (W) in the installation  corresponding subscriber.  13 - Device according to claim 10 or 12, characterized  in that the second calculation means (6c) are calculation means  numerals comprising arithmetic calculating means (64c) and means (61c) for managing and controlling the calculation flow  during each time interval (IT).  14 - Test equipment for controlling the operation of a  Device according to any one of Claims 1 to 13 for localising defective circuits in the device, characterized in that it comprises  means (91, 92, 94) storing a test algorithm and commands cyclically by the sampling means (2, 3, 4) of the device for setting data and control words (DO1 to D03, C01-C02, SC) relating to test sequences determined according to the algorithm, and predetermined result words (D04) of the test sequences corresponding to a perfect operation of the counting device,  means (95a, 95b, 96) receiving data words (DO1 to DO3) for generating test signals (I, 1moy 'I, Ic) and injecting them into  c predetermined terminals ((-), 636b; 621C1, 62C1; 61Ea, 6a; 61Eb, 6b) of the counting device,  means (98) receiving control words (C02) for taking in the counting device response words (RE) produced in response to the injected test signals (I, 1moy 'Ic) respectively,  means (97) receiving the result words (DO4) and control words (C01) for comparing the picked response words (RE) with result words (D04) corresponding to the test signals to signal an anomaly of operation of the counting device when a difference between said response and result words (RE, DO4) is greater than a predetermined threshold, and  means (99) controlled by the comparing means (97) and the providing means (91, 92, 93) for storing in chronological order index words provided by the means for providing (92) and indicating faulty circuits in the counting device.  Test equipment according to claim 14, characterized in that the means for producing test signals comprise current-output digital-to-analog converters (95, 95b) connectable to said terminals ((-), 636b; 621c, 62C1) of the counting device.  16 - Test equipment according to claim 14 or 15, characterized in that the means for producing test signals comprise digital-to-analog conversion means (95a, 95b) and programmable digital phase-shifting means (96) connectable to said terminals ((-), 636b; 621C1; 62CI, 61Ea, 6a; 61Eb, 6b) of the counting device.  17 - Test equipment according to any one of claims 14 to 16, characterized in that the means for comparing (97) comprises a digital word comparator in which is programmed (C01) said predetermined threshold by the means for providing ( 91, 92, 94).