FR2605826A1 - Connection equipment for subscriber terminals, linked to an ISDN digital switch - Google Patents

Abstract

This item of equipment is intended mainly to provide on its own for the setting up and handling of telephone communications which pass through it, without recourse to a central control unit common to conventional connection equipment included in the known switches. In particular, the recorder function 6 in the known switches is effected by the item of equipment, and the translator function is deleted. Indeed, the address BADT of of an item of destination equipment is the call number dialled into the subscriber terminal attached to the equipment and serves to route messages BMDT + BSVT within the switched network. Conversely, the call number of the item of equipment is transmitted, in the form of data BMDT, at the beginning of a starting communication, and is recorded BMDR in a call circuit 8 of the item of destination equipment so as to be retransmitted with the messages compiled by the item of destination equipment. The item of equipment can be fitted to any telephone and computerised telephone installation, whatever its operating throughput.

Description

Connection equipment for subscriber terminals
connects an ISDN digital switch
The present invention relates to a connection equipment in a digital telephone exchange connecting a subscriber terminal to first and second transmission media.

In particular, this equipment combines and complements an "asynchronous sorting system for self-routable digital messages" described in the French patent application.
No.86-08939 filed on June 20, 1986, not yet published and on behalf of the current plaintiff.

 The first support conveys first time division multiplex messages, some of which are developed and transmitted by the equipment according to signals and information, data or speech delivered by the telephone line serving the subscriber terminal. The second support conveys second time division multiplex messages, some of which are intended for the equipment and processed by the latter for the purpose of retransmitting in the line signals and information. The first and second messages developed and processed are thus exchanged through the transmission media between the equipment and another connection equipment during a telephone communication between them. The messages are routed in a switch and, more generally , in a service integration switched digital network (ISDN).

 Currently, connection equipment in known exchanges is not autonomous from the point of view of the messages or signals they have to exchange on the one hand with subscriber telephone systems such as terminals, local networks or the like, through the telephone lines, on the other hand with other local or remote connection equipment through the switched network.In fact, the connection equipment is managed by a central control unit of the automatic switch ensuring in particular the processing of the signaling to establish and terminate communications, assignments and markings of time slots or time slots relating to equipment in digital transmission media or multiplex between equipments and chants of arrival and departure switching, recording of numbers and their translation, and the taxation of communications.Thus the control unit centralises all the information relating to communications run by the connection equipment and decides itself the tasks to be performed by each connection equipment, tasks which are limited only to transmissions and receptions, encodings and decodings, recovery of rhythm, and tests mainly signals. In particular, the control unit comprises organs such as a recorder, a translator and a memory of the operating states of the connection equipment, which are very bulky, complex and expensive and whose tasks must be distributed sparingly in real time. between the connection equipment.

 In addition, the control unit is all the more complex as the number of connection equipment is large and the ISDN procedures are multiple, and all the more expensive as the flow of information passing through the equipment is high. and eligible. When equipment operates at different rates, the control unit must clearly distinguish these devices, and often assign them specialized routes in the switch.

 The present invention aims to provide an autonomous connection equipment which itself ensures the establishment and management of telephone communications that pass through it, regardless of any central control unit switch.

 Connection equipment according to the invention thus contributes to constituting a new type of switch that avoids the relatively slow operation of software and the complexity of marking time or wire paths in the central control units of the known exchanges, and in which the logic and decision-making power are no longer centralized but distributed in connection equipment. The connection equipment according to the invention does not exchange information with a central unit. As a result, switches comprising equipment according to the invention do not exchange information between them for the routing and management of communications. the semaphore function being included in elementary messages; these features mean that the time elapsing between the end of the dialing and the call tone transmission of the called party and setting the connection establishment time is less than one millisecond per switch crossed. These conditions allow the use of a virtually unlimited number of transit centers for the routing of communications and thus allows to develop, in terms of security, hyper-meshed networks. This new type of switch offers other performance and advantages that are presented in the patent application No. 86-08939 already cited.

 For this purpose, a connection equipment in a digital telephone exchange connecting a subscriber telephone line to first and second transmission media conveying first and second time division multiplexed messages, the equipment receiving line signals including of data to convert them into first messages transmitted periodically at a rate of a first message per time slot allocated to the equipment in a frame of the first medium, and the equipment detecting second messages which are intended for it in the second medium in particular to convert them into signals transmitted in the line, the first and second messages being capable of being received and transmitted by other asynchronous connection equipment of said equipment, is characterized in that it comprises means for detecting and recording a destination equipment address delivered by the line in order to transmit it e with first messages during a whole start communication, means for transmitting an address of said equipment with first messages during a call sequence of a start communication, means for detecting the address of said equipment in second messages conveyed by the second medium, and means for registering a destination equipment address in second messages containing the address of said equipment and for transmitting the registered receiving device address with first messages during a whole incoming communication.

 This last main characteristic of the invention shows that the functions of recorder in the known exchanges are provided by the equipment itself, and that the functions of translator are suppressed. Indeed, the destination equipment address is the dialed number in the subscriber telephone system and is used directly to route the first messages in the switched network; as a corollary, the address of said equipment is the telephone number of the equipment and serves to route the second messages in the switched network and detect them by the equipment. The means for recording the address of said equipment and the means for recording the address of the destination equipment are intended to record the call number of a calling subscriber for the whole time of a call and have no other role.

 According to other aspects of the invention, the establishment and the management of the communications passing through the equipment are obtained on the one hand, by the processing of signaling signals transmitted by the telephone line, on the other hand by service words identifying communication sequences and included in the first and second messages exchanged with the destination equipment. Thus, the signals are detected, managed and developed directly by the two pieces of equipment in communication, without the use of central switch control units and without involving a signaling network, and are such that they are permanently superimposed on the network. The measurement as well as that of associating each message with a destination equipment equipment address word contributes, according to a preferred embodiment, to the instantaneous bit rate of a 64 kbit / s link. or 136 kbit / s. However, given that all the means involved in routing and routing are not assigned, the availability of these resources during the most minute silence times, one millisecond and more, makes the flow rate convenient for a given time. full-rate telematic link is 136/2 = 68 kbit / s while for a telephone link this average bit rate is of even lower order due to the rhythm and punctuation of the speech.

 Furthermore, it should be noted that the structure and operation of a connection equipment according to the invention are not substantially modified when the subscriber line transmits signals at a base rate, for example 64 kbit / s , or signals at an integer multiple rate of the base rate, typically equal to 2qu64 kbit / s, where q is an integer between 0 and 12 inclusive. This feature allows terminals operating at one of these 13 speeds to use, regardless of their bit rate, the same subscriber connection equipment, knowing that this, after identifying the terminal and its speed, can automatically agree to this speed by logic control of changing its clock. The other equipment of the selection and transmission channel are not involved by this modification. Moreover, the structure and the principles used make it possible to very easily envisage a taxation based on the quantities of information actually exchanged regardless of any duration, a very important point. appreciable for ISDN networks.

Other advantages and features of the invention will appear more clearly on reading the following description of several preferred embodiments of the invention with reference to the corresponding appended drawings in which:
FIG. 1 is a block diagram of a switch including subscriber connection equipment according to the invention.
FIG. 2 shows a frame of time slots assigned to messages transmitted by connection equipment included in a stage of the automatic switch
FIG. 3 is a block diagram of an equipment addressing circuit relating to a stage;
FIG. 4 is a block diagram of a time base included in a connection equipment shown in FIG.
FIG. 5 shows timing diagrams of clock signals established by the timebase
FIG. 6 is a block diagram of a subscriber line connection equipment according to the invention
FIG. 7 shows in detail a number detection and recording circuit included in the equipment of the
Fig.6
- Fig.8 is a block diagram of a prefix comparison circuit and format determination common to the connection equipment included in a floor;
Fig.9 shows in detail a data transmission and service circuit included in the equipment of Fig.6;
Fig. 10 shows in detail a call handling circuit included in the equipment of Fig. 6;
FIG. 11 shows in detail a data and service reception circuit included in the equipment of FIG.
FIG. 12 shows in detail a memory with three registers of received data word and a read / write control circuit associated with the memory, included in the reception circuit of the receiver.
Fig.11
FIG. 13 shows timing diagrams of signals and operation established by the control circuit of FIG. 12; and
FIG. 14 shows in detail a programmable comparator included in circuits of the connection equipment of the
Fig.6.

 In FIG. 1 is schematically shown a telephone exchange comprising subscriber connection equipment EQ according to the invention. Each connection equipment constitutes a data termination equipment for connecting an LA subscriber telephone line serving a telephone subscriber installation, or more generally a telematic installation, with a SROU communication routing system constituting departure and arrival channels. of the automatic switch. The switch has an architecture and operation analogous to an "asynchronous sorting system of self-routable digital messages" described in the aforementioned French patent application No. 86-8939.

 In order to fix ideas, the main functions of connection equipment and their links with the routing system are first presented with reference to numerical values. As for the operation of the routing system, it is not within the scope of the present invention, and reference is made to the aforementioned patent application for more details on this subject.

 As shown in FIG. 1, the exchange comprises A autonomous stages of subscriber connection equipment ET1 to ETA.

All floors have an identical basic structure, and reference will be made later to the stage ET detailed in FIG.
a is an integer between 1 and A. The ET stage comprises B = 4096
a subscriber connection equipment EQ1 to EQB respectively connecting two-way two-way subscriber telephone lines LA1 to LAB to respective message transmission bus BT and message receiving bus BR connected to the communication system.
aa routing SROU.

Each equipment EQb, where b is an integer between 1 and
B, is primarily intended, when the line LAb conveys an analog signal, to convert an analog signal from the respective subscriber installation into a conventional PCM digital signal having a bit rate of 64 kbit / s and composed of sample bytes every T / 8 = 125 ps; reciprocally, in this case, a received PCM digital signal from the routing system
SROU, is to be converted by the equipment EQb into an analog signal to be transmitted in the line LAb. When the subscriber line Las is initially digital, it bi-directionally transmits PCM digital signals as defined above.

Secondly, the essential function of the EQB equipment is to form first MET digital messages to be transmitted on the BT bus to other so-called connection equipment.
to addressees, and to analyze second MER digital messages to be received by the BRa bus, transmitted by other equipment and intended for the EQb equipment. Other equipment may be equipment included in one of the stages ET1 to ET A of the switch, or equipment included in a remote switch and connected through the routing system. In the following, the letter T is assigned to words, messages and buses relating to transmissions from the equipment EQb through the bus BT, and the letter R is assigned to words, messages and buses relating to receptions in the equipment EQb through the bus
BR
at
Each digital message MET, MER comprises KM = 136 bits or bits transmitted in parallel and distributed as follows in three sub-buses of the bus BT, BR
- 16x4 = 64 bits form a call number, called destination address ADT, ADR, and- correspond to the coding of 16 digits in binary coded decimal code (DCB);
- 8x8 = 64 bits constitute a word of information MDT, MDR in which are included, after a sequence of call, data proper from the installation connected to the equipment EQb, respectively to the receiving equipment
- 8 bits constitute a service word SVT, SVR intended to identify a current sequence among predetermined sequences of a communication between the equipment EQb and the destination equipment.

For example, for a conventional telephone communication, a service word indicates a sequence of call, call return, busy or free recipient, data transmission, communication break, etc., depending on whether the EQb equipment is attached to a requesting subscriber facility, or to a requested subscriber facility. Other sequences relate to recent services offered to subscribers, such as temporary call forwarding, transfer of an absent subscriber call to another subscriber, call of a private station in an automatic subscriber installation of the subscriber. PBX type, etc ... Whether the subscriber equipment EQb is requesting or requested, the address word ADT, ADR in each transmitted message is composed of the recipient address identifier, according to the sense of transmission, the requested equipment or the requesting equipment.As will be seen below, an address word ADT, ADR is according to the invention, a recipient subscriber call number having at most 16 digits which is either dialed directly on the dial keypad or dial number of the calling subscriber's facility and read from a recorder of the requesting equipment, or read from a RAM of the called subscriber's equipment. The address word to be transmitted is not translated into the connection equipment and is used directly to select routes in the routing system
SROU to route messages from one communication to the other device. The information word MDT consists, during a call sequence by the requesting equipment EQb, of a call number AEQb having not more than 16 digits, identifying the calling equipment. This number coded in decimal code bit code is taken from a read-only memory of the equipment EQb, during the call sequence, so that the called destination equipment stores the calling number of the calling party in the random access memory and uses it in the addressing messages sent back to the requesting equipment EQb. After establishing a communication, each word
MDT, like each word HDR, is composed of K = 8 bytes corresponding in particular to 8 speech samples in PCM code.

As shown in FIG. 1, each group of subscriber connection equipment forming an ET stage is autonomous,
ie multiplexed time division messages transmitted by the equipment EQ1 to EQ8 in a transmission multiplex channel formed by the bus BT, independently and in a manner
has totally asynchronous message multiplexing in other equipment stages. The bus BT has RM = 64 + 64 + 8 = 136 wires
In the bus BTa, 64 first wires form a first sub-bus BADT to transmit in parallel the bits of each of the address words ADT, 64 second son form a second sub-bus BMDT to transmit in parallel the bits of each of the data words MDT, and 8 third wires form a third sub-bus
BSVT for parallel transmission of the bits of each of the SVT service words. Thus, for a data rate of d = 64 kbit / s, the bus BT has a bit rate Do = (d / (8xK)) B = 4096 kbit / s, which after
serializing the messages to be transmitted in a modem, if necessary, corresponds to a bit rate D '= Do.KN F 4.096 x 136 = O 557.056 Mbit / s. Each message transmitted by a device, such as the equipment EQb of the stage ETa, occupies a time slot ITb of channel having a width t0 = (0.125 / B) K = 244.1 ns and a predetermined rank b in a frame period T = 0.125 x K = 1 ms, as shown in Fig.2. Row b defines an address of the internal EQb equipment at stage AND
at
In the stage ET is thus provided an addressing circuit
a of equipment 1 to address by words 1 to B having log2 B = 12 bits equipments EQ1 to EQB, as a function of an autonomous clock at the frequency of f0 = 4.096 MHz, in order to multiplex B = 4096 messages transmitted by the equipment EQ1 to EQB in the bus BT a
The ET stage also includes a prefix comparison circuit
a and call number format determination 2 which is common to the equipment EQ1 to EQB and which will be described later with reference to FIG.

Likewise, the reception bus BR conveys frames having a
has a duration T = 1 ms and composed of 4096 time intervals having a duration of t0 = 244.1 ns and selectively assigned by the routing system SROU, according to the address words AnR, to messages intended for the equipment EQ1 to EQB . The BR bus includes a first
a BADE sub-bus for transmitting in parallel 64 bits of each of the address words ADR equal to one of the words AEQ1 to AEQB, a second sub-bus BMDR for transmitting in parallel the 64 bits of each of the HDR data words, and a third sub-bus BSVR for transmitting in parallel the bits of each of the service words
SVR.

As shown in FIG. 3, the equipment addressing circuit 1 essentially comprises a clock 10 establishing a clock signal at the frequency of f0 = 4.096 MHz, corresponding to the period of t0 = 244.1 ns, a counter modulo B = 4096, 11, receiving the clock signal f0, and two RAMs 12 and 13 connected to a 12-wire output bus of the counter 11 to produce the addresses in binary code 1 to B during each frame period T = 1 ms in an internal ADEQ 12-wire equipment address bus on the floor
AND .The logic circuits included in each EQ1 equipment at EQB
a are activated in response to the respective time interval IT1 to IT3 and are designed to best use the duration t0 = 244 ns, so that the sum of the operating times of these circuits plus a margin of safety does not exceed not this duration. In practice, there is a security margin of 34.1 ns, or about 15%, and a net time of 210 ns.

 The logic circuits can then be implemented as multilayer logic circuits typically comprising 14 layers, with components with an operating time of 15 ns, or 42 layers with components of 5 ns, in practice at 3 ns.

In order to have at most the theoretical time interval of 244.1 ns, the address counter 11 is arranged so as to mark on the address bus ADEQ, in all cases, stabilized information for a time also neighbor as possible of 244.1 ns. The counter 11 is a shift counter composed here of 12 flip-flops and is preferably an address counter.
Stabilized and Optimized Time Mark (MSOD). The offset address counter 11 receives by a clock input 11H the frequency f0 of 4.096 MHz. This is halved in a frequency divider 14 to provide a signal at frequency f0 / 2 = 2.048 MHz which is applied to a monostable time-constant flip-flop equal to t0.

 The flip-flop 15 calibrates the frequency signal fo / 2 into calibrated pulses having a width of t0 = 244.1 ns and a form factor equal to 1. The calibrated pulses are applied directly to read and write control inputs 12L and 13E of the memories 12 and 13 and, through an inverter 16, write and read control inputs 12E and 13L of the memories 12 and 13, respectively. The memories 12 and 13 receive in parallel the 12-bit address word of the counter 11, and have 12 outputs each connected to the address bus ADEQ.

 During a period t0 = 244.1 ns, in one of the memories 12 and 13 is read an equipment address while in the other memory is written the following equipment address, according to the natural order 1 to B. During the next period t0, the previous reading and writing are reversed. Thus, at the very short operating time of reading, the information present on the ADEQ address bus is stable for a time very close to 244.1 ns.

The B = 4096 addresses 1 to B of the equipment EQ1 to EQB are transmitted to time bases respectively included in the equipment so that the respective address of each equipment serves as a time reference for establishing the clock signals H1 to be necessary to the operation of the equipment. Thus, all the clock signals established in the equipment EQ1 to EQB are respectively identical, but are out of phase with each other from t0 to Bt. One, 3, of these time bases, included in the equipment
EQb, is shown in Fig.4.

The time base 3 essentially comprises a read-only memory
PROM 30 containing the binary address b at 12 bits of the equipment
EQb, a PROM ROM 31 containing an address AEQ'b corresponding to the binary coded decimal code of the address b and, having 4x4 = 16 bits and constituting a first part of the address AEQb,
I digital add-phase-shifter circuits 32 to 32ils and I digital comparison circuits 331 to 33, to produce the clock signals H1 = HI.

The memories 30 and 31 are fixed in a rack or rack of the equipment stage AND in which are housed cards of
circuit board supporting the circuits of equipment EQ1 to EQB.

Twelve parallel outputs of the memory 30 are connected to a 12-wire input bus 34 common to the circuits 321 to 32I through a first connection strip with male and female conductive elements 35. Sixteen parallel outputs of the second memory 31 are connected. through a second connection strip 36 to a 16-wire input bus serving an equipment address RAM 71 included in a data transmission and service circuit 7 and serving an address comparator. equipment 80 included in a call processing circuit 8, as will be seen in the following. As soon as the printed circuit board of the equipment EQb is plugged into the frame, the addresses b and AEQ'b are transferred to the circuits 321 to 32I and the RAM memory 71 and the comparator 80 of the equipment. These conditions advantageously confer interchangeability and standardization of equipment cards.

 When transferring the address b of the memory 80 through the bus 34, the adder-phase-shifter circuits 321 to 321 respectively add the address b to binary words representing phase shifts 91 to fI of the first pulses of the clock signals. H1 to HI with respect to the time interval ITb containing the address b in a frame T of the ADEQ bus.

By way of example, pulse rising edges of five clock signals H1 to H5 are shown in FIG. 5. The signal H3 is in phase with the time interval containing the address b I in the bus ADEQ, that is to say # 3 = 0, has a period of
T = 1 ms and pulse width equal to t0 = 244 ns, and is used to transmit first messages by the equipment
EQb.The signals H1, H2, H4 and H5 respectively have phase shifts of #r = 0, #r = 1000/16 = 62.5 ps, #r = -tr = -244 ns and rfr to the signal H3 , periods equal to T / 8 = 125 ps, with pulse widths equal to 60 μs, 60 μs, 244 μs and 60 μs.

The binary words representing the phase shifts 1 to #I are respectively equal to the number of time intervals between the appearance of the address b in a frame of the bus ADEQ and the establishment of the first pulses of the signals H1 to HI succeeding the address b, taking care that the additions in circuits 321 to 32I are congruent to B = 4096; thus the numbers O, 0, 4096/16 = 256, (4096/8) -1 = 511, and (4096/16) +1 = 257 are added to the address b to obtain the phase shifts of the signals H3, H1, H2, H4 and H5, respectively. In this manner, each clocking signal having respectively the same phase shifts with respect to the reference time slots 1T1 to ITB containing the addresses 1 B in the ADEQ bus is obtained in each connection equipment EQ1 to EQB. Such an arrangement makes it possible, in addition to the advantage of making all the equipment in the same standard and thereby making the equipment interchangeable, also to initialise a "mother" clock common to all the equipment in the AND stage. used to fix the
a phase shift of the clock signals between equipments in order to perform similar operations in the equipment and the multiplexing and demultiplexing of the messages in the LV buses and
at
BR
at
The comparison circuits 331 to 33I are intended to determine the periods t1 to t1 of the clock signals H1 to HI. Outputs 33S1 to 33SI of the circuits 331 to 33I are connected to monostable flip-flops having time constants respectively equal to the widths of the pulses of the signals H1 to HI. Twelve first inputs 33A1 to 33AI of the circuits 331 to 33I are connected to the circuit of FIG. addressing equipment 1 (FIG. 3) through the ADEQ bus, and twelve second inputs 33B1 to 33BI, circuits 331 to 33I are connected to parallel outputs of the circuits 321 to 32I. The comparison circuits are programmable comparators allowing bit-by-bit comparisons of two binary words for bits of these words having predetermined ranks. The predetermined ranks of the bits to be compared are indicated by states "0" in respective wires of third input buses having at most 12 wires 33N1 to 33NI circuits 331 to 33 ,, connected for example to dead memories wired. Such programmable comparators are described at the end of the present description with reference to FIG. 14.

Knowing that the clock signals H1 to H1 have periods equal to whole submultiples of the frame period T, it follows that a comparison made in a comparator is performed on a predetermined low-order bit number. a function of the ratio between the frame period T and the period of the respective clock signal. Thus, for the circuit 333 producing the signal H3, the comparison of the addresses 1 to B in the ADEQ bus and of the address b is performed on the 12 bits. For the circuits 331 332 '334 and 335 producing the signals H1, H2, H4 and H5, the comparisons are made on the 12 - log2 (1000/125) = 9 least significant bits of the 12 - bit words to be compared. More generally for a clock signal of period t T / 29, with O <q <12, the
q = = comparisons of addresses in the ADEQ bus and the phase shift word b + B / 29 mod (B) are performed on the 12 - log 2q = 12 - q bits of
2 low weight.

According to other embodiments of the invention, a connection equipment in an ET stage is connected to a subscriber line
a serving a terminal with a bit rate higher than the base rate of 64 kbit / s. Such high rates are equal to 2q x 64 kbit / s, with integer values of q varying between 0 and Q = 12, ie bit rates between the basic low bit rate of 64 kbit / s 12 and the high bit rate of 2 x 64 = 262 144 kbit / s. In this case, the addressing circuit 1 (FIG. 3) operates with a clock of frequency 4.096 × 2q = 16777.216 MHz to deliver addresses having Q + 12 = 24 bits in an ADEQ bus. At the input of the base of a device operating at the rate of 2qu64 kbit / s, a circuit neutralizes the ql most significant bits in the addresses of the bus ADEQ so as to transmit the address b of the equipment having here, Q + 12 + ( q-1) bits, at inputs 33B1 è 33BI of the comparators. These clock signals are then similar to those shown in Fig.5, but the period T is reduced to T / 2q. Thus, the connection equipment has a structure unchanged regardless of the rate of the subscriber line to which it is connected, and the operations it performs remain unchanged but are performed at faster speeds depending on the flow of the line.

As shown in FIG. 6, a subscriber line connection equipment, such as the EQB equipment, comprises, in addition to the time base 3, a control unit 4, a bidirectional coupling circuit 5 connecting the line from subscriber LAb to the equipment, a detecting and dialing circuit 6 connected to the coupling circuit and the sub-bus BADT for transmitting a called subscriber call number said destination address word
ADT, a data transmission circuit and service 7 connected to the coupling circuit and to the sub-bus BMDT and BSVT for transmitting the words MDT and SVT of first messages, a call processing circuit 8 connected to the buses BT and BR for mainly to receive
aa second call messages of other equipment and transmit first messages in response to the call messages and detect the equipment address AEQb in the sub-bus BADR, and a receiving circuit 9 connected to the sub-buses BMDR and BSVR and the coupling circuit for processing second messages transmitted by other equipment in communication with the EQb equipment, and having data to be transmitted in the subscriber line
Preferably, as shown in FIG. 6, the control unit 4 comprises a sequencer 40 independent of all clocks, offering a very short sequence tripping time, of the order of 40 ns, and having a wired programming. Such a sequencer is described in the French patent application No.85-14531 filed on July 1
October 1985, not yet published, and on behalf of the current applicant.

This sequencer does not use a microprocessor and makes it possible to repeat sequences or groups of sequences or to skip them, in order to control the different possible scheduling of incoming and outgoing communications.

 The sequencer 40 constitutes the "heart" of the equipment and delivers commands in the form of logic signals to the circuits internal to the equipment EQb by output terminals 41, and commands in the form of an 8-bit service word SVT to the requesting or called equipment in communication with the equipment EQb via an 8-wire output bus 42 connected to the transmission circuit 7.The latter orders are respectively transmitted in response to commands received by input terminals 43 of the sequencer and delivered by the internal circuits to the equipment EQb and the equipment in communication; the commands established by the internal circuits of the equipment are logic signals applied directly to input terminals 43, whereas the commands established by the equipment in communication are in the form of an 8-bit service word SVR detected in the sub-bus BSVR by the receiving circuit 9 and decoded by a decoder 44 connected to inputs 43 corresponding to the various words SVR.

 According to a preferred embodiment, the sequencer 40 controls 28 = 128 input or output commands, this order number being clearly sufficient to trigger the different sequences of a start communication and an arrival communication. In the following, it is considered that an order received in response to a state "1" at a respective input terminal 43 triggers a corresponding sequence by setting "1" of the associated output terminal 41 and / or by reading an 8-bit read only memory included in the sequencer 40 and containing an associated service word SVT to be transmitted in the bus 42.In particular, the sequencer 40 receives a first input terminal 431 a state "1" delivered by a line signaling circuit 93 included in the reception circuit 9 to initialize a start communication following a line loop closure, or stall in the subscriber installation serving the EQb equipment, and by a last input terminal 43F connected through an inverter 45 to the terminal 431 a state "O" issued by the signaling circuit following a line opening or hang-up in a subscriber line. The various command signals received by the inputs 43 and delivered by the outputs 41 are listed during the description below of the various circuits of the equipment.

As also shown in detail in FIG. 6, the coupling circuit 5 comprises a double differential transformer for directing signals transmitted by the subscriber installation through the line Lq to a transmission channel VT connected to two terminals of FIG. entering the transmission circuit 7, and for directing signals transmitted by two output terminals of the receiving circuit 9 in a reception channel VR to the subscriber installation through the subscriber line
The differential transformer comprises first and second primary windings 511-512 and 521-522 connecting the wires L1 and L2 of the line LA to the terminals of a line balancer 53, respectively.A first secondary winding 541-542 is coupled to the winding 511-512 and is connected to the two aforementioned input terminals of the circuit 7 through two potentiometers 551 and 552 in the transmission path VT. Midpoints of the primary windings 511-512 and 521-522 are decoupled by a capacitor 56 and are respectively connected to the two aforementioned output terminals of the circuit 9 through the reception channel VR. The transformer also comprises a single secondary winding 57 coupled to the primary half-winding 521 in order to pick up the numbering frequencies transmitted by the subscriber installation in a numbering frequency detector 601 included in the circuit 6.

In accordance with CCITT recommendations (Advisory Committee
International Telegraph and Telephone), a telephone number has not more than 11 digits, the maximum number required to obtain international communication. However, the invention provides a call number containing an additional 5 digits, selected after a maximum of 11 digits of the telephone number, in order to merge the public telephone number of a private exchange, for example of the PABX type. , and the number of a supplementary extension served by the private exchange. The extension number does not affect the national numbering. In this manner is generalized and trivialized a direct selection of arrival communication in a called private switch.

 According to another application relating to connection equipment intended to serve all types of current and future terminals, the identification of the type of terminal and as a result of local networks and protocol procedures for exchanges between these networks and the equipment is performed on the base of a prefix included in the number at Il + 3 = 14 digits. This application can be combined with the numbering of private extensions, for example by reducing the two-digit extension number.

 As is known, the digits of the telephone number are coded in multifrequency code. Each digit corresponds to a respective combination of one of three first frequencies F1, F2 and F3 with one of four second frequencies F4, F5, F6 and F7, these frequencies belonging to the telephone frequency band, typically between 300 Hz. and 4 kHz.

 As shown in FIG. 7, the number detection and recording circuit comprises a detection and coding circuit 60 for detecting, validating and decoding the numbering frequencies transmitted by the line LAb, two number recording circuits. 61Co and 61SE service call and instruction call, and a prefix readout and validation circuit 62.

In the detector 601 of the detection and coding circuit are provided a feedback amplifier with a high input impedance, connected to the half-winding 57 of the differential transformer. Seven bandpass filters are connected to an output of the amplifier to detect the F1 to
F7. The high input impedance of the amplifier does not affect the balancing of the transformer and reproduces at a constant amplitude the frequency signals at the inputs of the bandpass filters. A detection of one of the frequencies F1 to F7 is translated by a "1" to one of the seven output terminals 60F1 to 60F7 of the detector 401 constituting an output terminal of the respective bandpass filter.

In the circuit 60, the terminals 60F1 to 60F corresponding to the
The first 3 frequencies F1 to F3 are respectively connected to three inputs of a first OR gate 6031 and to three first inputs of a binary encoder 604. Similarly, the terminals 60F4 to 60F7 corresponding to the second frequencies F4 to F7 are respectively connected at four inputs of a second OR gate 6032 and four second inputs of the encoder 604. An AND gate 605 has two inputs connected to the outputs of the OR gates 6031 and 6032. An output 6C6 of the gate 605 is in the state "1" when one of the predetermined combinations of two frequencies is detected. The encoder 604 delivers in a four-wire bus 607 a parallel 4-bit word characterizing a combination of first and second frequencies among twelve possible, and resulting from a binary decimal coding (DCB) of the digit or associated character.

 The invention also provides for distinguishing not only combinations of two frequencies or two frequencies, but also two-frequency periods in order to increase the possibilities of encoding multifrequency signals. For example, a dual frequency characterizing a number of a 16-digit number at most is transmitted by the subscriber installation for a predetermined duration AtCo A frequency characterized by an AtSE duration different from QtCo allows, once the line connected to one of special services automated servers such as automatic alarm clock, conference organization, request telephone accounting account statement or other, to address to this server with the only use of the telephone keypad, data necessary to define the requested service such as, for example, the date and time of waking, the numbers of posts to participate in a conference and the date and duration thereof, a PIN, identity and period concerned by an extract request account, etc.

This same inter-active procedure also applies when the requested operation is the responsibility of the subscriber connection equipment and does not require prior connection to a specific PLC server; such an operation consists, for example, in a provisional forwarding of a line, a grouping of PBX lines, an arrival communication filtering, a "red list" registration of the subscriber installation number by adding a confidential code, a prohibition of access to certain numbering zones or servers (restricted service) etc ... All these operations and others which, until now, were carried out by operating agents can to be so by the subscriber himself, in the framework of new categories of new services of the type "Self Management" or "Tele-control",
As shown in FIG. 7, each of the recording circuits 61C0 and 61SE comprises two pulse detectors 611C0 and 611SE detecting pulses as a function of the Atco CO and SE durations respectively. Such detectors are described in the French patent application No.85-15418 filed October 17, 1985, not yet published, and in the name of the current applicant. The detectors 61C0 and 61SE are connected to the output 606 of the AND gate 605 and have outputs 612C0 and 612SE respectively connected firstly directly to circuit control inputs 613C0 and 613sue having four AND gates connected to the output bus 607 of the encoder 604, on the other hand, to clock inputs HCO and HSE of two 614CO and 614SE recorders through 615C0 and 615SE inverters, respectively. A state "1" at the output 612C0 or 612SE of a pulse detector thus validates the recording of the 4-bit word characterizing a frequency representing a call or communication instruction number. The recorder 614CO is constituted by four parallel shift registers having inputs respectively connected to the outputs of the four gates in the circuit ET 613coq and each comprising 16 flip-flop stages 61B1 to 61B16 in order to record a maximum of 16 digits of a call number communication, at the rate of the states "1" or clock pulses delivered by the output 612cl. The register 614SE is constituted by four parallel shift registers having inputs respectively connected to the outputs of the four gates in the circuit ET 613SE and each comprising 8 flip-flop stages in order to record a maximum of 8 digits of an instruction number. The recorders 614C0 and 614SE are reset by terminals RZC0 and RZSE respectively in response to a telephone communication break, such as hang-up of the calling party, and at the end of the transmission of a service instruction, under the control of the output of the inverter 45 in the control unit 4.

 The interconnections of the 614SE service instruction recorder with PLC servers do not fall within the scope of the invention. It will be considered in the rest of the description that the processing of a normal communication call number called "recipient address" of other equipment, for the establishment of a starting communication.

 The 16 x 4 = 64 outputs of the 614cl register latches are respectively connected to the 64 BADT address sub-bus wires through 64 AND gates in an output circuit 616 which are controlled by an output of an AND gate. two inputs 617. The gates in the circuit 616 are of the three-state type ("Tri-state") and are opened by a state "1" at the output of the gate 617; in the absence of a command, the output of a "tri-state" gate presents an infinite impedance regardless of the state "1" or "0" of the 614C0 register latch which marks its input. the inputs of the gate 617 respectively receive an end of numbering signal delivered by an output 41fn of the unit 4 and a clock signal H'3 to the frame period T = 1 ms delivered by the data transmission circuit and service 7 to transmit the ADT recipient address through the BADT sub-bus at the end of the dialing sequence and in each message to be transmitted MET during a start call after the dialing sequence.

 The prefix reading and validation circuit 62 of the equipment EQb and the prefix comparison circuit and format determination 2 common to the equipments EQ1 to EQB are shown in detail in FIGS. 7 and 8 respectively.

 The read and prefix enable circuit 62 includes a digit counter 620 having sixteen flip-flop outputs Q1 to Q16.

The outputs Q1 to Q6 are respectively connected to the first inputs of two-input AND gates 6211 to 6216. The counter 620 reads the first six digits consisting of a called destination number in the 614C0 recorder. for storing them in RAM 622 having 6 x 4 = 24 cells of one bit. It is recalled that in practice, the first six digits of the prefix of a call number determine, in addition to a part of the routing of the signals of a communication, such as message according to the invention, through the system of routing SROU (Fig.l), also the format of the call number that is to say the number of digits dialing the number. As will be seen below, the circuit 2 interconnected to the circuit 62 validates the prefix, that is to say checks if the prefix numbered corresponds to one of the prefixes according to the numbering plan in force and if the number of dialed call has a number of digits, called format, corresponding to the validated prefix. Such verifications are indispensable in order to definitively determine the end of the numbering sequence and to allow the passage to the next sequence for the purpose of establishing a starting communication.

 In the circuit 62 are also provided six circuits 6231 to 6236 each having four AND gates with two inputs. Each of the ET circuits 6231 to 6236 is controlled by an output of the respective gate 6211 to 6216, and has four inputs respectively connected to the equally ranked stages 61B1 to 61B6 in the four registers in the register 614cl.

 The counter 620 is reset at the end of communication at an input RZ62, by the output of the inverter 45 of the control unit 4, and is clocked by the digit detection pulses applied by the inverter 615C0 to a clock input H62. In response to the pulses at the input H62, a bit "1" is successively transferred in the stages of the counter 620, so that the outputs Q1 to Q16 successively switch from the state "0" to the state "1". For example, the detection of the first four digits implies that the outputs Q1 to Q4 are in the state "1" and the outputs Q5 to Q16 are in the state "0". When the seventh output Q7 goes to state "1", it blocks the gates 6211 to 6216 through an inverter 624. At this point, the first six 4-bit words recorded in the first six stages 61B 1 to 61B6 614CO recorder are written in the RAM 622, and the prefix in the memory 622 can not be changed by the recording of the other digits of the call number in the recorder 614C0 causing successive shifts of the first six digits , where appropriate, up to the last six floors 61Bll to 61B16.

 The buffer 622 is read-controlled by the clock signal H3 at the frame rate T. In response to the address b of the equipment EQb transmitted in the address bus ADEQ from the addressing circuit of equipment 1 and therefore to a pulse H3 delivered every T = 1 ms by the time base 3, the six prefix digit bit words in the memory 622 are applied to first inputs 20A1 to 20pop programmable comparators of prefix 201 to 20p included in the circuit 2, through a 6 x 4 bus = 24 BPR wires, as shown in Fig.8.

 Each comparator 201 to 20p, of the type described at the end of the description, is programmed and addressed by an operating and programming unit UEX included in the switch, in order to apply to a second word 20B1 to 20Bp a second word. prefix in DCB code, and third inputs 20N1 to 20Np states indicating the ranks of the digits of the prefix compare. These conditions contribute to an "open" numbering plan by validating a prefix not only according to the values of the prefix digits but also according to the rank of these digits in a six-digit number. In addition, each digit being represented by a 4-bit word, it appears that a digit makes it possible to consider 15 prefixes with 1 digit.

Such possibilities facilitate rapid changes in numbering plans as a result of telephone network developments.

 As long as a prefix is not recognized by one of the comparators 201 to 20p during the time interval ITb of t0 = 244 ns allocated to the equipment FQb in a frame of T = 1 ms, outputs 20S1 to 20Sp comparators are at "0". This occurs in particular when the prefix is being dialed and therefore stored in the RAM 622. On the other hand, as soon as the stored prefix is recognized by one of the comparators 201 to 20p, the output 20S1 to 20Sp of that It goes to state "1" to control the reading of an associated format memory. As shown in FIG. 8, the circuit 2 comprises 15 PROMs 222 to 2216, having recorded 15 format words. f2 to fl6 in DCB code of a call number having 2 to 16 digits. The outputs 20S1 to 20Sp of the comparators 201 to 20p are respectively connected to read control inputs of the memories 222 to 2216 so as to match a validated prefix with a number of digits or format of the expected call number. The connections between the outputs 20S1 to 20Sp on the one hand, and the inputs of the PROMs 222 to 2216 on the other hand, are practically achievable with the aid of a pluggable and modular printed circuit which allows both the implementation service of new prefixes and changes to the numbering plan.

The outputs of the memories 222 to 2216 are served by a four-wire BFO bus, all the connection equipment in ET terminal. They are connected to a 626 four-bit RAM memory included
a in the circuit 62 of the equipment EQb, and read-controlled by the clock signal H3. The 4-bit format word read in the memory 626 is decoded in a format decoder 627 having 15 outputs 62f2 to 62fil6. One of the outputs 62f2 to 62f16 is in the state "1" when the format f2 to f16 has been read in the respective memory 222 to 2216 during the time interval ITb of 244 ns assigned to the equipment EQb. outputs 62f 2 to 62f16 are respectively connected to second inputs of two-input gates ET 6282 to 62816. First inputs of the gates 6282 to 62816 are respectively connected to the outputs Q2 to Q16 of the digit counter 620. As soon as the number of digits received by the recorder 614C0 and counted by the counter 620 reaches the value stored in the memory 626 and indicates by the state "1" to one of the outputs 62f2 to 62fil6, the corresponding door 6282 to 62816 is open. In this case, an output of an OR gate 629 having inputs connected to the outputs of the gates 6282 to 62816 is in the "1" state, which marks the end of the numbering sequence at an input 43fn of the sequencer 40. , the gates 6282 to 62816 validate a call number by a comparison of the number of digits dialed, transmitted through the line LN, and the number of digit1 or format, corresponding to the valid prefix of this number.

Following the marking of the input 43fn, an output 41fn of the sequencer 40 sets "1" an input of a two-input OR gate 616 included in the recording circuit 61CC. The gate 616 has another input connected to the output 612Co of the pulse detector 611c1, and an output connected to the input of the inverter 615Cc, as shown in FIG. The state "1" at the terminal 41fn then blocks the gate 616 and prevents accidental modification of the call number, called destination address ADT, recorded in the recorder 614CO, after the dialing sequence. The 614CO recorder then functions as a read-only memory to be read at each message transmission in the BT bus under signal control.
at H'3. Indeed, the output 41fn in state "1" opens the read gate 617 of the recorder 614C0 to apply pulses of the clock signal H'3 as soon as the end of the numbering sequence.

 As will be seen in the following, the signal H'3 is delivered in dependence on a silence detection circuit 74 (FIG 9) and is inhibited not only during the maize dialing sequence also during periods of silence during communication established in order not to transmit MET messages.

Thus, after validation of the recipient address ADT stored in the recorder 614C0, the OR gate 616 is blocked, which avoids any alteration of the registered address recipient, due to mishandling of the subscriber.

 Only a transmission of the ADT address allows an effective transmission of a MET message even if, moreover, the words MDT and SVT in the message are null. In the absence of the address word ADT, even if the words MDT and SVT contain significant information, these are lost as soon as they are recorded in the EQb equipment and thus do not unnecessarily load memories of this equipment.

 The call request situation is identified by an on-line loop and SVT and SVR void words that distinguish between line taps by the "calling off hook" and the "requested trunk". This situation marks a first sequence of the sequencer 40 which controls both the sending of the tone "invitation to dial" and the triggering of a timer of a duration of the order of 90 seconds for example. The detection of the first dialing pulse translated by a pulse collected at the output of the OR gate 616 causes the sequencer 40 to go to a second sequence. The latter stops the transmission of the "invitation to dial" tone and relays the action started by the first sequence at the level of the unlocking of the timer clock. The state "1" detected in 41fn (end of numbering) in a delay of less than 90 seconds controls the transition to a third sequence that resets the timer. On the other hand, if the timer counts the 90 seconds, either during the first sequence corresponding to a false call, or during the second sequence corresponding to a false numbering or to a numbering incident, the "invitation to dial" tone of the first sequence or the silence of the second sequence is replaced by a "dialing incident" tone. In the first case the user can dial without hanging up, and the sequence cycle continues and normalizes from the third sequence despite the superimposition of the tone " numbering incident "which must have no effect, given its frequency, on the good reception of the two-frequency numbering. On the other hand, optionally for this first case, and obligatorily for the second case corresponding to a numbering undertaken but incomplete or non-compliant, the user must hang up the handset of his station in order to initialize the recorder 614C0 and be able to correctly resume the numbering phase .

 With reference to FIG. 9, the data transmission and service circuit 7 essentially comprises eight buffer registers 701 to 708 for storing 8 consecutive bytes of data per se, two RAM memories 71 and 72 storing the call number or AEQb address of the equipment EQb, a message reading logic circuit 73, a silence detection circuit 74, and a service word stabilization and transmission circuit 75.

In addition, when the telephone line LA conveys a signal puremer.t analog or a digital signal modulated by a carrier frequency, the circuit 7 comprises as input, an analog-digital converter 76 having two inputs connected to the transmission path VT of the circuit The converter 76 converts the signal transmitted by the subscriber installation into the telephone line L4 into a conventional PCM digital signal consisting of bytes resulting from a sampling at the period of 125 ps determined by the signal. H1 clock established in the time base 3.Delaying the converter 76 is of the type of those described in the French patent application No.86-00305 filed on 10
January 1986, not yet published, and on behalf of the current applicant.

The converter 76 comprises a high speed acyclic quantization circuit according to the latter patent application allowing a continuous and instantaneous quantization of the analog signal relative to 256 steps or quantization levels. The converter 76 comprises, at its output, a read-only memory of PCM bytes addressed by outputs of the quantization circuit, at the rate of the pulses of the signal H. According to another variant, as indicated with reference to FIG.
FIG. 6, in the patent application No.86-00305, the quantization circuit may be common to several connection equipments, and be preceded by switching circuits respectively connected to the transmission paths of the equipment and addresses by the signaling signals. respective clock H3> provided that the period of the frame, such a time multiplexing, is compatible with the sampling period resulting from the high transmission rates likely to be applied to all or part of the equipment thus associated with the same quantifier. Again, any increase in transmission rate, compared to the basic rate of 64 kbit / s considered here, does not change the functional and structural characteristics of the equipment.

For an online rate of 2ex64 kbit / s, the sampling period is 125.2 (q l) ps.

 Whatever the analog or digital type of signal transmitted by the telephone line, the bits of each sample byte are applied in parallel by a serie-parallel converter, or a circuit equivalent thereto, included in the block 76 of FIG. 9, through an 8-wire bus 761, at between buffer registers 701 to 708 and at first eight inputs 740A of a programmable comparator 740 included in circuit 74.

The registers 701 to 708 each have eight stages and respectively record the eight byte bits of one byte in response to each write pulse provided by the clock signal H2 and applied to write control inputs 70E of the registers.

Thus, during a frame period T = 1 ms, eight consecutive bytes are written and accumulated in the registers 701 to 708.

8 x 8 = 64 outputs of the stages of the registers 701 to 70 & are respectively connected to the wires of the sub-data transmission bus BEST to transmit a data word composed of 8 parallel bytes in the time interval ITb of t0 = 244 ns assigned to the equipment EQb, in response to the respective clock signal H'3 after establishment of a communication. The clock signal H'3 has the same characteristics, period and width of a pulse, as the clock signal H3, is produced by the message reading circuit 73, as will be seen in the following, and is applied to read control inputs 70L of registers 701 to 708 by an AND gate 733 included in read circuit 73.

The silence detection circuit 74 comprises, besides the programmable data byte comparator 740 mentioned above, a gate
ET 741 having an input connected to an output 740S of the comparator 740 and another input connected to an output 41dr of the sequencer 40 through an inverter 742. The output 41dr is in the "1" state during a call or a hang-up of the requesting EQb equipment. A three flip-flop counter 743 in circuit 74 has at most eight states "1" at the output of gate 741 during a frame period T = 1 msec and is reset by a 743RZ input at the end of each period of time. frame. The comparator 740 detects the bytes of data in the bus 761 corresponding to quantization levels within a predetermined range of silence. The counter 743 counts such bytes during one frame, i.e., between two intervals ITb, in order to producing a signal at state "1" with a 743S output and inhibiting the transmission of eight successive bytes of a frame corresponding to quantization levels included in the silence range.

In order to better understand the operation of the silence detection circuit 7, reference is made to quantization bytes
PCM having bits b8, b7, b6> bg, b4, b32 b2, b1 having the following 8 meanings for quantization at 2 = 256 levels or quantization steps distributed symmetrically with respect to an average amplitude of 0 volts of a signal analog V having a peak voltage V
max
the bit b8 is a sign bit, such that b8 = "1" for V> 0 and b8 = "" if V <0,
bits b7, b6 and b5 correspond to one of eight quantization segments for O <V <V> and
max
bits b4, b3, b2 and b1 correspond to one of sixteen quantization steps in the segment identified by bits b72 b6 and b5.

Eight seconds inputs 740B and eight third inputs 740N of the comparator 740 are connected to the UEX programming and operating unit already mentioned. 740B inputs receive bits
B defining the range of silence to which bits of the same rank are compared in the bytes of data, respectively. The inputs 740N receive bits N in the state "0" to indicate the rank of the bits in the bytes of data that are to be compared. According to a first example, a range of silence having two steps on either side of the 0 volt, being the smallest silence range, is defined by N8 B7 B6 ss5 B4 B3 B2 B1, where B7 to B1 are bits of two first quantization steps to be compared; according to a second example, a range of silence having two pairs of steps on either side of the 0 volt is defined by N8 B7 B6 B3 B4 B3 B2
N1, or B7 to B2 are bits common to the four steps to be compared; according to a third example, a range of silence having two segments on either side of the 0 volt is defined by N B7 B
B5 N4 N3 N2 N1, where B7, B6 and B5 are bits common to the two steps to be compared; according to a fourth example, a range of silence having two pairs of segments on either side of the 0 volt is defined by N8 B7 B6 N5 N4 N3 N2 N1, where B7 and B6 are bits common to the four levels to be compared.

Each byte corresponding to one of the byte configurations determining the fixed silence range causes an identity in comparator 740 and sets s "1" to output 740S. The output 740S controls the counter 743, which, when it counted eight pulses corresponding to 8 bytes of the range of silence during a frame T corresponding to the formation of a message to be transmitted, raises to "1" the 743S exit. Counter 743 is reset by terminal 743RZ at each frame period T determined by the signal
In addition, the gate 741 and the inverter 742 inhibit the action of the silence detection circuit, in response to an order associated with requestor sequences, such as call sequence and hang up for example, or in the case of video or telematic links for which the range of "silence" corresponds to significant data and no longer to silences. The delimitation of the silence range is set by the UEX operating unit and by addressing the AND stage and the EQB equipment by this unit.
a unit. The ranges of silence may be identical for all the equipment or adapted to each of them according to technical criteria.

 Thus the silence detection circuit has two roles. The circuit 74 makes it possible to "recover" any silence equal to or greater than one millisecond and reduces, in the case of telephone communications, the load of the multiplexed transmission channels in the buses and routes of the SROU routing system by more than 50%.

Incidentally, the circuit 74 attenuates parasitic background noise of various origins in periods of silence, such as ambient or street noise in a telephone communication, or crosstalk of the distribution network. The circuit 74 is equivalent to producing an increase in the sensitivity threshold of the user's microphone during periods of silence.

The read circuit 73 comprises a NOR gate 731, three AND gates with two inputs 732, 733 and 734 and an inverter 735. The circuit 73 controls a simultaneous reading of three stored words.
ADT, MDT and SVT for composing a MET message to be transmitted during the time interval ITb of duration t0 = 244.1 ns assigned to the equipment EQb in a frame T, in response to a pulse of the clock signal H3, when such reading is enabled by the control unit 4 and the silence detection circuit 74. The NOR gate 731 has an input connected to the output 743S of the counter 743 and several inputs connected to outputs 41 of the sequencer 40 to prevent any message transmission for example during the transmission of signaling signals to the subscriber installation through the line L4, such as dialing signal, call signal, and call return signal . In addition, at least one input of the gate 731 is connected to the UEX operating unit to block any transmission of messages, for example during the maintenance test of the equipment EQb, or to control a suspension of the line either at the initiative of the operator is at the initiative of the user as part of the "self management" service. When a message transmission is allowed, the output of the gate 731 applies a "1" to an input of the AND gate 732 having another input receiving the clock signal H3, so that an output of the gate 732 delivers the clock signal H'3 controlling a message reading.

 As already said, the signal H'3 delivered by the output of the gate 732 opens the read gate 617 (Fig. 7) of the recorder 614C0 following a read permission corresponding to a state "1" at the output 41fn sequencer 40, for reading and transmitting the address word of the addressed destination equipment ADT. The output of the gate 732 is also connected to two-gate AND two-input control inputs 751A and 751B included in the circuit 75 for transmitting an SVT service word for BSVT purposes.

Finally, the output of the gate 732 is connected to first inputs of the AND gates 733 and 734 having outputs respectively connected to the read control inputs 70L of the buffer registers 701 to 708 and to control inputs 71L and 72L of the memories
RAM 71 and 72. Other inputs of the gates 733 and 734 receive through the inverter 735 and directly a command signal via an output terminal 4lapidé the sequencer 40 in order to transmit in the BMDT bus, addresses of equipment and in the memories 71 and 72 during a call sequence of a start call, or to transmit on the BMDT bus, 8 bytes of data read in the registers 701 to 708 during a conversation sequence of a For this purpose, the memory 71 stores the address word AEQ'b of the equipment EQb having 4 x 4 = 16 bits in DCB code delivered by the PROM 31, as already indicated in FIG. reference to Fig.4. The memory 72 stores the address word of the AND stage having
typically has 48 bits, programmed by the UEX operating unit.

Thus 16 + 48 = 64 outputs of memories 71 and 72 are connected to the sub-bus BMDT. In the following, the addresses of the equipment EQb and the stage AND are designated by "equipment address" AEQb.

at
It should be noted that the equipment address AEQ'b is used to identify the equipment EQb of the stage AND by the remote equipment
a when establishing a call and corresponds to the last four digits of the EQb equipment call number, while the floor address corresponds to the L1-4 = 7 digits not more than the number of the call and is only used for routing messages transmitted by remote equipment through the system
SROU, so that these messages arrive via the BR bus. Otherwise,
in practice, each stage ET1 to ET comprises 96 non-numbering equipment used for special functions relating to dedicated start lines, automatic maintenance, test circuits, etc. The address Equipment AEQb in the memories 31 and 71 is thus between 0000 and 3999 for the first stage; 4000 and 7999 for the second; 8000 and 11999 for the third; 12000 and 15999 for the fourth; 16,000 and 19,999 for the fifth; then resume the address numbering cycle in the second and third tens of thousands and so on.

This arrangement makes it possible to have a numbering plan presenting no "hole". PROM 31 on the rack side are marked accordingly.

 The service word stabilization and transmission circuit 75 comprises, in addition to the two AND gates 751A and 751B, a comparator 752 having two input buses 752A and 752B connected directly and through an eight delay line circuit 753 to the bus. output 42 of the sequencer 40. Outputs of the gates 751A and 751B are connected to eight-gate AND 754A and 754B control inputs having other inputs connected to the input bus 752A and 752B of the comparator and the outputs connected thereto. BSVT-bus through an 8-gate OR 755 circuit. An output 752S of the comparator 752 is connected to a control input of an AND gate 756 having another between receiving the clock signal H4. An output of the gate 756 is connected, through a monostable flip-flop 757, and respectively through an inverter 758 and directly to the control inputs of the AND gates 751A and 751B.

 The circuit 75 is intended to "stabilize" an SVT service word delivered by the control unit 4 with a view to its transfer into the sub-bus ESVT, in order to remedy an asynchronism between a message transmission MET triggered by the signal H'3 clock and a reading of the corresponding SVT word in the sequence 40. Indeed, given the random nature of any change of sequence, the moment at which a MET message must be transmitted, can coincide with the moment when the word SVT is being modified, and as a result, the word SVT read at this time may be inconsistent.

The input 752B of the comparator 752 receives an SVT word of the bus 42 after a delay greater than 2t0 = 488.2 ns, ie typically a delay of 500 ns, imposed by the circuit 753. Such a delay makes it possible to control the stability of a word SVT in the bus 42 especially at the moment of appearance of a clock pulse H'3 determining the time interval ITb. As shown in FIG. 5, the clock signal H4 has a "last" pulse in advance of t0 = 244.1 ns with respect to that of the clock signal H3 in each frame. If at the instant of the At the last signal pulse H4 the word SVT is stable for at least 500 ns, the output 752S is at "1", and the gate 756 triggers the monostable flip-flop 757 which produces a 500 ns slot to open the AND gate 751B; the pulse of the signal H'3 then passes through the gate 751B 244,1 ns later, to transmit the word SVT through the open circuit ET 754 B. However, if the word SVT is being modified at the moment of the last pulse of the signal H4, the gate 756 remains closed following a state "0" at the output 752S of the comparator 752; 244.1 ns later, the pulse of the signal H'3 opens the door 751A, the output of the monostable flip-flop 757 being in the state "0", and the modified word
SVT is read through the AND circuit 754A at a time which is significantly greater than the time of modification of the service word applied to the input bus 752A, given the delay of 244.1 ns of
H'3 with respect to H4. Thus, the transfer of an SVT word from the bus 42 to the BSVT bus is performed after the change of this word.

During an "apdé" call sequence triggered by a stall in the installation connected to the equipment EQb, the door 733 is closed and the AND gate 734 is open, so that the memories 71 and 72 transmit the signal. AEQb equipment address in the BMDT subbus. During this call sequence the registers 701 to 708 are not read because of the blocking of the clock signal H'3 by the gate 733; the content of these registers is not significant and corresponds to the digitized noises of the subscriber line. The address AEQb is used by the destination equipment to send back the EQb equipment, after registering the AEQb address and transmitting the AEQb address in the sub-bus
BADT connected to the recipient equipment, as will be seen in the following.

 As shown in FIG. 10, the call processing circuit 8 comprises a 16-bit address comparator 80, a memory write control circuit 81, a call receiving circuit 82, a response circuit, and a receiver. free subscriber 83, a subscriber response circuit occupies 84, and a subscriber response circuit transferred 85.

The circuit 8 is used to signal to a calling subscriber equipment remote the state of the requested equipment EQb, free, busy, or call number to transfer.

The comparator 80 serves to recognize among the second multiplexed messages in the bus BR, those intended for
to the EQb equipment, detecting the AEQb address in the sub-bus
BADR. As already said, the messages in the BR bus are routed
a by the routing system according to the address of the stage AND, and consequently, the comparator 80 detects only the last 4 digits of the telephone number of the equipment EQb corresponding to the address AEQ'b . For this purpose, the comparator 80 has first inputs 80A connected to 16 first wires of the sub-bus BADR, and second inputs 80B receiving the address AEQ'b delivered by the PROM 31 (FIG. 4). a call from the equipment EQb by another equipment, an output 80S of the circuit 80 applies a "1" to first inputs of three AND gates with two inputs 811, 812 and 813 and a three input AND gate 814 in the circuit 81.

Other inputs of the gates 811 and 812 are respectively connected to AND gate outputs with two inputs 820 and 824 included in the call reception circuit 82. First gates 820 and 824 are connected to an output of a door
OR 82T directly and through an inverter 822. An input of the gate 821 is connected to the input terminal 431 of the sequencer 40 which, as already said, is in the state "0" when the subscriber line LAb is open and therefore the subscriber installation is free. Other inputs of the gates 820 and 824 are connected to an output 823S of an incoming communication test comparator 823 having inputs 823B connected to a read only memory containing a service word identifying a call and inputs 823A connected to the sub-slot. -bus BSVR. During a call, the requesting equipment transmits in the sub-bus BSVR serving the EQb equipment, here requested, the call sequence word. If the equipment EQb is free, the output of an AND gate 824 is in the state "1" which opens the door 811. Under these conditions, a "1" at the exit of the door 811 marks the entry 43apar of the sequencer 40 corresponding to an incoming communication call on the one hand, to inhibit any action of the silence detector 74 by closing the AND gate 741 via the terminal 41dr, and on the other hand, to trigger the transmission of a tone call to the subscriber installation from the signaling circuit 93 in the reception circuit 9.

 Further, the output of the gate 811 is connected to a write control input 831E of a 64-bit RAM 831 in the circuit 83 to write the requesting equipment address received by the BMDR sub-bus into the memory 831. A read control input 831L of the memory 831 is connected to an output of an AND gate 833 having a link connected to an incoming communication call output terminal 4lapar of the sequencer 40> and another input receiving the clock signal H'3. The address word of the requesting equipment is thus retransmitted by the memory 831 of the equipment requested in the sub-bus BADT towards the requesting equipment. This retransmission is carried out during the entire communication during which the terminal 4apar is in the state "]", and the memory 831 is read as a read-only memory. Furthermore, during the call sequence of the incoming communication, a ROM 832 in the circuit 83 is read to transmit in the sub-bus BSVT a "free request" service word under the control of an AND gate 834. The gate 834 has an input receiving the clock signal E'3, an input connected to an output 41ar of the sequencer 40 which is in the state "1" during the incoming communication call sequence, and an output connected to a read control input 832L of the memory 832.In the requesting equipment, the reception of the word of "free inquiry" service triggers a call return tone, transmitted is by the sequencer of the requesting equipment while a call tone is transmitted from the signaling circuit included in the equipment request EQb following the state "1" to the terminal 43apar. The sequence "call return" then ends upon receipt by the requesting equipment of a service word "request response" transmitted by the equipment request EQb following the stall of the called subscriber.

If a message reaches the requested equipment EQb while a communication is in progress, the input 431 of the sequencer in the requested equipment is "1". The AND gates 820 and 812 are unlocked, and the output of the gate 812 applies a "1" to a second input of the AND gate 814 which is then open. The door
AND 814 applies a "1" to a write command input 840E of a RAM 840 included in the busy subscriber response circuit 83. In the memory 840 is stored the address of the requesting equipment received by the 64-wire sub-bus BMDR. In the circuit 84, the memory 840 is associated with an 8-bit ROM memory 841 containing a "requested busy" service word. The memory 840 makes it possible to memorize for a random duration and up to the return transmission of the message " busy request ", the address of the requesting device and retransmitting it in the time interval ITb, made available by a" milli-silence "of the current conversation, and assigned to the requested equipment busy EQb by the signal H3.

 The forwarding of a call to another equipment, depending on the occupation of the subscriber line in the case of a grouping of lines by PBX switch, and systematically in the case of a temporary transfer or transfer fall within the same procedure below.

 The occupation of the subscriber line is marked by a "1" at the input 431 of the sequencer 40 in the equipment requests EQb and therefore at an input of the OR gate 821, which implies a writing of the address of the requesting equipment in the memory 840 via the gates 820, 812 and 814. Moreover, in the circuit 85, a bistable flip-flop 850 having inputs S and R connected to the unit exploStation UEX, or possibly to a special control terminal of the CAB subscriber attached to a circuit dependent on the service word read in the recorder 614SE (Fig.7), has a Q output in state "1" when the subscriber is an ordinary subscriber, and in the "0" state when the subscriber facility is temporarily forwarded RT to another subscriber facility or is served by a private PBX exchange identified by at least two call numbers. grouped lines. In circuit 85, the Q output of flip-flop 850 is connected directly and through an inverter 851 to first inputs of AND gates 852 and 853 having other inputs connected to an output of an AND gate 854. The gate 854 has an input connected to the output 743S of the byte counter 743 in the silence detection circuit (Fig. 9) and another input receiving the clock signal 113. The gate 854 also opens the doors 852 and 853 outside. any period of data message transmission.

 Thus, for a call number transfer, the output of the gate 853 applies a "1" to a read input 855L of a RAM 855 that has registered a subscriber number of 64 bits to be substituted for the number. calling the equipment EQb following a write addressing 855E by the UEX unit or the subscriber control CAB, and a reading input 856L of an 8-bit ROM memory 856 containing a word of service called transfer.

The requested equipment EQb then retransmits the transfer call number and the transfer service word read in memories 855 and 856 via the sub-bus BMDT and BSVT, and the requesting equipment then proceeds to a call sequence. ordinary subscriber identified by the new call number after detecting the transfer service word. The temporary return RT in the requested equipment is also marked by a "1" at a second input of the OR gate 821, which also makes it possible to retransmit the address of the requesting equipment in the sub-bus BADT by reading the However, the output of the gate 852 is connected to a read control input 841L of the memory 841 and to an input of a memory. OR gate 842, the latter having another input connected to the output of the AND gate 853 and an output connected to a read control input 840L of the memory 840.

 When the equipment requested is an ordinary subscriber equipment, a "1" at the output of the AND gate 852 orders the reading of the memories 840 and 841 which respectively deliver the address of the requesting equipment and the service word " busy demand "in the sub-bus BADT and BSVT. No information is transcribed in the buffer registers 701 to 708 (FIG. 9) which, as already stated, remain empty and whose transmission of information will require a "forcing" of the silence detection circuit 74.

 When a connection equipment has to transmit a message, this transmission is carried out at a precise instant determined by the respective time slot assigned to it in the 4096-way frame. In order to transmit a "call return" message by the call processing circuit 8 to the requesting equipment, the invention provides for using the periods of silence of the called equipment that is in communication, for retransmitting messages. call back messages. These periods of silence that are at least a millisecond appear in a random manner, but in practice, these periods of silence appear statistically after a maximum delay of a few tenths of a second of a conversation. Such a delay does not pose as well. problem to transmit call-back message by a busy equipment through a conversation.

 On the other hand, in the case of full-duplex telematic links with high and constant bit rates, this delay may be high or even infinite.

For this case, one of the following three solutions can be selected
1) use of a timer after which, in the event of absence of reception of "call return" message, the requesting equipment switches to "requested busy" sequence to trigger the transmission of a tone or corresponding digital information to the requesting subscriber installation;
2) insertion in switched terminal mechanisms using uninterrupted transmission paths, artificial silences lasting substantially greater than one millisecond during a data transmission;
3) creation of a special semaphore stage with a transmission bus and an own address counter; this stage may be common to the 64 or more subscriber floors of the switch which sets the transmission sampling period of a "call return" message at 64 milliseconds, ie an average duration of 32 milliseconds of the delay. waiting for this message.

 The solution illustrated in FIG. 10 uses periods of silence to transmit, when they must letter, the "call back" messages. For this purpose, the clock H3 which controls the transmission of the MET messages in the requested equipment is controlled by the AND gate 854 whose opening depends on the state of the output 743S of the silence byte counter 743. The output of the gate 854 is connected to inputs of the AND gates 852 and 853 which, as already mentioned, are switched by the Q output of the flip-flop 850 which stores the subscriber category, Q = 1 for an ordinary subscriber and Q = O for a PBX or RT subscriber; the flip-flop 850 is positioned by the operator or the subscriber. The door 853 (PBX or RT subscriber) orients the reading set determined by the signal H3 to the memories 840, 855 and 856. The door 852 (ordinary subscriber) directs the the reading order of the signal H3 to the memory 840, and no mark of the sub-bus BMDT data transmission is operated.

 In both cases, ordinary subscriber or PBX subscriber or RT, a falling edge of the read command resets to 0 and clears the 64 bits in the memory 840 by a flip-flop 843 interconnected between the output of the OR gate 842 and an input 840RZ memory 840.

This state "O" in the memory 840 is maintained until new reception of a call message transmitted in the bus BR or by the
to the same requesting equipment for the duration of the call sequence, or by another equipment in the case where several call messages are practically simultaneous, that is to say occur during a frame of one millisecond; only the last call message preceding the pulse H3 is processed since it was last written in the memory 840 following the last identical read by the comparators 80 and 823. This is only after treatment and not reappearing of the aforementioned message stored during the following frames, that the call message which precedes it is processed in turn and so on.

Thus, the switch automatically handles simultaneous calls, even in very large numbers, with the only limit of the possibilities of admission of traffic of the subscriber floor in reception, or 4096 messages per millisecond for the whole of a subscriber floor AND
at
Furthermore, it should be noted that a read command H3 applied to the memory 841, or to the memories 855 and 856 (memorized number of the station to which a PBX or RT transfer is to be made), while the memory 840 is Zero causes the marking of the BMDT and BSVT sub-buses, but the absence of a recipient address does not imply, as will be seen later, any processing of the transcribed data so that it is lost and in no way affect the load on switching and transmission equipment.

In addition, messages are received by the BR bus
in a manner totally unreasonable with respect to the reading order derived from the clock signal H3. In order to avoid any simultaneity of the writing and reading operations, having in practice a probability of 1/4096, the reading order applies to the memory 840 by the door 854, via the doors 852 and 842, blocks the command The write-in method is applied through the gate 814, by means of an inverter 857 interconnected between the output of the gate 854 and a third input of the gate 814. The components 857 and 814 having an operating time obviously shorter than that of the 852 and 842 components giving the reading order, the blocking of the writing well precedes the reading order in the memory 840.The reading order therefore certainly applies to a stable phase memory; on the other hand, the blocking of the writing can itself occur during writing, the recipient address is altered and then gives rise to the issue of an erroneous message. This erroneous message arrives wrong with any recipient device. This has no effect since this recipient equipment is not itself in call sequence. In the following frames, the call messages, received by the equipment demandenormal, because of the very low probability of successive and consecutive repetitions of the writing-reading coincidences, are received and exploited normally. This results in no other disadvantage than the delay inflicted on this sequence, a delay of one or a few frames, that is to say of one or a few milliseconds. Without the write blocking inverter 857, the coincidence concerns a time interval of 244 ns in a frame of one millisecond, the mentioned probability of 1/4096; with the blocking reverser, the coincidence relates to the only tripping time of the blocking and reading components, ie approximately 15 ns. The probability of coincidence is thus reduced to (1/4096) x (15/244) = 1 / 66628 is 16 times less, hence its interest. It is therefore not necessary for the processing of call messages to provide an alternating read / write control circuit 91 whose role and operation will be described later, and which offers a rigorous solution to the problem of coincidence. read-write when these two functions are independent and apply to the same memory or register.

 Returning again to a normal call for which the equipment EQb is a free request equipment, translated by a "1" to the outputs of the AND gate 824 and 811, it will be noted, as explained below, that the memory 831 retransmits the address of the destination equipment, here requesting, in the BADT sub-bus with the messages during all the incoming communication, in a manner equivalent to the retransmission of the destination call number by the recorder 614ci (FIG. 7) during a start call.

 An arrival communication in the requested equipment thus begins by applying a "1" to the input 43a of the sequencer 40 connected to the output of the AND gate 811. This initializes a call sequence and triggers the transmission of a call tone in line LA through the already mentioned signaling circuit 93 included in circuit 9, as will be seen in the following. The stall of the subscriber requests, equivalent to the end of the numbering sequence for a start communication, and causing a supply voltage inversion in the line, does not open the door 6J7 (FIG. the register of the call number 614cl, since the terminal 41fn remains in the "O" state. The door 617.demeure closed during all the arrival communication in the equipment request. Although normally all the stages of the register 614C0 are "O" since the end of the last communication, all untimely manipulations of the keypad in the installation of the subscriber request that give rise to recording of 4-bit words in the recorder 614cl are ineffective since the read gate 617 is closed.

 Thus, during transmission of the call-request tone, outputs 41apar and 41ar of the sequencer are at "1" to read memories 83J and 832 via AND gates 833 and 834 and transmit the address of the calling party's equipment and the service word "free request" in the sub-bus BADT and BSVT in response to each pulse of the clock signal H'3. On stalling the called party, the terminal 41ar goes to "n" to block the AND gate 834, while the terminal 41apar remains in the state 1 during the entire arrival communication so that the address of the requesting equipment is retransmitted with each message to be transmitted to the requesting equipment. Thus, as soon as an incoming or outgoing call is established, the exchange and the composition of the messages is done in a similar manner in the requesting and requesting equipment, the exception of reading the address of the destination equipment which is made either from the memory 831, or from the recorder 614CO. In any case, after the call sequence, the equipment is in the busy state when receiving the data messages, and the AND gates 820, 824, 811, and 812 have "O" outputs. The outputs of the gates 8) 1 and 812 being connected to a second input of the gate 813 through a NOR gate 815 in the circuit 8], the gate 813 is at "1" in response to each data message detected by the comparator 80.

 Hang-up of the request or the requestor at any time causes the equipment attached to the subscriber who has hung up a resetting of the sequencer, following the application of a "Q" at the input 431 of this sequencer, and the transmission of a "00000000" service word to the other equipment to reset the sequencer in this equipment. In one and the other equipment, the inverters 45 in the control units 4 reset all the equipment returns, and output terminals 41 of the sequencers control, via the signaling circuits 93 and the channels R, the transmission of end of communication signals to the subscriber installations.

 Referring now to FIG. 11, the data receiving and service circuit 9 essentially comprises a buffer memory 90 having three 64-bit parallel registers 90os 9 1 and 902 for storing data words received by the BMDR sub-bus, a read-write control circuit 91 controlling the registers 900 to 9 2 an 8-bit random access memory RAM 92 for storing service words received by the sub-bus BSVR, the signaling circuit 93, already cited, for transmitting data. signaling signals and data signals in the telephone line LAbw and data coding means, indicated by the general reference 94, interconnected between the memory 90 and the signaling circuit 93 and selected according to the transmission criteria specified below. after.

The subscriber line signaling circuit 93 has two output terminals 931 and 932 connected across the decoupling capacitor 56 in the coupling circuit 5 (FIG.6) through the receiving channel VR. The circuit 93 comprises a line supply voltage reversal circuit at -48 volts on the one hand, to apply a direct battery voltage to the LN line when the subscriber telephone system is at rest and does not communicate. not with another remote subscriber installation, or when the subscriber installation exchanges signaling, such as tones and dialing signals, during the establishment of a call, and on the other hand, to apply a reverse voltage the battery voltage during an established call, for example during a conversation or data exchange sequence proper. In particular, the signaling circuit 93 interacts with the sequencer 40 (Fig. 6) via a line state output terminal 93S connected to the sequencer input 4-1, and terminals. signal injection control inputs 93C respectively connected to output terminals 41 of the sequencer.The output terminal 93S of the circuit 93 signals with an "O" the open state of line loop corresponding to a hook-up of the subscriber and by a "1" the closed state of the line loop corresponding to a stall of the subscriber to initialize the sequencer for the establishment of a start communication, by controlling the transmission of a dial tone. invitation to dial through circuit 93, via two connected terminals 41 and 93C. Other terminal pairs 41-93C control battery inversions for establishing or terminating incoming communication, in response to call service or call-back service words oigné, and injections of signaling signals such as call tone at 50 or 25 Ez, ringback tone, and charging pulses. These various signaling signals are applied to input terminals 93E of the equipment 93 connected to conventional signaling generators. In addition to these signaling signals, the equipment 93 also makes it possible to inject into the line, data signals via input terminals 93E under the control of signals applied to respective terminals 93C by outputs 41 of the sequencer. Data signals can be analog, digital with carrier frequency, or purely digital as specified below. A signaling circuit or equipment fulfilling the above functions is preferably of the type described in patent application No. 85-11392 filed on July 25, 2004.
July 1985, not yet published, and on behalf of the current applicant.

 As shown in FIG. 11, an 8-wire output bus common to the three registers 900 to 902 serves first inputs of two 8-door AND circuits 941 and 942 having control inputs connected directly and through an inverter 943 to the UEX operating unit or a logic control dependent on an identification circuit of the terminal in order to select, according to the validation illustrated, two transmission modes.

When the AND circuit 941 is selected, the data bytes are serialized in a 64 kbit / s 944 parallel-to-serial converter connected to an input terminal 93E of the signaling circuit. This latter terminal is associated either with a pair of terminals 41-93C for controlling the injection of purely digital data in line LAb, or with another pair of terminals 41-93C for controlling the injection of digital data modulating a carrier frequency predetermined in the LN line
When the AND circuit 942 is selected, the data bytes are applied to an 8-bit - 2x16-bit transcoder, 945, which converts each byte into a first 16-bit word having only one bit at state "1" whose rank indicates a first sample value among 16 first levels of a quantization law, and a second 16-bit word having only one bit in state "1" whose rank indicates a second sample value among 16 seconds quantization levels in the vicinity of said first sample value, the quantization law thus having 28 = 256 second quantization levels. The first and second words are applied in parallel to two "samplers" included in a modulated pulse modulator in duration 946 so that each byte is converted into a pulse having a predetermined width and modulating a predetermined carrier frequency, the pulse width being determined according to the first and cond quantization levels respective. Such a pulse modulator-duration module is described in the patent application No. 86-00357 filed January 13, 1986, not yet published, and in the name of the current applicant. As already said about the detectors of pulses 611SE and 611C0 (FIG 7), pulse duration modulations can increase the number of signals to be transmitted in a line, such as data, signaling or service signals, without increasing the bandwidth of the signal. line. The modulation in the modulator 946 depends on the clock signal H5 at the sampling period of 125 pss and the width-modulated pulses are applied to one of the input terminals 93E of the signaling circuit 93 provided to a pair of control terminal 41-93C.

According to other variants, when the data is to be transmitted in analog form, the transcoder 945 and the modulator 946 are replaced by a conventional digital-to-analog converter.

All service words SVR received in the sub-bus BSVR, other than the call service words which are processed separately, by the circuit 82 (Flg.lO), due to the fact of their possible appearance at any time , are written in the buffer memory 92. The entries in the memory 90 and in the memory 92 are made under the control of the AND gate 820 (FIG. 10) via, in particular, the gate
ET 813 having an output connected to write control inputs 90E and 92E of the memories 90 and 92. The stored service words are read in parallel in the memory 92 by the decoder 44 included in the control unit 4 (FIG. 6). The decoder 44 comprises, for example, comparators associated with word-of-service memories and having outputs connected to respective inputs 43 of the sequencer 40, or a matrix crossing the 16 combinations of the first 4 bits of the SVR byte with the 16 combinations of the last 4 bits and thus having the 256 outputs usable to the sequencer.

 Before describing in detail the read-write control circuit 91 with reference to FIG. 12, certain characteristics of the routing system SROU (FIG. 1) according to the French patent application No. 86-08939 which imply the constitution of a memory of received data 90 by three parallel registers 900, 901 and 902 and correRativement particular addressing write-read of this memory.

 The routing system is composed of a plurality of routing circuits interconnected by roads which are of the same type as the transmission and reception buses BT1 to BT A and BR1 to BR.

Each route is composed of 4096 time division multiplexed channels each occupying a time interval of t0 = 244 connected ns during a frame T = 1 ms. Each routing circuit is inputted to a route from which the routing circuit retrieves messages for retransmission on a route or multiple routes based on the recipient addresses included in the messages. The routing circuits, like the stages ET1 to ETA, are independent of each other, that is to say completely asynchronous, and each comprise a channel addressing circuit at the frame period similar to the circuit i (FIG. .3) .In addition, in each output route of a routing circuit are initially allocated a predetermined number of useful channels less than 4096, for example equal to 64, in which channels are inserted messages taken from the route of the route. Entrance.

 However, messages of the same communication are not necessarily transferred in the same way of an exit route; in fact, the channels in an output route are cyclically addressed to the frame period in the routing circuit, starting with the ordinal rank address O up to the ordinal rank 409f, and a message is transferred in the first channel free of the route having the lowest ordinal rank after detection of the message by the routing circuit. It appears that messages transmitted by the same connection equipment at times t and t + T and relating to the same communication transit in different ways of a given route and are received by a recipient connection equipment at times including the difference is T + AT, where # T denotes a variable phase shift depending on the ranks of the paths taken by the messages through the different sorting and transfer registers to reach the destination equipment. The "accordion" time slip is in fact a function of the intensity of the traffic in the roads borrowed at the times when the messages are transmitted in these roads respectively. The study of this random slip phenomenon makes it possible to demonstrate mathematically that a chronological inversion of two consecutive messages can not occur, in the worst hypotheses of successive slips of maximum amplitude, equal to 64 channels for the described embodiment. here, and with the same sign, that beyond the crossing of 32 registers in this case, is practically a dozen transit centers.

However, the probability of meeting in a frame window of one millisecond these maximum conditions and of the same sign accumulating in the crossing of these 32 registers is practically nil; it follows that
a) two messages transmitted successively to t and t + T never have their order at the inverted reception, that is to say at the reception in a destination equipment, the first message transmitted to t is not received after the second message sent to t +
T.

We also show that
b) at reception, at most two messages successively transmitted at t and t + T are received during a frame period
T; this results in the following two corollaries
bl) if two messages from the same equipment are detected during a period T in a recipient equipment, one or no message from the same equipment can only be received during the next frame period
b2) at the reception, two periods T during each of which two successive messages transmitted by the same equipment are received, are necessarily spaced by a period T during which no message of this equipment is received.

The write-read control circuit 91 thus serves to regulate the flow of messages in the bus BR intended to
to the EQb equipment in order to write them in the buffer 90 at the variable rate of their reception and to read in this memory the data bytes at the constant sampling period of 125 ps corresponding to the basic rate of 64 kbit / s a subscriber installation.

As shown in FIG. 12, the buffer memory 90 is composed of three identical shift registers 90of 901 and 9C2, each consisting of eight parallel-input byte shift registers connected to the BMDR sub-bus and to serial outputs connected to the circuits.
And 941 and 942 (FIG. 11). Each of the registers is capable of storing an MDR data word having 64 bits, i.e. having 8 bytes in parallel included in a received message MER, and retransmitting the stored bytes at the rate of 125 ps under the control of the write clock signal H2 applied to a 90L input. A write command is applied to an input 90E of the memory 90, as well as to an input 91E of the circuit 91, through the output of the gate 813 (Fig. 10) which is in the "1" state, as already said, when the equipment is no longer in the call phase but is occupied by the current arrival or departure communication, and when the comparator 80 detects the address of the equipment EQ6 in the sub-bus BADR (Fig. 10). The write and read commands are also applied to write and read address decoders 90AE and 90AL to address the registers 900 to 902 respectively and independently of each other. Two 91AE and 91AL address buses son out of the circuit 91 deliver to the decoders 90AE and 90AL two-bit addresses "00", "01" and "10" to address respectively the registers 900, 901 and 902.

 The read / write control circuit 91 comprises a read address counter 910, two address transcoders 911 and 912, a write address logic 913, and a command coincidence correction circuit. writing and reading 914.

 The read address counter 910 is a modulo counter 3 having two stages clocked by the clock signal H3 at the frame period T and successively outputting the register reading addresses "00", "01" and "10" to the addressing circuit 90AL and to the inputs of the transcoders 911 and 912 through the bus 91AL. The first transcoder 911 encodes the incoming address "00", "01", "10" applied by the bus 91AL to a next address immediately "01", "10", "00" which is applied to two first AND "tri-state" gates 913 (j1) In the circuit 913, the gates 91301 are opened by a two-input NAND gate 91311 for transmitting the outgoing write address of the transcoder 911, shifted with respect to the read address, in the bus 91AE and writing a data word MDR in the register 9 1 '9 2' 90O having an address succeeding that of the register 900 to 903 containing a data word normally received during the previous frame. The second transcoder 912 encodes the incoming address "00", "01", "10" applied by the 91AL bus to a next write address shifted by two ranks, ie "10", "00", "01", which is applied to two and 91302 tri-state gates in the circuit 913. The 91302 gates are opened by a two-input AND gate 91312 to transmit the outgoing address of the transcoder 912, shifted two ranks from the read address. in the bus 91AE and write a data word MDR in the register 902> 90O 9 1 having an address shifted by two ranks with respect to that of the register 900 to 903 containing a data word received previously possibly during the same period of time. frame.

The addressing logic circuit 913 also comprises a modun 3, 9132, two AND gates with two inputs 9133 and 9134, two OR gates with two inputs 9135 and 9136, a pulse multiplier by 2, 9137, a delay line. 9138 imposing a delay 1 typically 30 ps, and a monostable flip-flop 9139 triggering on a falling edge and having a time constant e2, typically 5 ps. The counter 9132 cyclically delivers addresses yx such that "00", "01" and "10" by two outputs respectively connected to the inputs of the OR gate 9135 and the gate
NAND 91311 and connected directly and through an inverter 913I to the inputs of the AND gate 91312, in response to clock pulses applied by an output of the AND gate 9133. The gate
ET 9134 has an input receiving the clock signal H3 through a monostable flip-flop 9140 on a rising edge and having a time constant 82> and another input connected to the output of the OR gate 9135. The AND gate 9133 has a input connected to an inverter 9i41 included in the circuit 914, and another input connected to the output of the OR gate 9136 through the delay line 9138.The OR gate 9136 has an input-connected to the output of the AND gate 9134 through multiplier 9137, and another input connected to the write command output of gate 813 (Fig. 10) through monostable flip-flop 9139.

 To describe the operation of the addressing circuit 913, it is assumed that the frame pulses H3 and the message write commands delivered by the gate 813 do not coincide; a coincidence with a probability of, t0 / T = 1/4096 involving the circuit 914, and the components 9138 and 9139 will be described in the following. As a result, it is assumed that for an anticoincidence between a pulse H3 and an order of writing, the inverter 9141 in the circuit 914 has an output at the state "1" which makes it possible to open the AND gate 9133 to apply to the clock input of the counter 9132 write pulses delivered by the flip-flop 9139 via the OR gate 9136, and clock pulses H3, delivered by the gate 9134, via the multiplier 9.137, the output of the gate 9134 being at "1" when the count yx of the counter 9132 is different from "00" .

On power-up, outputs x and y of counter 9132 are at "O" which blocks AND 91322, and unlocks the door
NAND 01311, the latter opening the two gates 91301 to transmit a write address of one of the registers 900 to 902> of the transcoder 911 to the write addressing circuit 90tE. The first MDR data word received at this time is written in the register 90, 902 or 900, whose address succeeds that of the register currently being read 900, or 9 1 or 902, under the control of the signal With reference to FIG. 5, the pulses H2 have a period T / 8 = 125 ps and a width of 60 ps, less than 125/2 ps, and provide during each frame period T. determined by the signal H3 the reading of 8 bytes at the original bit rate of 64 kbit / s, and that the first pulse H2 at the beginning of a frame period T is out of phase with -n, that is to say 125 / 2 = 62.5 ps, relative to the H3 pulse at the beginning of the period T.

If no other MDR word is received until the first next pulse I13, this pulse H increments the read counter 910 by one unit, and therefore the circuit 90AL reads the register where the first received word MDR has been received. written. The write order of the first word received MDR increments the counter 9132, via the gates 9136 and 9133, and consequently the outputs y and x of the counter 9132 are at "O" and "1" which unlocks the gate OR 9135 to increment the counter by two units with the multiplier 9137, via the gates 9136 and 9133, in response to the first pulse H3. Following this first pulse H3, the count yx is at "00" which opens the gates 91311 again. and 91301 for the transcoder 911 to provide a second register address immediately following that of the register in which the first MDR word is being read.

A second MDR word received normally during the frame period succeeding the first pulse H3 is then written in the second register. This normal write-read procedure is summarized with reference to two words MDR1 and MDR2 received during the first two frame periods shown in FIG. 13.

 On the other hand, if the second MDR data word is received before the first pulse H3 is produced and the first word MDR is read, the count yx of the counter 9132 changes from "00" to "01" in response to the order of writing the first message, which opens the doors 91312 and 91302 so that the transcoder 912 delivers a read address shifted by two units with respect to that of the register where the first message is written, read address addressing the register where is written the second message. After the writing of the second message, the writing order of this second message increments by one unit the counter 9132 whose count yx passes from "01" to "10" which closes the transcoder 91311 selection doors. and 91312.

This means that in the case where the count yx is equal to "10", no write address is marked in the circuit 90AE, which corresponds, as already stated, to the fact that no more than two messages in the same frame and that in this case, the next frame will have at most one message. When the first pulse E3 is applied to the open gate 9134, the counter 9132 is incremented by two units and its count goes from "10" to "01". The counter 910 delivers the read address of the register containing the first received data word, as for the normal case, and since yx = "01", the transcoder 912 can deliver the address of the third register where neither the first word being played, nor the second word waiting for reading. If no third data word is received during the second frame, the count xy changes to "00" in response to a second pulse H3, and the normal read-write cycle continues, starting with the reading of the second received message .

The write-read procedures of two data words received during the same frame period and two received data words separated by a frame period not including data words are illustrated in Fig. 13, with reference to FIG. two words
MDR3 and MDR4 and two-word MDR5 and MDR6.

 It should be noted that if the count yx of the counter 9132 is equal to "00" when a pulse H3 is applied to the gate 9134, the latter is blocked by the closing of the OR gate 9135, and the count of the counter 9132 remains unchanged until a next MDR data word is written.

 In summary, the three accounts "00", "01", "10" of the counter 9132 respectively indicate that no data word is in the process of reading, that a data word is in the process of reading, and that two words of data are in the process of reading. Thus, the addressing logic circuit 913 regulates the time intervals separating data words, and more generally received successive messages, and the counter 9132 indicates by its count yx the balance of received messages written and read.

The write commands issued by the gate 813 and the circular permutation commands of the read addresses H3 are completely independent. Their colncidence leads to distort the incrementation of the counter 9132 and thus to skip the reading of an MDR data word or to record and read the same word twice.
MDR as a result of which, the counter status may return to normal.

The probability of this coincidence is, in practice, 1/20000, the impulses in question having a duration of the order of 50 ns with an average interval of one millisecond. This probability is very high here because the coincidence can appear at an average interval of 20 seconds, and result in a "noise" in speech and a loss or repetition of a set of 8 octets in telematics. This therefore made it necessary to implement the coincidence correction circuit 914.

 As shown in FIG. 12, the circuit 914 also comprises two AND gates with two inputs 9142 and 9143, a monostable flip-flop 9144 that can be triggered on a rising edge to produce calibrated pulses having a duration of typically 28 μs equal to 60 μs, a circuit 9145 to three monostable flip-flops in cascade to produce a sequence of three pulses, and a diode 9146. The inputs of the AND gate 9142 are respectively connected to the outputs of the monostable flip-flops 9140 and 9139. The flip-flop 9144 has an input connected to the output of the gate 9142, and an output connected to the inputs of the circuit 9145 and the inverter 9141 of the circuit 914, and to an input of the gate 9143.The gate 9143 has another input connected to the output of the flip-flop 9145, and a connected output at the clock input of the counter 9132 and at the output of the gate 9133, via the diode 9146.

It will be noted that the circuit 914, just like the logic addressing circuit 913, has for its action a time much greater than the time interval t0 = 244 ns during which a message is present in the reception bus ER> since the average interval
a separating two write commands is of the order of one millisecond, and the reading addressing action by the circuit 90AL has the time between two successive pulses H3 and H2, ie 62.5 ps.

 A coincidence between a pulse H3 and a write pulse is detected by the AND gate 9142 as long as this coincidence corresponds to an overlap of these two pulses for a time greater than the operating time of the gate 9142. At the door ET 9142, this coincidence detection precedes that which is performed by the OR gate 9136 in the addressing logic circuit and is delayed by the delay line 9138. The detection of a collision by the AND gate 9142 triggers the monostable flip-flop. 9144 which delivers a calibrated pulse of duration 201. The calibrated pulse blocks the AND gate 9133, via the inverter 914], for a time which exceeds 81 the moment when a pulse E3, multiplied in two pulses, and a pulse mixed and transmitted by the OR gate 9136 and the delay line 9138 are applied to the AND gate 9133.

 By tailors, the calibrated pulse delivered by the flip-flop 9144 triggers the circuit with three monostable flip-flops 9145 which delivers a train of three pulses, having a duration less than 8 i> which corresponds to the three pulses which would have incremented the counter 9132 if no There was no coincidence. The train of three pulses passes through the unlocked gate 9143 during the duration 281 and therefore increments the counter 9132. The write command pulse at the output of the gate 813 triggers by its falling edge the flip-flop 9139 which delivers a calibrated pulse of width 82 = 5 Similarly, the clock pulse H3 triggers by its rising edge the flip-flop 9140 which delivers a calibrated pulse of width 82 = 5 μs. These calibrated pulses are reserved for the single addressing circuit 913. Under these conditions the maximum value of 81 of the duration of the three pulses delivered by the flip-flop circuit 9145 is 30 us This value 81 = 30 us is compatible with the available delay 62.5 us between two pulses 113 and H2, reported above, and is such that 281 = 60 us <62.5 us.

 It is indeed necessary to make the choice of the greatest possible value so that on high-rate links the reduction, made as we have seen, by the play of the clocks H1 to HI (FIG. are then divided by 2q, do not lead to values too low compared to the operating times of the flip-flops. In particular, it is verified that at the highest rate of 64 kbit / s × 210, these pulses go from 5 μs to 5.2 μps = 4.8 ns compatible with flip-flops operating at 3 ns.

 The bit rates of 64 x 211 kbit / s and 64 x 2 kbit / s are not covered by an address logic circuit with three addresses but with two addresses and one address respectively, and the result of which is obtained for these two cases by the de facto neutralization of the addressing logic circuit and the transcoder 912. Indeed, in these two cases according to the demonstration made, it is no longer possible to receive two MDR words at a time in a reading interval since two consecutive messages are spaced only one interval for the first case and none for the second case.

Or the receipt of two MER messages in the same interval must be followed at some point or another of an interval with no message which in both cases can not occur.

This is otherwise explained by the fact that the amplitude of the slip is then limited to a time interval t0 for the first case and zero interval for the second case. So there is de facto synchronization. As already stated, all the circuits and registers receiving clock signals adapt to the bit rates higher than 2 × 64 kbit / s by the corresponding clock signals provided by the time base 3.

As announced in the description, a programmable comparator CP which can preferably be used in the circuits of a subscriber connection equipment and in routing circuits of the routing system is now described with reference to FIG.
Srou. The comparator CP is intended to compare an incoming word having
E bits transmitted in parallel by a first E-bit CPA input bus, with a reference word having at most E bits transmitted in parallel by a second input bus CPB to E son. More precisely, a comparison of two words is carried out by simultaneous comparisons between bits of predetermined ranks in the incoming word and the reference word. Rows 1 to E of the bits to be compared and bits that are not compared or "neutralized" are respectively reported by states "O" and "1" on corresponding wires of a third CPN input bus having E wires.

The comparator CP comprises E identical cells CEL1 to CELE which each compare two bits of the same rank in the incoming and reference words and an output AND gate EPC having E inputs respectively connected to outputs OR or three inputs
CPCU1 to CPUEE included in cells CEL1 to CELE.

A cell, such as the CEL cell, where the integer e is
e between 1 and E, includes an AND gate, CPET, and a gate
NAND, CPNO, each having two inputs connected to the respective wires of the CFA and CPB buses transmitting the bit of rank e in the incoming word to be compared and the bit of rank e in the reference word. Outputs from the CPET and CPNO gates are connected to
ee first two entries of the door CPOU. A third entry of
e the gate CPOU is connected to the respective wire of the bus CPN signaling by
e the state "O" that the bits of the row e are to be compared, and by the state "1" that the bits of the row e are not to be compared. According to another variant, the doors CPET and CPN0 are replaced by a door
ee
NOR XOR.

If the respective wire in the CPN bus is in the "O" state, the gate
CPOU is only open when two bits of rank e are
e identical. CPET and CPNO doors detect respectively
ee the identity of the two bits in state "1" and in the state "O", identity which is translated by "1" to one of the first two inputs of the door
CPOU and therefore at the exit of it. If not, where
e the two bits are different, the output of the gate CPOU is at
e the state "O".

If the respective wire of the CPN bus is in state "1", the output of the gate CPOU is in the state "1" whatever the states of the bits
e of rank e.

The output CPS of the gate CPE thus indicates in state "1" that all the bits compared in the incoming word and the reference word are respectively identical, and by the state "O" that at least one of the Incoming word bits compared are different from those in the reference word having the same rank, since the non-comparing bits impose a state "1" at the output of the respective gate CPOU1 to CLOUE
In particular, when the incoming word is a binary word at E = 64 bits obtained by decimal binary coding of CH = 16 digits or characters of an incoming number, in CH bit words at 4 bits, as for example for the number of call stored in the form of the recipient address word ADT in the 614CO recorder (Fig. 7), the bus CPN then comprises only CH son connected respectively to CH sets of E / CH = 4 cells. Each set of cells is able to compare two character words having the same rank in the incoming number and a reference number.

The distribution of the states "1" and "O" in the wires of the bus CPN can be chosen in any manner, for example to compare only bits or words of character of lower or higher rank, corresponding for example to a prefix or suffix of the incoming word, indicating a message routing route, or a set of bits or character words having any ranks in the incoming word. Thus, not only the reference word is programmable, but also the states of the bus wires
CPN indicating the ranks of the bits or sets of bits to be compared.

 Note that the programmable comparator CP is achievable in integrated circuit and offers a very high speed of operation, regardless of the number of bits to compare, the result of the comparison being obtained in at most 15 ns approximately.

The comparator CP described above is thus usable according to the invention as address comparators 331 to 33I included in the time base 3 (FIG. 4), prefix comparators 201 to 20p included in the comparison circuit of FIG. prefix and format determination 2 (Fig. 8), byte comparator 740 included in the silence detection circuit 74 (Fig. 9), service word comparator 752 included in the stabilization circuit and service word transmission 75 (Fig. 9), and call service word comparator 823 and destination equipment address comparator 80 included in the call handling circuit (Fig. 10). CPA input buses,
CPB and CPN and the CPS output of the comparator CP correspond to the buses and outputs of the abovementioned comparators by replacing "CP" by the reference numbers of the abovementioned comparators respectively.

Claims (27)

 1 - Connecting equipment (EQb) in a digital telephone exchange connecting a subscriber telephone line (las) to first and second transmission medium (BTB, BR) conveying first and second division multiplexed messages (MET, MER) time, the equipment receiving line (LAb) including data signals to convert them into first messages (MET) periodically transmitted at a rate of a first message per time interval (ITb, 113) allocated to the equipment in a frame (T) of the first support (BT), and the equipment detecting second messages (MER) which are intended for it in the second support (BRa) for particular conversion into signals transmitted in the line (LAb) , the first and second messages (MET, MER) being capable of being received and transmitted by other asynchronous connection equipment of said equipment (EQb)> characterized in that it comprises  means (6) for detecting and registering a destination equipment address (ADT) delivered by the line (las) for transmission with first messages (MET) during a whole initial communication,  means (71, 72) for transmitting an address of said equipment (AEQb = MDT) with first messages (MET) during a call sequence of a start communication,  means (80) for detecting the address of said equipment (ADR = AEQb) in second messages (MER) conveyed by the second medium (BR), and  means (83,84,85) for registering a destination equipment address (MDR) in second messages (MER) containing the address of said equipment (ADR = AEQb) and for transmitting the registered destination equipment address ( MDR = ADT) with first messages (MET) during a whole incoming communication.  2 - Equipment according to claim 1, characterized in that the means for detecting and recording a destination equipment address (6) comprises means (60) for coding in the form of a binary address word (ADT) of multifrequency signals representative of the destination equipment address and delivered by the line (las), means (614ci) for storing the binary address word, and means (617) for reading and transmitting the word of stored bit address (ADT) in the first medium (BTa) in response to the time slots (ITb) allocated to the equipment (EQb) in the frame (T).  3 - Equipment according to claim 2, characterized in that the means for detecting and recording a destination equipment address (6) comprise means (62, 2) for validating a stored bit address word (MDT) in order to allow reading and transmission of said binary address word when it is validated.  4 - Equipment according to claim 3, characterized in that the means for enabling comprises means (621, 623, 622) for taking bits of predetermined ranks in the stored bit address word (ADT), and means ( 201 to 20p) for comparing the bits taken from predetermined words (prefixes) to allow reading and transmission of said bit address word when it is identical to one of the predetermined words.  5 - Equipment according to claim 3 or 4, characterized in that the means for validating comprise means (621, 623, 622) for taking a part (prefix) of the stored bit address word (ADT) implicitly indicating the number of bits to be contained in the bit address word, memories (222 to 2216) storing predetermined numbers of bits (f 2 to f16) to be contained by the bit equipment address words respectively, and means (201 20p) to read one of said predetermined numbers according to the portion of the address word taken to allow reading and transmission of said bit address word when it has a number of bits equal to the predetermined number read ( 2 to 16).  6 - Equipment according to any one of claims 1 to 5, characterized in that the recipient equipment address (ADT) transmitted with each first message (MET) of a coninunication departure corresponds to the telephone number of the subscriber line (las), preferably after decimal bit coding of this call number.  7 - Equipment according to any one of claims 1 to 6, characterized in that the destination equipment address (ADT) is delivered in the subscriber line (LAb) in the form of multifrequency signals modulating pulses having a first predetermined width (ATco) and in that the means for detecting and recording (6) comprise means (611cl) for enabling said address when pulses provided by the line have said predetermined width.  8 - Equipment according to claim 7, characterized in that it comprises means (61SE) for detecting and recording ancillary service words (SE) delivered by the subscriber line (las) in the form of multifrequency signals modulating pulses having a second predetermined width (AtsE) different from the first width (AtCo).  9 - Equipment according to any one of claims 1 to 8, characterized in that the means for transmitting the address of said equipment comprises a memory (71, 72) containing the address of said equipment (AEQb) and means (73 ) to read said memory (71, 72) in response to each time slot (ITb, H3) allocated to the equipment (EQB) in the frames (T) and during a start communication call sequence (4lapda) starting with a stall signal delivered by line (L).  10 - Equipment according to claim 9, characterized in that it comprises means (70) for storing data words (MDT) delivered by the line (las), if necessary through a decoder and / or analog converter and in that the means for reading (73) read stored data words in response to each time interval (ITb, E3) after a start or end communication call sequence.  11 - Equipment according to any one of claims 1 to 10, characterized in that the first support (BTa) comprises a sub-support (BMDT) in which are transmitted the destination equipment address (ADT) and words of data delivered by the line (las) during a call sequence of a start call and after a start or end call call sequence, respectively.  12 - Equipment according to claim 10 or 11, characterized in that it comprises means (74) for inhibiting transmissions of first data message (MET) after establishment of a call, when data delivered by the line ( las) belong to one or more predetermined data ranges (silence ranges).  13 - Equipment according to claim 12, characterized in that the predetermined data ranges are ranges of silence corresponding to predetermined quantization levels of a quantization law according to which are digitally coded data.  14 - Equipment according to any one of claims 1 to 13, characterized in that it comprises means (40, 75) for establishing service words (BSVT) identifying communication sequences and introduce them into the first messages (MET) transmitted by said equipment (EQb), and means (92, 44) for processing service words (BSVR) in the second received messages (MER) containing the address of said equipment (EQb).  Equipment according to claim 14, characterized in that the means for establishing and entering service words comprise service word memories (40), means (43) for reading the service word memories in response to communication sequence signals provided by means (6, 8, 9) internal to the equipment (EQb) and received service words (BSVR) respectively, and means (75) for transmitting each service word (SVT) in a frame time (ITb) allocated to the equipment, regardless of when the service word is read.  16 - Equipment according to any one of claims 1 to 15, characterized in that the means for recording and transmitting (83, 84, 85) comprise means (831) for recording the destination equipment address in response to a second call message transmitted by the destination equipment when said equipment (EQb) is free of any communication, a memory (832) containing a free equipment service word, and means (833, 834) for reading and introducing in first messages (MET) said registered destination equipment address and said stored free equipment service word, in response to time slots (ITb, 113) allocated to said equipment (EQb) during the frames (T) and respectively during a whole incoming communication (4lapar) and during the call sequence of an incoming communication (41ar) when said equipment (EQb) is free of any communication before said call sequence.  17 - Equipment according to any one of claims 1 to 16, characterized in that the means for recording and transmitting (83, 84, 85) comprise means (840) for recording a requesting equipment address in response to a request. second call message transmitted by the requesting equipment when said equipment (EQb) is occupied by a communication in progress, a memory (841) containing a busy equipment service word, and means (852, 854) for reading and inputting in said first messages (MET) said registered requesting equipment address and said stored occupied equipment service word, in response to time slots (ITb, H3) allocated to said equipment (EQb) during the frames (T ) and during silence intervals of predetermined amplitude of said communication in progress.  18 - Equipment according to any one of claims 1 to 17, characterized in that the means for recording and transmitting (83, 84, 85) comprise means (840) for recording a requesting equipment address in response to a request. second call message transmitted by the requesting equipment when said equipment (EQb) is occupied by a communication in progress, a memory (855) containing a transfer equipment address when said equipment (EQb) is grouped with the equipment or when said equipment (EQb) serves an absent subscriber for which incoming calls are to be transferred to the transfer equipment, a memory (856) containing an equipment transfer service word, and means ( 853, 854) for reading and entering in first messages (MET) said registered requesting equipment address, said transfer equipment address and said transfer service word in response to int. time intervals (ITb, H3) allocated to said equipment (EQb) during the frames (T? and during silence intervals of predetermined amplitude of a communication in progress when said equipment is grouped, or at any time when said subscriber is absent.  19 - Equipment according to any one of claims 1 to 18, characterized in that it comprises  means (90, 91) for storing data words (MDRs) in second messages (MERs) for the equipment after a call sequence of a communication,  means (92) for storing communication sequence service words (SVRs) in the second messages (MERs) for the equipment,  means (82) for detecting incoming communication call sequence service words in the second messages, and  means (81) connected to the means for detecting the address of said equipment (80) and means for detecting call sequence service words (82) for controlling the writing of a recipient address word ( MDR) in said means for recording and transmitting (83, 84, 85) in response to a call sequence service word and the address of said equipment (SEQb) in a second message, and for controlling the writing a data word and a service word, when it is different from a call sequence service word, in a second message (AEQb) in said means for storing (90, 91, 92) in response to the address of said equipment in the second message.  20 - Equipment according to any one of claims 1 to 19, characterized in that the second messages (MER) for said equipment (EQb) have a variable flow in the second transmission medium (BRa) and in that two seconds successive messages for said equipment in the second transmission medium (3Ra) are received by the equipment (EQb) during two successive frame periods (T), or during the same frame period, or during two spaced frame periods of a frame period, said frame periods determining the periodicity of the periodic time slots (ITb) during which the first messages are transmitted by said equipment in the first medium (BTb).  21 - Equipment according to claims 19 and 20, characterized in that the means for storing data words (90, 91) comprise a buffer memory (90) for storing the received data words, means (9OAE, 911, 912 , 913, 914) for writing the received data words to the buffer in response to data and service word write commands (813) provided as a function of said variable flow of the second messages for said equipment (EQb) by the means for controlling the writing (81), and means (90AL, 910) for reading portions (bytes) of the written data words, at a period (H2) of sampling signals transmitted in the telephone line (L) -  22 - Equipment according to claims 19 and 20, characterized in that the means for storing data words (.90, 91) comprise three buffer registers in parallel (900, 90 ,, 902) for each storing a data word, means (910) for generating three register read addresses cyclically every three frame periods (T); means (90AL) for reading portions (bytes) of a written data word in a read-addressed register at a sampling period (H2) of signals transmitted by the telephone line (Li), means (911, 912) connected to the means for producing the read addresses (910) to produce first and second register write addresses corresponding to the two other buffer registers which are not being read during each frame period, means (90AE) for writing a data word (MDR) in one of the two registers which is not being read in response to a writ order re of data and service words (813), and means (913, 914) interconnected to the means for generating write addresses (911, 912) and writing means (90AE), for selecting the address of writing one of said two registers which is not being read and which does not contain data words in response to a write order of data and service words.  23 - Equipment according to claim 22, characterized in that the means for selecting (913, 914) comprise means (914, 9133, 9138) for delaying the selection of the write address of one of said registers when a write command (813) substantially coincides with a read start time (R3) of another register.  24 - Equipment according to any one of claims 19 and 21 to 23, characterized in that it comprises means (94, 93) for transmitting in the telephone line (las) data words (EDR) read in the means for storing data words (90, 91) after a communication call sequence, the means for transmitting transmitting the data words either through a parallel-serial converter and / or an encoder (944), or through means (945, 946) modulating pulse duration as a function of parts (bytes) of the read data words (MDR).  25 - Equipment according to any one of claims 1 to 24, characterized in that it comprises means (93) for injecting into the telephone line (las)) signaling signals (93E) according to the state open or closed line (431) and signaling signals (41, 93C) transmitted by line and in the form of service words (SVR) included in second messages (MER) for said equipment and indicating sequences of 'a communication.  26 - Equipment according to any one of claims 1 to 25, characterized in that it is included in a set (ETa) of several synchronous connection equipment (EQ1 to EQB) connected to said first and second transmission media (BT , BR), said set (ET) comprising means (1) for addressing  a a to the frame period (T) said equipment in order to allocate each one of them one or more respective time slots (IT1 to ITB) according to the rate of the signals transmitted in the telephone line (LA1 to L) connected to the equipment (EQ1 to EQB), and each of said equipment comprising a time base (3) punctuated according to an address of the equipment (1 to B) delivered during the respective time intervals by the means for addressing the equipment (1) to produce equipment specific clock signals (H1 to HI) in response to the address of the device. equipment (1 to B) in each respective time interval (IT1 to ITB).  27 - Equipment according to any one of claims 1 to 27, characterized in that the equipment rate is equal to 2ex64 kbit / s, where q is an integer between 0 and 12 inclusive.