FR2599572A1 - Method and device for multiplexing binary signals - Google Patents

Abstract

The present invention relates to a multiplexer of binary signals present on m data lines and appearing at a maximum rate corresponding to a frequency f0, comprising a counter 10 counting cyclically from 0 to n at a frequency greater than nf0 for each line: a sampling-detection circuit 13 for detecting the transitions of this line in synchronisation with the sampling pulses at a frequency greater than nf0 and a flip-flop 11 for memorising on each transition of this line a memory word (WWWP) indicating the state of the line and the value of the counter immediately after the transition, a shift register 20 with parallel inputs and serial output receiving the inputs from the m flip-flops into successive slots and sequentially providing at a frequency greater than nmf0 the string of words from each flip-flop.

Description

MULTIPLEXING METHOD AND DEVICE
BINARY SIGNALS
The present invention relates generally to a method of multiplexing binary signals present on separate lines and to be sent in serial form on a single line.

 It applies more particularly to the connection of a set of terminals such as: terminal with screen and keyboard, printer, modem, etc.) to a central computer comprising itself, for example, a central unit, random access memories and memory (RAM and ROM), input / output devices and various peripherals such as mass storage devices.

 Conventionally, to connect several terminals to a central computer, these terminals are associated in groups with a distribution panel itself connected to an input / output access of the central computer. Conventionally, each terminal includes ten input / output terminals. Thus, if you want to connect several terminals to a distribution panel, you will need to provide a connector with several tens of pins between each panel and the central computer. For a connection cable with several tens of wires, the standards entail a limitation of the maximum distance to a value of the order of a meter. Thus, with a normal distribution panel, the distance between the panel and the central computer is limited to 1 set. This means that it is difficult or hazardous to have a set of terminals too far from the location of the central computer and in particular that the distribution panels are practically in the immediate vicinity of the central computer.

 In fact, in practical applications, one would like, for example inside a building, to have groups of terminals themselves distant from the central computer.

 It is an object of the present invention to provide a multiplexing method allowing, given a distribution card connected by sets of several wires to various terminals, to connect this distribution card to the central computer via a single link, for example a pair of optical fibers, a two-wire double link, a two-wire link and a ground ...

 To achieve this object, the present invention provides a new multiplexing method for sending more information on a two-wire line.

 Generally, at the outset, a multiplexing uses a sampling of each of the pieces of information which it must combine with others. It is the number of samples per information that defines the quality of the treatment. For a given sampling, in the prior art, a number of pieces of information is transmitted in the multiplexed link equal to the number of samples, possibly using various data compression methods avoiding, for example, sending identical signal sequences.

 Thus, a general object of the present invention is to provide a sampling method with a view to multiplexing making it possible, for a given sampling, to send a number of pieces of information less than the number of samples while retaining the precision related to sampling.

 To achieve this object as well as others, the present invention provides a new method for multiplexing signals present on a set of m data lines, on which appear binary signals varying between a high state (1) and a low state ( O) at a maximum rate corresponding to a frequency fO, comprising the following steps: sampling each line at a frequency f (f greater than nfO, n being an integer) and detecting in synchronization with this sampling the changes in the signals of each line; provide a counter cyclically counting from O to nl at frequency f, memorize after each transition of a line the content of the counter and the state (1 or O) thereof according to a memory word, transmit sequentially memory words on a transmission line at a rate greater than nmf.

 This process allows compression of the data to be transmitted by replacing n samples with [log2 (n) +1] samples.

 Another object of the present invention is to provide a device implementing this method.

To achieve this other object, the present invention provides a device for multiplexing binary signals present on m data lines and appearing at a maximum rate corresponding to a frequency f0, comprising
a counter counting cyclically from O to nl (n being an integer) at a frequency greater than nfO,
for each line: a sampling-detection circuit to detect the transitions of this line in synchronization with the sampling pulses at a frequency greater than nfO, and a flip-flop with (n + 1) bits to memorize at each transition of this line a memory word indicative of the state of the line and the value of the counter immediately after the transition,
a shift register with parallel inputs and serial output receiving the inputs of the m flip-flops in successive boxes and supplying sequentially, at a frequency greater than nmf0, the sequence of words of each flip-flop.

These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of a particular embodiment made in relation to the attached figures, among which
FIG. 1 shows in general the coupling of terminals to a central computer
FIG. 2 represents timing diagrams intended to illustrate the operation of the present invention
FIG. 3 represents an embodiment of an encoder according to the present invention
FIG. 4 represents a particular embodiment of an edge detector according to the present invention;
FIG. 5 represents the general diagram of a multiplexer according to the present invention; and
FIG. 6 symbolically represents the outputs of a multiplexer according to the present invention.

 your Figure 1 illustrates in general the problem that the present invention aims to solve and which has been presented above. Given a central computer 1, when we try to connect terminals 2-1, ..., 2-m such as screen and keyboard terminals, printers, modems, etc., we generally use an intermediate card 3 said distribution panel. This card comprises on the one hand connectors 4-1, 4-2, ..., 4-m in numbers equal to the maximum number of terminals that one wants to connect, on the other hand a connector 5 intended to ensure the connection with the central processing device. Conventionally, each terminal comprises a dozen connection wires, but only some of these wires, usually one or two, are capable of conveying elements of information repeating themselves periodically rapidly.

 In the absence of multiplexing, the connection between the central computer 1 and the distribution card 3 is ensured by as many wires as the connection to each of the terminals multiplied by the number of terminals. For example, for eight terminals each connected by 10 wires, there will be 80 wires connected to connector 5 without counting the ground connections. In fact, commonly, this number is slightly reduced because in the connections between each of the terminals and the distribution panel, certain wires carry common general messages which are found on the same wire between the distribution panel 3 and the central computer. 1. Thus, if there are eight terminals each connected by 10 wires, the number of wires between the central computer and the distribution panel can be of the order of 50 to 80.

 In any case, from the moment when an information-carrying connection cable exceeds a number of wires of the order of thirty, existing standards lead to a limitation of the length of this wire to a value of the order of metre. In fact, beyond this value, noise-related faults are likely to occur. With regard to 10-wire cables between the distribution panel and the terminals, the length limit imposed by the standards is of the order of 10 to 20 meters.

 As already stated above, the present invention aims to achieve a two-wire or at most three-wire connection between the central computer 1 and the distribution panel 3 by providing in the distribution panel 3 a multiplexing card which is will call CREM card according to the acronym of the Anglo-Saxon expression Cluster Remote Extension Multiplexer (Multiplexer for Network of Remote Terminals).

 The basic principle of the multiplexing method according to the present invention will first be explained in relation to FIG. 2, and will be repeated below in relation to the embodiments of the device according to the invention illustrated in FIGS. 3 to 5 .

Given a binary coded data signal D, that is to say which may be at a high level (1) or at a low level (0), and assuming that the shortest period between two transitions is that shown on line D of FIG. 2 (corresponding to a frequency f0), the present invention provides in a conventional manner for sampling this data signal D by a clock signal C1. In the example of the figure, has chosen a sampling frequency greater than eight times the frequency fO. Following this sampling, a signal P or edge signal synchronized on the clock pulses is supplied from the data signal D and it is possible to possibly supply by various means from this signal P a signal
S corresponding to a pulse for each of the clock pulses following a transition.

 According to the present invention, provision is made to act in parallel with this sampling system a counter operating acyclically, at the rate of the clock pulses C1.

For each transition of the signal P, a binary signal WWW is supplied corresponding to the counting of the counter at the time of the transition. In the example of FIG. 2, it can be seen that for the two transitions of the signal P the counter has reached the value 5.

Then, as information representing the transition, this binary coded value 5 (WWW = 101) will be transmitted accompanied by a position bit P equal to O or 1 depending on whether, at the time of the clock signal, the signal P is high or low. Whereas in a conventional way, we would have sent an information element (1 bit) at each sampling instant, i.e. eight bits between the two transitions represented, according to the invention, we will only send a signal to four bits (three bits corresponding to the value indicated in binary of the count at the time of the transition and a position bit).

 If we had chosen a much tighter sampling, for example by taking 16 samples during the shortest possible period between two transitions, instead of sending in a conventional manner 16 bits of information, we would send according to the present invention only 5 bits : 4 bits to indicate the value of the counter between 0 and 15 and a position bit.

 This process and its advantages will appear more clearly on reading the following description of a particular embodiment of an apparatus for implementing it.

 FIG. 3 represents an encoder 13 for a data line D. This encoder is associated with a counter 10 actuated by a clock Cîl and providing on three outputs (in the case of a count between 0 and 7) the corresponding binary value to its current count. The outputs of the counter 10 are connected to the first three inputs of a memory flip-flop (latch) 11. The flip-flop 11 receives on its fourth input the output signal P from an edge detector 12 corresponding to the signal illustrated in FIG. 2. The detector 12 receives as input the data signal D to be analyzed and a clock signal C12. The detector 12 also provides an output S corresponding to the signal shown in FIG. 2 which activates the clock input of the flip-flop 11. Thus, at each transition, the flip-flop 11 will store a count W2, Wl, WO and a position bit P characteristics of the position of the counter at the time of the transition and of the polarity of the signal immediately after the transition, this information being synchronized with a clock signal.

FIG. 4 shows by way of example a schematic embodiment of the edge detector 12. This detector 12 receives as input a data signal D applied to the input D1 of a flip-flop FF1 whose output Q1 is connected to the input D2 of a flip-flop FF2. The clock inputs of flip-flops FF1 and FF2 receive the clock signal C12. The output Q1 of the flip-flop FF1 is connected to a first input of an Exclusive OR gate 14 whose second input is connected to the output Q2 of the flip-flop
FF2.We thus obtain well at the output Q1 of the flip-flop D the signal P which senses the same transitions as the signal D, but these transitions are located at the instants of sampling which follow the transitions of the signal D. The flip-flop FF2 will switch with a delay time with respect to the flip-flop FF1, that is to say in synchronism with the following clock pulse C12 to supply the signal B illustrated in FIG. 2 and we therefore obtain well at the output of the Exclusive OR gate 14 the signal S represented in FIG. 2. It is clear that FIG. 4 only represents an example of a circuit making it possible to supply signals P and S, many other similar circuits being able to be produced by man. art.

 FIG. 5 schematically represents a multiplexing device according to the present invention.

 In this circuit, four data input lines D1, D2, D3, D4 are shown, respectively connected to position encoders 13-1, 13-2, 13-3, 13-4, (or more generally 13 -1 to 13-m) each constituted as the position encoder 13 in FIG. 3. A counter 10 similar to the counter in FIG. 3 is connected to each of these position encoders. The WWWP outputs of the position encoders 13-1 to 13-m are connected to the inputs of a shift register (SR) 20 from which they can be extracted in series form by an output terminal 21. Other information is also inserted in this shift register 20 as shown in the upper part of FIG. 6. In particular, at the head of the register, it is possible to insert an identification reference word announcing the start of the transfer of the content of the register called frame F. This word will include example two bits SS '. On the other hand, between successive groups of WWWP words coming from the position encoders, for example once every two words, it is possible to insert a bit relating to other information, for example, in the case of a connection to a terminal , status codes identifying the operating mode of the terminal, for example data transmission codes, transmission request, ready status indication, test signal, etc. These codes are designated in Figure 5 by MO-O and MO-1 for the first two and are generally designated by the letter M in Figure 6. These are information that occurs much less often than information from D data which can be transferred6 much less often.

 On the other hand, as the lower part of FIG. 6 shows, and as is conventional in the field of information transmission, and if the content of register 20 is called frame F, successive frames F1 to F16 may be grouped in successive superframes, the reference words between the successive frames of a superframe being able to be used to convey service information :.

 Extracting data from the registry at. shift SR 20 is controlled by a clock CL 22. It will be necessary to provide synchronization between this clock 22 (and the clock controlling the counter 10) and corresponding clocks at an associated demultiplexer.

 The advantages of the multiplexing method according to the invention have already been presented above with regard to the reduction in the congestion in frequency that it produces on a transmission channel compared to conventional methods. Another advantage of this circuit is that the coupling and synchronization between this multiplexer and a corresponding dmultiplexer can be achieved in a particularly simple manner since it suffices to provide at the level of the demultiplexing circuits a counter operating at the same rate as the counter 10.

 As an example of orders of magnitude of the operating frequencies of a device according to the present invention, it may be noted that the clock frequency Cîl applied to the counter 10 can be in a practical embodiment of 184.32 kHz , the clock frequency C12 applied to the edge detector being equal to or multiple of this value, the clock frequency applied to the shift register 20 being 921.6 kHz and the clock frequency applied to the Manchester encoder 23 being the double the previous one, namely 1,843.2 kHz, which corresponds substantially to a link at two Mbauds. All these frequencies can, as usual, be derived from a central clock generator. This example is given in the case where it is sought to sample eight lines of information such that the frequency corresponding to the shortest period of a signal on one of these lines is 23.04 kHz, which corresponds to a nominal frequency of 19,200 baud while keeping a safety margin of 20%.

Claims (4)

 1. Method for multiplexing signals present on a set of m data lines, on which binary signals appear varying between a high state (1) and a low state (O) at a maximum rate corresponding to a frequency fO, characterized in what it includes the following steps  sample each line at a frequency f (f greater than nfO, n being an integer) and detect in synchronization with this sampling the changes in state of the signals of each line  cyclically count from O to n-l, at frequency f,  memorize after each transition of a line the count value and the state (1 or 0) of this one according to a memory word (WWWp),  send the memory words sequentially on a transmission line at a higher rate nmf.  2. Multiplexing method according to claim 1, characterized in that one transmits further status bits (M) characteristics of the devices transmitting said binary signals on each of the lines, and service bits (SS ').  3. Multiplexer of binary signals present on m data lines and appearing at a maximum rate corresponding to a frequency fO, characterized in that it comprises  a counter (10) counting cyclically from O to n (n being an integer) at a higher frequency nfO,  for each line: an edge detector (12) for detecting the transitions of this line in synchronization with the sampling pulses at a frequency greater than nfO, and a flip-flop (11) for memorizing at each transition of this line a memory word (WWWP) indicative of the line status and the counter value immediately after the transition,  a shift register (20) with parallel inputs and serial output receiving the inputs of the m flip-flops in successive boxes and supplying sequentially at a frequency greater than nfO the sequence of words of each flip-flop.  4. Multiplexer according to claim 3, characterized in that said series of words are grouped in frames and preceded by a reference code (SS ') before transmission.