FR2596606A1 - Switch with modular architecture - Google Patents

Abstract

The switch of the invention has a mono-multiprocessor structure. Each cell of a bay includes several processors 5.1 to 5.n linked to a common bus 9, the control units 6 of which intercommunicate via a packet network internal to the switch. Switching couplers 10.1 to 10.m are linked to the common bus.

Description

MODULAR ARCHITECTURE SWITCH
The present invention relates to a switch with modular architecture.

 Currently manufactured switches have a narrowly defined power range and are designed accordingly.

So, for example, there are switches with either a low capacity and traffic range (less than 30 Erlang), or a medium range (200 to 1000 Erlang), or a large range (more than 2000 Erlang), but none model does not cover these three ranges or even two of them. In addition, these switches have a reduced service range: either they allow access to speech and data signals, without the possibility of allowing transit, or the opposite.

 The present invention relates to a switch making it possible to easily cover a very wide range of powers, for example 30 to 1000 Erlang, and this, by offering an extended service: access and transit, speech and data processing, this switch in front be made up of a limited number of different elements to facilitate industrialization.

 The switch according to the invention has a single-processor structure, with software at least partially distributed to several similar cells, each cell comprising a local interprocessor bus, as well as a local bus completely decoupled from the buses of the other cells, the information circuit of the subscriber being decoupled from the information circuit of the processor.

 According to other respective features of the invention, the data path of a switch has a constant transit time; all the cells are synchronous; the cards, constituting functional entities within their cell, are supervised by decentralized control units located in their cell; the control units communicate with each other via a packet network internal to the switch; inside a single cell, the packet network borrows the support of a memory queue network, according to the hyper-lattice technique; and outside a single cell, the packet network is meshed in a hypercube and follows high-flow pathways from the internal arteries.

The present invention will be better understood on reading the detailed description of an embodiment, taken as a nonlimiting example and illustrated by the appended drawing, in which:
- Figure 1 is a functional block diagram of a switch according to the invention;
- Figure 2 is a simplified block diagram of the multiprocessor system of the switch of Figure I
FIG. 3 is a block diagram of a subsystem of the switch of FIG. 1, and
- Figure 4 is a block diagram of a subsystem of the switch of Figure 1 to packet transmission service network.

 The modular architecture switch system described below consists of a set of multiservice switches allowing the establishment of communications between interoperable subscribers, for example between a subscriber communicating in digital voice and a subscriber communicating in analog voice, or between subscribers transmitting data and operating at different rates.

 The architecture of this switching system is produced from four interdependent functional subsystems which are, as shown in FIG. 1, a "packaging" subsystem 1, a computer subsystem 2, a switching subsystem packets 3, and a physical circuit subsystem 4.

 Subsystem 1 constitutes the "cement" of the modular switching system. It imposes environmental and interfacing standards on the physical and software components of the other subsystems. It also makes it possible to adapt the switch to all kinds of environmental conditions, in particular when these are very severe, without however implicating the functional questioning of the other subsystems.

 The computer subsystem 2 hosts all of the switch's software applications (that is to say located above level 5 of the OSI architecture of the ISO standard). The hardware components are only intended to facilitate this reception and minimize the cost.

 The subsystem 3 fulfills two main objectives: firstly, an internal service ensures the interrelation of the objects of the computer subsystem independently of their physical location in the network of individual switches of the system. It is transparent to users. Second, an external service, dissociated from the product, and sized on demand according to the traffic of the users, making it possible to provide the latter with the services of a packet data transmission network according, for example, to the recommendations of the CCITT (circuits permanent and / or switched and / or datagram).

 Subsystem 4 provides all the switching functions encountered in traditional circuit switches (access or transit). It is also dimensioned as a function of user traffic, throughout the power range covered by the switch system of the invention. Management is ensured by applications hosted in the IT subsystem 2.

 The subsystem 1 will now be described in more detail. The switch system of the invention is a distributed intelligence architecture which only exists through the interrelation of several machines (or processors). It is necessary that the multiprocessor efficiency of the system degrades only slightly with the increase in the number of processors (we know that the useful work carried out by a given processor of a set of processors cooperating together decreases when the number of processors of this together increases). To this end, each processor is provided with the necessary private resources (mainly bus and private memory) to minimize this drop in efficiency.

 Thus, as shown in FIG. 2, the multiprocessor system of the switch comprises n machines 5.1 to 5.n each consisting of a physical processor 6 and its private resources comprising for example a memory, a particular input-output interface, etc. The only common resource necessary remains the member 8 for exchanging messages between the tasks of the various processors, such a member 8 being, of course, non-existent in single processor structures. The bit rate necessary for such an exchange of messages, of the order of 5 to 20 Mbits / s, allows the use of a low-performance parallel bus, for example of the "Multibus" or VME type, as described below in reference to figure 3.

 The physical machines 5.1 to 5.n are each connected to a common parallel bus, to which are connected switching couplers 10.1 to 10.m, a member 11 for exchanging messages internal to the local cell, and a member 12 d exchange of messages to distant cells. Each processor 6 is connected to its private resources 7 by a private bus 13.

 Physical machines 5.1 to 5.n have only two types of logical interaction with their environment: inter-processor messages, and physical input-output to their couplers 10.1 to 10.n.

 The digital majority of switch couplers are specialized couplers of switching equipment, such as trunks and signalers. It is advantageous to make their location not very dependent on that of the processors with which they cooperate. This is why, as specified above, these couplers are connected, in the present case, to bus 9. This bus 9 has more diversified traffic than private buses 13, although the assignment of a determined coupler to a determined processor is very often static for a given configuration. It will be noted, however, that this independence in locating the couplers is only possible because the physical input-output rate of the couplers is very low with respect to the number of cycles due to messaging (local messages between processors and to the distant alveoli).

 The switched information has a linearly increasing bit rate with the capacity of the switch. They are exchanged on specific supports of small physical size, provided with an electrical standard and a protocol standard, with rustic technology (low speed and cost).

 In a preferred embodiment, to transmit raster information, a multipoint technique is used allowing the routing of information relating to the user practically without phase shift between the cells. Such a network is easily extensible depending on the capacity, without questioning the architecture. All the internal junctions of a switch are synchronized with one another in a manner known per se.

 The switch of the invention being multiservice, must be able to support a packet transmission service network.

These packets circulate on a specific network reserved on the media offered by the network of internal physical circuits of the switch. Thus, as shown in FIG. 4, a packet transmission service coupler 14 is connected to the bus 9. There is also connected to this bus 9 a service message server 15 and a message server relating to the users 16. These two servers 15, 16 are also connected to a physical circuit switch 17, itself connected to the packet transmission network.

This multipoint network also serves to support the exchange of messages between the cells. To this end, the server 15 has been provided to route the inter-cell service messages.

 From the point of view of physical location, the switch comprises several elementary physical units called alveoli.

The cell constitutes the switch's defense unit since the decommissioning of a cell does not necessarily jeopardize the survival of the switch to which it belongs. If no cell is vital for the survival of the switch, this switch is said to be duplicated, and in this case each cell has a certain autonomy: it has its own power supply, its own time base, etc., and it is relatively independent of neighboring cells.

 The general synchronization of the switching is ensured by an internal clock device, located in a cell called the master cell, and distributing the time to slave clock devices located in the other cells (slave cells), each clock device slave distributing the time in his cell. The master clock device can be controlled by a selectable master (pilot) clock, and a backup master clock can be provided.

 The computer subsystem 2 is mainly characterized by its multiprocessor design in which the dialogs between the logical concepts (functions, tasks, ...) are ensured by the data switching subsystem, in a transparent manner, and by the allocation of private means to individual processors that do not penalize their intrinsic performance in the multiprocessor environment. In addition, this subsystem 2 is advantageously characterized by an optimization for medium volume software (for example of volume between 100 K bytes and 4 M byte), by the use of high level languages, as well as by a monitor and a debugger geared towards switching applications.

 From the point of view of physical implementation, advantageously, the natural framework for executing the software procedures is the task, which corresponds to the notion of deferred task of conventional operating systems. Each task has its own real-time framework and can be defined by attributes such as the declaration and launch parameters, the code segment executable at declaration, the code segment executable at launch, the complete context of registers, stacks execution, symbolic priority at launch, logical address space, etc.

For example, in the case of processing a call, a task is the natural framework for managing a half-call (or the call log for a conference call with n parties). A task is created in a logical address space to which it has access. This space may or may not be divided into segments having different access rights (for example: read / write, or read only ...).

 From a software point of view, the fact that a task belongs to a set of tasks sharing the same logical address space then constitutes the only guarantee of sharing the same memory space with another task of this set. In all other cases, two given tasks, therefore not belonging to the same set, must be considered as not sharing the same physical memory, that is to say as executing in another address space under the control of another machine and forming part of another elementary switch. These tasks must then communicate by exchanging messages using a device, both hardware and specialized software.

 When the system is configured, the tasks are assigned to a specific physical machine which will execute them throughout the lifetime of the system. The number of these machines depends solely on the processing power sought, and is not linked to the functional role of the software tasks to be executed. Software tasks communicate with each other in a unique and transparent manner vis-à-vis their physical location on a specific processor. Thus, the software of a small and a large switch differ only in their configuration directives.

 When a task has to interact with another task, it borrows a transport device. This transport device is divided into physical layers linked to the physical distance of two tasks. We can then define for example a layer local to the processor (transport between local tasks relating to the same processor), a layer local to the cell (transport between tasks relating to processors different from the same cell), a local layer to a node (transport between tasks relating to different cells of the same physical location), a layer local to the network (transport between tasks relating to different nodes of the same physical location), and a transport layer to the outside (using other transmission protocols). In this case, the network is considered as a single set of tasks.

 The device for transporting service messages between the different tasks is seen by users as a network having its own autonomy. The realization of this network is made according to the cutting in layers of the ISO standard: the users constitute the application layer and the only interface which is visible to them is the classic application and presentation interface. The software for this internal transport network constitutes a specific subsystem broken down into physical components linked to the management of the transit levels between the physical layers mentioned above.

 The packet switching subsystem 3 carries information. between the different subscribers of the switch. The various services relating to internal subscribers and external subscribers are physically distinct but their functional and physical architecture is identical. This makes it possible to size the service relating to internal subscribers according to the architecture of the elementary switches and the network, and to size the service relating to external subscribers according to the traffic of users. However, the operation of these two services being identical in the present case, the internal subscriber service can itself be a subscriber of the external subscriber service.

 The internal packet network architecture respects the OSI layer structure of the ISO. The external service, having no subscribers in the network of the switch of the invention, is connected to the internal service on the network layer to allow the accessibility of internal subscribers. The two internal and external services operate identically, and differ in connection protocols used for external subscribers, according to the standards in force (that is to say in OSI levels 1, 2 and 3).

 The service network of internal subscribers of a node is built around virtual loops established by the brewer of an elementary switch. These loops connect several signalers, for example of the HDLC type, normally located on different common buses. A loop is formed by the connection of several time intervals from the brewer and going towards it. These time intervals constitute elementary logical paths and can, of course, be located on identical or different physical paths (junctions).

 Since the bit rate of a loop is generally reduced (16, 32 or 64 kbit / s), it is necessary to use several loops in a switch. The number of flaggers in a loop is limited by the total loop throughput. Since the routing of a message in the switch can use several loops, the network software is responsible for regulating the route.

 The loops of a switching node are managed by the internal defense task of the node. This task, physically located in one of the decentralized intelligences of the node, has its own route and is capable, among other functions, of exchanging defense messages vis-à-vis each signalman. It uses signaling to detect batches of inaccessible or unusable resources, and it reconfigures the loop by actuating the stirrer to remove the "dead branches" (unusable in messaging), which can then be used to support test and test loops. maintenance.

 Thus, the service network of internal subscribers allows the computer subsystem 2 to be distributed among several processors and to delegate tasks to lighter and more numerous decentralized intelligences. This ensures the uniqueness of hardware and software development and the independence between its constitution and its external interface (which makes it possible to easily ensure its future development), and therefore it guarantees its subsequent extension in transmission power in a simple way and inexpensive.

 The physical circuit subsystem 4 is constructed as a traditional circuit switch core. I1 essentially comprises four main sub-assemblies: chain cores (elementary switches capable of switching internal junctions between them), transit junctions (interfacing the internal junctions with transmission equipment to form, by mesh, a network of switches) , subscriber junctions (analog or digital, multiservices in particular), and satellite servers (for example, voice signalers channel by channel, modulation transcoders, clock servers, radio synchronization servers, etc.) .

 All these sub-assemblies easily cooperate with each other thanks to an appropriate internal junction standard with which they are all compatible and which allows their interconnection. They are supervised by the computer subsystem 2 vis-à-vis which they behave like slave couplers, accessible by the input / output function supported by their common bus.

 Thus, the switch of the invention is presented as a set of cells meshed with speech and data paths, the data path having a practically constant transit time. Each cell is independent of the others and can be isolated or fail without causing the system to shut down. Network software is distributed, preferably fully or almost completely distributed; the processors are autonomous, and their software dialogues by exchanging messages.

Claims (6)

 1. Architecture switch, characterized in that it has a mono-multiprocessor structure (5.1 to 5.n), with software at least partially distributed, with several similar cells, each cell comprising a local interprocessor bus (9), and a local bus (13) completely decoupled from the interprocessor bus, the subscriber information circuit being decoupled (16) from the processor information circuit (9).  2. Switch according to claim 1, characterized in that all the cells are synchronous.  3. Switch according to one of claims 1 or 2, characterized in that the cells have functional entities which are supervised by decentralized control units located in their cell.  4. Switch according to one of claims 1 to 3, characterized in that the control units (6) communicate with each other by a packet network internal to the switch.  5. Switch according to claim 4, characterized in that inside a same cell the packet network borrows the support of a queue network in memory according to the technique of hypertreillis.  6. Switch according to one of the claims 4 or 5, characterized in that outside of the same cell the packet network is meshed in a hypercube and follows high-flow paths of the internal arteries.