FR2586877A1 - Adaptive equaliser device for digital data transmission installation - Google Patents

Abstract

The device comprises an adaptive data equaliser 10 placed upstream of a decision unit supplying an estimated value of the data. It moreover includes a phase equaliser for determining the phase average over a specified number of successive data transitions and a digital phase-locking loop driven by the said equaliser and controlling a sampler of the data received.

Description

Adaptive Equalizer Device for Digital Data Transmission System
The invention relates to digital data transmission installations and more particularly to a recursive equalizer device for such installations. It finds a particularly important, although not exclusive, application in digital transmission facilities using the local telecommunications distribution network.

 The current telecommunications distribution network is extremely heterogeneous: it includes cables of various lengths and diameters. A line serving a subscriber is generally constituted by cascading different lengths of cable having different characteristics, resulting in impedance mismatches.

 In spite of this heterogeneous character, the local distribution network is correctly adapted to the analog transmission of the telephone signal, essentially consisting of speech in the band ranging from 300 to 3400 Hz. But the digitization of this network to offer to the different As a subscriber to a large number of new telecommunication services requiring high-speed data transmission, it is planned to provide users with a useful bit rate of 144 kbit / s, including two 64 kbit / s channels. a 16 kbits service channel, in bidirectional transmission between the central office and the subscriber.

 The problems posed by this digitization are already known. We will now briefly remind them.

by limiting itself to a particular case that can be considered as representative, that in which a bidirectional transmission must be performed on two distinct metal pairs (a similar problem that lends itself to the same solution according to the invention being encountered in the case of installations two son equipped with an echo canceller).

 The code used to perform the transmission is usually a bipolar code, return or no return to zero (RZ or NRZ), other codes are however possible. A first problem arises at the subscriber side reception, because the receiver of the subscriber must be able to regenerate the 160 kHz clock signal for re-transmitting data from the subscriber to the central office.

The distribution network acts on digital signals as a filter with linear characteristics. To compensate for this distortion and the phenomenon of interference between successive symbols that it causes, it has already been proposed to use adaptive equalizers s. The principle of such equalizers is described in many documents, for example in "Adaptative equalization" by Schahid Qureshi, IEEE COMMUNICATIONS
MAGAZINE, March 1982, pp. 9-16 and in "Adaptive receivers for high-speed data transmission", by C. MACCHI et al., Annals of Telecommunications, 30, No. 9-10, 1975. Figure 1 shows, as a simple example, a possible equalizer arrangement 10, constituted by an adaptive recursive filter, in the receiver 26 of a data transmission installation.

The received signal Sr is applied to an adder 20 which also receives the output signal of a correction loop. The signal R corrected using an estimation of the effects of the transmission is applied to a decision element 12, constituted by a threshold comparator, which provides an estimate of the data transmitted. The estimated value is compared with R in a comparator 14 which provides an estimate ê of the error, applied to an analog / digital converter 16. The output of the analog / digital converter is applied to the matching inputs of the equalizer 10, The most frequently used adaptation algorithm is the gradient algorithm, which will be discussed later in detail, but other algorithms such as sign (which only takes into account the sign of the error ê).

 Finally, the digital output of the recursive equalizer 10 is applied, via a digital-to-analog converter 18, to the input minus the adder 20 to correct the received signal Sr.

 Before further describing the known devices and their limitations, then the invention, we will recall some indications on the digital transmission on local distribution network, limiting itself to the case of a bipolar code.

 In the case of such a code, the binary data of a sequence t ..., b (i), ...], which can take the values 0 and 1, are sent online, in the form of values d ( i) which have the value 0 when b (i) = 0, the value +1 or -1, alternatively, when b (i) = 1.

In this case, there is no linear relationship between b (i) and d (i). But, to show the impulse response of the transmission channel, it is desirable to reduce the case of the bipolar code to that of a linear code. For this, we introduce an auxiliary variable a (i) such that
a <i) = b (i) 6) a (i-1)
d (i) = a (i) - a (i-1).

 We see that the second of the relations above, which links the value emitted in line to auxiliary variable, is linear.

 The transformation that has just been defined is obviously not necessary when there is a linear relationship between the value transmitted and the data to be transmitted, which is the case with the binary code or the biphase code for example.

 The transmission medium 22 connecting the transmitter 24 to the receiver can be characterized by its impulse response. In the case of an ideal channel, the pulse emitted by the transmitter 24 is received by the receiver 26 (FIG. 1) after a delay which depends on the length of the channel, with a weakening, but with a shape and a duration equal to those of the transmitted pulse. On the other hand, in the real case, the pulse representative of the value d (i) spreads and there is the appearance of the phenomenon of intersymbol interference, frequently called by the abbreviation ISI, whose gravity increases with the flow rate of on the line.

 In what follows, we will denote by h (i) the samples of the impulse response taken with respect to the maximum of this response, denoted by h (O), the sampling taking place at the working frequency, inverse of the duration T assigned to each symbol.

If we denote by N the value of i beyond which the interference phenomenon becomes negligible, the samples h (i), with - 1 i i <N, represent the impulse response.

 In the practical case, which is that of the cables of the existing local distribution network, h (-1) is negligible compared to h (O), which means that one can dispense with the use of a transverse equalizer and adopt, as an equalizer 10, a purely adaptive recursive filter to provide a proper estimate of the data d. issued online.

In this case, the signal received at the instant nT (T being the duration assigned to each symbol) will be

Equation (1) above can also be written

 This last equation shows that the received signal has two terms, the first being the ideal value and the second representing the intersymbol interference, which will be designated t (nT).

A purely recursive adaptive equalizer provides an estimate of the ISI t (nT)
- an estimate of (ni) received data, and
an estimate Ah (i) of the coefficients of the impulse response

By subtraction (in the adder 20 on the
1) of the estimate t of the ISI to the received signal Sr, we obtain the signal R which is applied to the decision element 12

After convergence, the estimated values # (i) are very little different from h (i) and the estimated values â (i) are equal to a (i) .The difference between the last two terms of equation (4) is then reduces to a value e (nT):

 It can be seen that, under these conditions, the data a (n) can be recovered, but provided the gain h (O) is known: a first solution consists in using an automatic gain control circuit placed upstream of the equalizer (circuit 28 indicated in phantom in Figure 1) to make h (O) equal to 1 regardless of the attenuation provided by the transmission channel 22. In this case, in binary code, the estimate â (n) the received data is done by simple determination of the sign of R (nT).

to (n) = sign [R (nT)] (6)
As indicated above, the coefficients h (i) of the equalizer 10 are generally adapted according to the algorithm of the gradient h (i) n + 1 = h (i) n +. [R (nT) -a (n)]. (ni) (7)
In this equation, p represents the gain or not of incrementation of the algorithm and the term R (nT) - & n) represents the estimated error on the data received at time nT.

 The value of p is chosen in the form of a compromise between a low value, making it possible to ensure convergence, and a high value, which reduces the convergence time.

In the case where there is no circuit for reducing h (O) to 1, equations (6) and (7) are replaced by
((n) = sign Eh (O) .a (n) + # (n)] (6a) h (i) n + 1 = h (i) n +. [R (nT) -α (n). h (O)]. (ni) (7a)
The estimated value h (0) can be obtained recursively by: # (O) n + 1 = (1- #) #n (O) + # | Sr (nT) | (8)
The receptor shown by way of example in FIG. 2 implements the method that has just been defined. It includes elements similar to those already shown in
Figure 1. It also comprises a clock recovery block 30 placed upstream of an analgesic / digital converter 32 for allowing the sampling of the signal S (r). But the correct recovery of the samples requires that the phase of sampling is correct, otherwise the equalizer 10 can function in good conditions, and the parallel interference rate must be low enough for the clock recovery unit 30 to work under acceptable conditions.

 The first problem can be solved in a simple way only when the transmission channel has known and invariable characteristics: it suffices then to insert an adjustable network 34 between the block 30 and the converter 32 and to adjust the phase once and for all. manually.

 On the other hand, a self-adaptive adjustment becomes necessary when the phase is likely to evolve for example as a result of frequency slip phenomena or phase jitter. Various solutions have already been proposed to solve this problem. The article "A New Equalizer: Dual Sampling Equalizer by Odile Macchi and Coll A. TELEC 30, No.

9-10, 1975, pp. 1-8 proposes to use a multiple-sampling equalizer. But the operation of this equalizer implies that the clock signal, whose exact frequency is not available to the receiver, is recovered by an auxiliary means.

 Thus we see reappearing the second problem, which is that of the correct recovery of the clock signal in the presence of a significant ISI rate.

 Moreover, the multiple sampling equalizers which have been proposed are of the transverse type, with a large number of taps, the implementation of which involves a large number of multiplications. This is an important complication compared to using a non-recursive equalizer, especially when the data to be retrieved can only take the values +1 and -1, or +1 and O.

 The aim of the invention is to provide a recursive equalizer device for a digital data transmission installation, of the type comprising an adaptive data equalizer placed upstream of a decision-making device providing an estimated value of the data, a device capable of automatically adapting to the nature of the network and tolerate significant phase variations and a high ISI rate, while implementing only relatively simple means.

 For this purpose, the invention notably proposes a device of the type defined above, furthermore comprising means for determining the sampling phase average over a given number of successive data transitions and a controlled digital phase-locked loop. by these means and controlling a sampler of the received data.

 The data equalizer may in particular be of the known type comprising delay means simultaneously providing several successive estimated values and means for adapting the weighting coefficients corresponding to these estimated values. The phase and frequency equalizer may then advantageously be intended to use these estimated values, but adapt only when there is a transition between successive estimated values (between +1 and -I for example).

 According to another aspect of the invention, the device also includes a phase / frequency equalizer adapted to determine the sign of the sample phase average of the data from a slow clock signal obtained by dividing the signal provided by a fast local clock and for adding or subtracting a pulse in the output signal of the fast clock following the sign of said phase average.

 In practice, the device will implement two recursive equalizers coupled via the delay means. The first of the equalizers sampled at 1 / T (T being the duration assigned to each data), can be traditional if it will be used to recover the data with a conventional adaptation algorithm.

which will be for example the algorithm of the gradient or the algorithm of the sign. The second equalizer will be sampled at 1 / T with a delay of T / 2 and will provide advance or delay information for driving a fully digital lock loop. to recover the transmission frequency and to converge the sampling phase of the first equalizer towards its optimum, with the result that h (0) will be very much greater than h (-1) and that the received data will be represented in such a way that reliable by the sign of R (nT ?, according to equation (6).

 The adaptation algorithm of the second equalizer can no longer be one of the conventional algorithms known to compensate the ISI but, in practice, we will always keep a purely recursive equalizer, to avoid complex multiplications.

 Thanks to the implementation of the device that has just been described, it will be easy to recover, after analog / digital conversion and automatic gain control, these two operations being performed in any order, the data and the clock to the times, in an entirely digital way. This last feature is particularly advantageous in that it makes it possible to implement specific integrated circuits.

The invention will be better understood on reading the following description of a particular embodiment, given by way of non-limiting example. The description refers to the accompanying drawings in which
FIG. 1, already mentioned, is a block diagram of a known receiver with adaptive recursive equalizer
FIG. 2, similar to FIG. 1, is a block diagram of a receiver comprising a phase correction sampler.
- Figure 3 is a timing diagram showing an example of a data sequence
- Figure @ is a block diagram of an equalizer device according to one embodiment of the invention
- Figure 5 is a diagram showing the constitution of the equalizers of Figure 4
FIGS. 6A and 6B are timing diagrams for displaying the phase correction.

The invention will be described by way of example in the case of an equalizer device intended for a data transmission installation where the received signal
Sr (nT) is of the form given by formula (2) above, the equalizer device comprising a data equalizer estimating intersymbol interference by the formula (3). The decision body will receive the signal
R (nT) = SrtnT) - t (nT) and the estimate å (nT) of the received data, provided by the decision organ, will be labeledR (nT)].

The data equalizer will be adapted by an algorithm that will be assumed, in what follows, the gradient algorithm, that is to say, for the coefficient # (i) n + 1 = # (i) n + .E (nT) .a (ni) (9) where E designates the error signal
E (nT) = R (nT) - sign [R (nT)] (10)
Since the phase and frequency equalization is sufficient for the sampling to be done under acceptable conditions, the coefficients of the data equalizer will converge to a point of equilibrium such that
R (nT) = h (-1) .a (n + 1) + h (O) .a (n) (4a)
According to the invention, the equalizer device comprises, in addition to the data equalizer, a phase / frequency equalizer whose function will first be described, before giving a particular mode of execution.

We can assimilate the function of the phase equalizer / frequency to the artificial reconstitution of the diagram of the eye of the digital transmission. In the case of a bipolar auxiliary variable, which can take the values +1 and -1, we can write the signal
R (nT) in the form
R (nT) = â (n) + E (nT) (11)
It is possible to view the signal R (nT).

for example using a digital / analog converter placed at the input of the device. In this case we see a sequence of values that differs from +1 and -1 in an amount corresponding to the noise provided by E (nT). Figure 3 shows an example of sample- ing corresponding to the case where the data å (n) takes the successive values +1, +1, -1, -1, +1, -1.

 From a sampling of the signal Sr carried out with a shift of T / 2 compared to the sampling providing the values R, we will see that we can synthesize a signal E. And we will see that we must act on the phase to converge E # (whose optimal value is not known in the general case) to O in the case where the data a (n) and a (n + 1) are of opposite signs, that is to say say that there is a transition of the signal R (nT). Figure 3 shows two cases of such transitions.

It will be assumed that the sampling used for the phase / frequency equalization is lagging behind the sampling used for the data equalization, the delay being equal to T / 2 (the reasoning being similar in case of advance) . In this case, the signal used for phase / frequency equalization will be

en utilisant les valeurs estimées â(n-i) fournies par l'égaliseur de données récursif ayant la constitution décrite plus haut.In formula (12), each term h # (i) represents a sample of the impulse response h (t) of the transmission channel at time nT + T / 2
h # (i) = h (iT + T / 2) (13)
We can search for an estimate h T for 1 # is N and then calculate the value t by a formula similar to formula (3) above

using the estimated values ((ni) provided by the recursive data equalizer having the constitution described above.

From the values t we can calculate the estimated error E that we will try to reduce to O during the transitions E # (nT + T / 2) = Sr (nT + T / 2) - # (nT + T / 2) ) (15)
In practice, it can be assumed that the estimated values h # (i) are very little different from the exact values h (i) when the data equalizer has
T converged towards its equilibrium point for which
R (nT) = h (-1) .a (n + 1) + h (O) .a (n) (4a)
And in this case, we have E # (nT + T / 2) = h # (- 1) .a (n + 1) + h # (O) .a (n) + e (16) where # represents the estimation error on h T and a.

Convergence from h - h
In order to bring about the convergence of timed values h T (i) and to realize 1 adaptation of the phase, it is used that the value E # (nT + T / 2) must tend towards O during transitions of the signal R. Indeed, the phase / frequency equalizer matching algorithm can be [## (i)] n + 1 = [## (i)] n + vE # [(n-1) T + T / 2]. (n-1-i) [I-a (n). â (nl)] (17)
2 with 1 # i # N.

 And we see that in the second term of the equation the last factor is zero when the data â (n) and â (n-1) are of the same sign, so that the adaptation occurs only when the two received data are of opposite signs. The gain v is advantageously the same as the gain p of the data equalizer, although this is not essential.

 The formula (17) shows that the adaptation of ## can only occur after detection of â (n). It will therefore be necessary to use the phase / frequency equalizer with a delay with respect to the data equalizer.

RecuDeration of the clock and the Dhase
The phase and the clock frequency have to be determined in order to perform the sampling with a suitable synchronism.

For this, the invention uses a two-step process
- blocking of the sampling phase for a time long enough for the phase / frequency equalizer to converge towards an equilibrium giving a significant indication on the value E # (nT + T / 2) at the times of transition,
- evolution of the sampling phase to make E tend towards 0.

 For this purpose, it is advantageous to use a conventional phase-locked digital phase loop comprising a fast local clock * which makes it possible to obtain, by division, a "slow" clock signal at a fesiosynchronous frequency of the clock signal at frequency f of the received signal and an element for deleting or adding one pulse at a time in the signal supplied by the local clock, in order to move the phase of the slow clock.

Equalizer device
A device embodying the process just described will now be described, this device constituting only a particular example of embodiment.

 The device shown in Figures 4 and 5 has elements common to that of Figure 2 and which have the same reference number. More specifically, the receiver comprises an automatic gain control input amplifier 28 and an analog / digital converter 32. This converter uses the recovered clock signal, implementing the phase / frequency equalizer which will be described. further. The sampling is done at a frequency of 2f '= 1 / 2T, after correction by the phase equalizer / frequency, so as to allow, on the one hand, the data equalization, on the other hand, the equalization phase / frequency. The analog / digital converter may be placed upstream of the automatic gain control amplifier 28, provided that it has an increased dynamic.

 The digitally coded signal is switched, by a switch 36, alternately to the data equalizer 10 and to the phase / frequency equalizer 40, using a circuit shown schematically in the form of a switch 36, operated at the frequency 1 / T by means of a frequency divider 38 which receives at the input the sampling frequency 2f '.

 The data equalizer 10 has a conventional general constitution. For the sake of simplicity only the adaptations of the coefficients h (i) and h # (i) for the coefficients h (1) and h # (i) have been shown in Figures 4 and 5.

 The data equalizer essentially comprises an adder 42 (FIG. 4) whose inputs receive the terms #..., So as to form the estimate t of the intersymbol interference, according to the equation (3).

The different simple products are made by an assembly of the kind shown in Figure 5. In the case where the two complement code is used for the internal representation of the data (n) estimated,
â (n) = 1 corresponds to the internal representation
O in the delay line constituted by a cascade of elements 42 (successive positions of a register for example),
â (n) = -1 corresponds to the internal representation I (sign complementing two).

 Under these conditions, the simple products ((ni). # (I) are realized by applying simple weights +1 and -1, according to the values stored in the delay line 42, to the coefficients # (i) obtained from E (nT). The advance of the bits in the register 42 is controlled at the rate of the reconstituted clock by correction of the local clock.

 The signal R (nT) is reconstituted in the sumator 20 by subtracting t (nT) from Sr (nT) in the additive 20. The decision element 44 then supplies the data item a (n), constituted by the sign of R {equation 6).

The error E (nT) is elaborated by subtracting the reconstituted data item a (n) to R with the aid of an adder 14.

 The evaluation and adaptation block of h (1) will alone be described, among all the adaptation blocks of # (i). This block 46 comprises an input multiplexer 48 which receives, on the one hand, the signal E (nT), on the other hand.

the incrementation step LI of the gradient algorithm, set once and for all.

 In practice, we will generally choose a value of p constituted by a negative power of 2, so that the multiplication is reduced to a simple shift. A value between 2-6 and 2-10 will generally be satisfactory.

 At the output of the multiplier 48, a value is obtained .E (nT). This value is multiplied, in a second multiplier 50, by the estimated datum â (n-1) which can take the value +1 or -1.

 The result obtained is applied to an adder 52, to be added to the previous value of h (1) and the result of this last operation replaces the old value of # (1).

 The phase / frequency equalizer 40 uses as the input signal the signal Sr (nT + T / 2) fed by the switch 36 to the output of the analog / digital converter 32.

 Like the data equalizer, the phase / frequency equalizer 40 comprises an adder 54 for calculating the sum of equation (14), i.e. ##.

The products ## (i) x â (ni) are made by circuits 56 having a constitution similar to that of the circuit 46. But the coefficients are ## (i) instead of being h (i), the data (ni) being taken from the delay line 42, as used for data equalization.

 The adder 54 thus provides the signal t # (nT + T / 2) which is subtracted from the signal Sr (nT + T / 2) in an adder 58 to provide the signal E # (nT + T / 2).

The adaptation of thieves estimated h # (i) coefficients by the formula (17) above requires that we have E # [(n-1) T + T / 2]. For this, the adapter comprises a block 60 providing a delay T, connected to the output of the adder 58. The implementation of the equation involves looking for the convergence of E # to zero only in cases where there is transition.For this, the circuit comprises a block 62 with EXCLUSIVE OR gate (XOR) which generates the result of
1-â (n) .a (n-1)
2
The output of the block 62 (at Q when there is a transition) is connected to one of the inputs of the calculation blocks of the estimated values of the coefficients h #. The calculation block of ## (1) (only represented) has a constitution similar to that of block 46. It comprises a multiplier 48j by p, a multiplier 64 by +1 or -1 which receives the output of block 62, a multiplier 50a by â (n-2) and an adder 53a for forming the new value # ~ (1) from the previous value. Only the multi
Tner 64 forming the validation portion has no counterpart in block 46 and the value â (n-2) replaces â (n-1).

 The part of the phase / frequency equalizer which has just been described provides only an estimated value of the coefficients h # (1). It is supplemented by a digital phase locked loop which comprises the fixed frequency clock Mf '(f' being little different from the bit frequency f), a correction circuit capable of adding a pulse (by doubling the frequency a pulse emitted by 66 for example) or to delete one, and a divider 70 by M / 2 whose output drives the analog / digital converter 32.

Such an arrangement, supplemented by a phase comparator, exists in most phase locked loops. But in the case of the invention, this comparator is replaced by the phase equalizer / frequency 40, which we will see that it is constituted to calculate the average phase MP on a number K bit periods, not taking into account that transitions, in accordance with the formula

<tb> MP (n) <SEP> = <SEP> E <SEP> sign <SEP> Butsign {Etfn-1) + i) TT / 2]]. åznt
<tb><SEP> j = O
<tb> [1-â (n-1 + j) .â (n + j)]
2 (18)
Since HP (n) is available only every K periods, the phase adaptation can be done only once every K periods, which will lead to invalidating the correction circuit 68 permanently, except every K periods when the adaptation of the phase f 'will be made according to the formula #f' (mkT) = #f, [m (k-1) T] + sign (MP) x2 # / M (19)
#f; being the phase of the clock signal at the output of the divider TO.

 This formula expresses that there must be added a pulse to the fast clock 66 to advance the phase if MP is negative and suppression of a pulse to delay the phase if MP is positive.

We see in Figure 6A a case where the value of-MP will lead to a correction by phase delay. The signal E # (nT + T / 2) having the same sign as
R (nT) during a transition on R (nT), it is necessary to delay the sampling phase to decrease E (nT + T / 2) by approximating the sampling time of the -data
R [(n + 1) T]. The following values R [(n + 1) T] and R [(n + 2) T] having the same sign do not contribute to the calculation of the average.

 Figure 68 shows the opposite case, which will cause a correction in advance of phase.

To implement the approach that has just been defined, the circuit 68 is associated with a control block 72 capable of providing it
a validation signal VEP authorizing the correction,
an RT / AV signal indicating the direction of the correction to be made.

 The block 72 shown in FIG. 4 comprises a counter T4 modulo K which receives the signals indicative of transition VT provided by block 62, it supplies the signal VEP for validation validation to the phase-locked loop every K transitions and in the same way time returns to zero. The block also includes a circuit 76 which, associated with a threshold circuit 77, implements the formula (18) and provides MP. It may be constituted by a memory or a directional dial loop looped through an adder 78 to make the algebraic sum of the pulses it receives between two resets by the counter 74. The input of the adder 78 not connected to the output must receive the +1 and -1 signals to accumulate during transitions. For this purpose, it is connected to the output of the summator 58 which supplies E by the delay element 60, a threshold detector 80, a multiplier 82 which receives (n-1) supplied by the equalizer 10. A second multiplier 84 receives VT and the output of multiplier 82 and feeds counter 76 through adder 78.

It can be seen that the contents of the memory or the counter 76 are incremented or decremented according to the product value of the sign of E # [[n-1) T + T / 2] by the transition enable signal VT and by the signal
If VT = 1 and if the sign of the product of E # by ((n-1) is equal to 1, in addition to 2, the value of MP stored in the counter 76 is decremented. Otherwise, it is incremented. If VT = O, there is no change in the MP value.

After K cycles of the VT signal after the previous reset of the counter 74, the VEP signal is generated. The digital loop is then actuated by the RT / AV signal according to equation (19). If the sign of HP is positive, the clock is delayed. If this sign is negative, the clock is advanced. In addition to 2, the clock must be delayed or advanced according to
HP is 0 or 1.

In response to the simultaneous presence of the signal
VEP (phase error validation) and signal / RT / AV, there are:
- suppression of a pulse by the circuit 68 if RT / AV t O to delay the phase of the clock available at the output of the divider 70,
- insertion of a pulse if RT / AV = 1 to advance the phase of the clock.

The different constant coefficients that intervene in the equations will be chosen according to the practical conditions. However, values in the following areas will generally be adopted
and v: 2-6 to 2-10, advantageously 2-7 in the case of the local area network,
k: 23 to 25, advantageously 24 in the same case, H: 2 to 2, advantageously 26.

The invention is capable of numerous variants. In particular, the phase / frequency equalizer and the data equalizer may be of a different type from those shown. For example, the summers 42 and 54 may be replaced by memories whose addresses are constituted by the content of the delay line providing the successor values of â (Figure 5). The products by the values of h (i) and ### (i) can be performed in the same way. The phase-locked loop may have any of the known constitutions. The adaptation algorithms may be other than the gradient algorithm and the equalizers may in particular be provided so that they implement the sign algorithm. , which corresponds to the formulas (9bis) and (17bis) ci-apress which replace the formulas (9> and (17)
[h (i)] n + 1 = [h (i)] n + sign [E (nt)]. (n-1) (9a) [# (i)] n + 1 = [## (i ) n + v sign #E # [(n-1) T + T / 2] #. â (n-1-i)
1-a (n) .a (n-1) [-] (17bis)
2
In this case, the step of incrementation p or v must be smaller than in the case of the gradient algorithm.

 This phase locked loop can itself have very different constitutions and include.

instead of a fixed frequency fast clock, a voltage controlled frequency oscillator: the signal E # [(n-1) T + T / 2] .a (n-1) is then applied to the oscillator to modify its frequency per step when validated by the signal VEP of Figure 4. The counters 74 and 76 which provide a filtering function can themselves be replaced by a filter itself having a role of low-pass, still acting on the signal E # .â (n-1) .VEP and whose output controls the variable frequency oscillator. We know such achievements of filters, digital or analog.

 It should be understood that the scope of this patent extends to such variants, thus more generally than to any other remaining within the scope of equivalences.

 Whatever the embodiment adopted, the invention uses two recursive equalizers coupled by the delay line storing successive values of the received data. One of the equalizers constitutes a phase equalizer and converts it to zero when there is has transition on the received data. The error from the phase equalizer controls a phase locked loop that allows data to be sampled at the correct frequency and phase.

Claims (8)

 A recursive equalizer device for a digital data transmission facility, comprising an adaptive data equalizer (10) upstream of a decision element (44) providing an estimated value of the data, characterized in that it further comprises a phase equalizer for determining the phase average over a given number of successive data transitions and a digital phase locked loop driven by said equalizer and co = a sampler of the received data.  A recursive equalizer device for a digital data transmission facility, comprising an adaptive data equalizer (10) upstream of a decision element (44) providing an estimated value of the data, characterized in that it also comprises a phase / frequency equalizer adapted to determine the sign of the phase average of sampling the data from a slow clock signal obtained by dividing the signal provided by a fast local clock (66) and adding or subtract a pulse in the output signal of the fast clock following the sign of said phase average.  3. Device according to claim 1, caraeterized in that the data equalizer comprises delay means simultaneously providing a plurality of successive estimated values and means for adjusting the weighting coefficients corresponding to these estimated values.  4. Device according to claim 3, characterized in that the phase equalizer / frequency is provided to use said estimated values, but adapt only during transitions between successive estimated values.  5. Device according to claim 1 or 2, characterized in that the phase equalizer is provided to operate according to the matching algorithm [## (i)] n + 1 = ttl (i)] n + vE [ (n-1) T + T / 2]. at (n-1-i)  [1-â (n), â (n-1)]  2 (17)  Where [h T (i)] designates the estimated values of the impulse response of the transmission channel at times at equal distances of successive sampling instants, v is an incrementing step, E denotes a synthesized signal chosen to converge to O during transitions between data, to designate the successive estimated data, T is the bit period of the signal.  A recursive equalizer device for a digital data transmission facility comprising an adaptive data equalizer (10) upstream of a decision element (44) providing an estimated value of (n) successive data and having a line delay simultaneously providing the successive reconstructed data at (nN-1), ..., â (n), characterized in that it further comprises  a switching switch (36) controlled by a local sampling clock, at double frequency of the bit frequency of the data, for routing the data samples to the data equalizer (10) and supplying samples taken at halfway between the data samples,  a phase equalizer (40) coupled to said data equalizer by the line supplying the successive values of the estimated data and designed to adapt only to the transitions of the signal supplied by the data equalizer, said phase equalizer being connected from to receive said samples mid-way and being adapted to adapt only during transitions of the estimated data signal to force the zero convergence of a signal E # (nT + T / 2) :: E # ( nT + T / 2) = Sr (nT + T / 2) -t # (nT + T / 2) Sr (nT + T / 2) being the half-way samples and being the intersymbol interference, and means for calculating the phase average over several transitions of the data, from the sign of the signal E # (nT + T / 2 ), and a phase locked loop controlling the clock signal from the calculated phase average.  7. Device according to claim 6, charac terized in that the phase-locked loop comprises a fast local clock (66) at a frequency M f ', f' being a plesiosynchronous frequency of the bit frequency f of the data, a circuit (68) ) capable of adding or deleting a pulse in the output signal of the fast clock, a divisor by M / 2 directly feeding the data sampling converter and controlling, via a divisor by two, the switch switch (36).  8. Device according to claim 6 or 7, characterized in that the calculating means comprise algebraic summation means of the quantities E # [(n-1) + j) T + T / 2] .a (n-1 + j ) during data transitions,  and means for causing adaptation after algebraic summation over K transitions, where K is a predetermined integer.