FR2574197A1 - DATA SEQUENCE TYPE PROCESSOR - Google Patents

Abstract

THE DATA SEQUENCE PROCESSOR IS A PROCESSOR THE OPERATION OF WHICH IS NOT GOVERNED BY THE SEQUENTIAL CONDUCT OF A PROGRAM BUT BY THE AVAILABILITY OF THE DATA NECESSARY FOR THE PERFORMANCE OF SPECIFIC FUNCTIONS. IT INCLUDES IN PARTICULAR SEVERAL INFORMATION MODULE PROCESSORS 23A-23C CONNECTED TO A COMMON BUS 21 TO WHICH IS ALSO CONNECTED AN ARBITRATION CIRCUIT 32 WHICH MANAGES ACCESS TO THE BUS. THE DATA ARE ORGANIZED IN INFORMATION MODULES EACH INCLUDING A LABEL AREA AND AN OPERAND DATA AREA, AND INTERCOMMUNICATION BETWEEN THE DIFFERENT INFORMATION MODULE PROCESSORS IS MADE BY TRANSFERRING INFORMATION MODULES ON THE COMMON BUS. EACH INFORMATION MODULE PROCESSOR INCLUDES A NUMBER OF PROCESSING UNITS 25A-25C PERFORMING THE REQUIRED FUNCTIONS, AND INPUT AND OUTPUT PROCESSORS 30, 31.

Description

DATA SEQUENCE TYPE PROCESSOR

  The present invention relates to a computer of the

  type using a data sequence processor. Con-

  trairement to a conventional computer, in which the execution

  instruction is carried out under the control of a program sequence, the data sequence processor works under the dependence of the availability of operand data. In a conventional computer, the circulation of data is controlled by the sequential execution of a program. From the point of view of an organization chart, the program is a sequential set of operations executed one after the other. If the program requires the calculation of several

  functions, these calculations are usually performed

killed in series.

  For example, if a program is to accomplish

  two operations, the first consisting of a utility function

  reading data entry information A, B and C and

  producing output information D, and the second

  sistant to a function that uses information from

  data entry B and C and which produces information of

  output E, these operations are carried out sequentially.

  In a h a bi tu e e way, all data is saved

  entered into a common memory. The computer performs the following actions: (1) it accesses the data in order

  A, then B, then C in the memory, (2) it performs the operations

  arithmetic or logical rations necessary to implement the function, and (3) it produces the output data D which are then introduced into the memory. Computer

  then accesses the memory again to obtain the values

  their data B and C which are used to perform

  the arithmetic or logical operations of the following function

  boasts. The resulting output value E is in turn entered into the memory. In such a conventional computer controlled by a program sequence, the speed at which processing can take place is limited by the rate at which the

  instructions can be executed in series, and by the -

  sequential access time to data in the common memory.

  This last limitation is linked to what is called the

  "Von Neumann's bottleneck", this expression

  signing the following reality: whatever the speed of operation of the processor, all the data must

  be aligned in a single file before they can be processed

  tees. In the example of the conventional computer controlled by a serial type program sequence which has just been described, the second function could not be performed before the completion of the first function, although the

  data (B and C) needed as information

  for the second function are already available in

  memory at the start of the calculation of the first

best function.

  A prior art technique for overcoming this speed limitation has been the use of multiple processors operating in parallel. For the example just described, we could program a computer equipped with parallel processors, so that

  the first function is performed by a processor

  while the second function is performed by a processor

  separate parallel. However, even in such a configuration

  tion, processors compete for access to the common data memory, which involves the same Von Neumann bottleneck. The first processor

-2574197

  must access data A, B and C sequentially, while the second processor must access data B and C sequentially and separately. This alignment in series of data thus imposes an inherent speed limitation, even for a computer with parallel processing of the type at

  control by program sequence.

  On the contrary, a data sequence processor has a fundamentally different organization. We use the

  parallel processing, but the bottleneck is eliminated-

  Von Neumann by distributing the data directly to the various parallel processing units. In each of these units, the requested function is performed as soon as the necessary data are available. We get a

  notable improvement in execution speed.

  In the example described above, the various data

  A, B and C are distributed directly and simultaneously to the various processing units. The processing unit which is assigned to the performance of the first function accepts the data A, B and C and it immediately performs the calculation of this function to give the output value

  D. Simultaneously, while data B and C are ap--

  applied to the first processing unit, they are also

  applied to the separate processing unit which has the

  appropriate configuration to perform the second function.

  This unit accepts data B and C and calculates immediately

  diat the second function, by producing an output value E. Thus, in a processor with data sequence, functional operations are carried out not in a sequential way, under the control of a program sequence, but under the dependence the availability of

operand data.

  An object of the invention is to provide a mode of

  realization of such a data sequence processor.

  This is achieved by a separate processor.

  data quency in which operand data is

  transmitted in the system in the form of information modules

  Each having a label area which contains an identification, and a data area which contains an operand data value. - The information modules are transmitted on a bus, here called a "traffic bus", to which several processors of information modules or "data sequence cards" are connected. Each information module processor includes one or more processing units

  and each of them has a configuration allowing it to

  perform a certain function requiring specific input data, or it can be controlled to

perform such a function.

  Each data sequence card also includes

  an input information module (PME) processor

  which controls the identification or label area of each

  module present on the circulation bus. The SME is looking for

  che information modules which contain operand data requested by the processing units which are on the same data sequence card. When the SME recognizes, by means of the identification contained in the

  tag area of the information module on the bus

  culation, that the present information module is requested by such a processing unit, it introduces the operand data coming from this information module into a memory which is located on the data sequence card itself. When all the requested operand data which is necessary for a particular processing unit

  have been received and entered in the memory of the PME, the uni-

  processing tee performs the function.

  By way of example, if the processing unit is to perform a function requiring input data A, B and C, the PME searches on the circulation bus for information modules having the zone identification values d 'label "A", "B" and "C". When these information modules

  are detected, the PME saves the data of operands cor-

  respondents. As soon as the operand values for the three input information "A", "B" and "C" have all been received,

  the processing unit can immediately perform the function.

  Each information module processor or card

  data sequence also includes a mo-

  output information module (PMS). As soon as the processing unit

  output data value, the PMS assem-

  ble this value in a new output information module.

  For example, if the processing unit performs a function having output information designated by "D", the PMS produces a new information module having in the area

  label an identification corresponding to "D", and contains

  in the data area the actual data value pro-

picked up by the processing unit.

  The PMS assembles the newly produced output information modules in a row to transmit them to the traffic bus. An arbitration circuit is associated with the circulation bus and this circuit interrogates each of the information module processors to determine the processors which have information modules ready to be transmitted. The arbitration circuit grants access to only one information module processor at a time, based on an appropriate rotating priority. The information module processor to which access is granted then transmits to the circulation bus the

  first information module in the queue.

  The invention also encompasses configurations with several traffic buses. The circulation buses are interconnected by processors of appropriate inter-bus information modules which transfer from one circulation bus to another only the information modules that request

the receiving bus.

  The computer configuration command of the pro-

  data sequence stopper of the invention allows a

  arbitrary assignment of specific functions to each

  processing units on data sequence cards

  individual born. It is thus possible to selectively reconfigure the system to optimize the performance for a particular application. Such a reconfiguration in fact constitutes a "programming" of the data sequence processor,

  allowing to realize a certain set of functions mu-

tally related.

  The invention will be better understood on reading the

  description which follows of embodiments, given at

  title of nonlimiting examples. The rest of the description

  refers to the appended drawings in which: FIG. 1 is a block diagram of the processor

  with a basic data sequence according to the invention.

  Figure 2 shows the format of an information module.

  training used in the data sequence processor

of figure 1.

  FIG. 3 is a schematic representation of a representative function implemented by a processing unit incorporated in the sequence processor

data in figure 1.

  Figure 4 is a schematic representation or "data flow diagram" of the set of mutually related functions that can be implemented by the

  Figure 1 data sequence processor.

  Figure 5 is a block diagram of a process

  representative information module that is used

in the system of figure 1.

  Figure 6 is a block diagram of another embodiment of the data sequence processor of

  the invention using two bus routing modules

  separate training, with means provided for the selective transfer of selected information modules between these buses. Figure 7 is a block diagram of a mode of

  realization of the inventive data sequence processor

  tion using several bus routing modules

interconnected training.

  Figure 8 is a block diagram showing a configuration for data input and / or output of the

  data sequence processor of the invention.

  Figure 9 is a block diagram of a system facilitating computer-controlled reconfiguration of a

  data sequence processor according to the invention.

  Figure 1 shows a basic data sequence processor, 20, according to the invention. It includes a bus 21 (sometimes called a "traffic bus"

  "), by which information modules are transferred

  mation. The information module format 22 (FIG. 2) comprises a label zone 22t containing a "label" or identifier, and a data zone 22d containing a

  actual operand data value.

  A number of input module processors

  formation 23 are connected to the data circulation bus 21 (sometimes each of the processors 23 is called a

  "data sequence card", and they are designated individually-

  by references 23a, 23b, etc.). Each processor

  of information module 23 includes a section of accomplis

  function 24 which contains one or more processing units 25. These processing units accomplish the

  real, arithmetic, mathematical, logical or other processing

  data received in an information module format

  tion from the data traffic bus.

  Each processing unit 25 has a configuration intended for the performance of a certain function (f)

  on some input data. This is shown diagrammatically

  tick in Figure 3, where the circle or "knot"

  26 represents a certain function (fa) which must be ac-

  complies with one of the processing units 25. The function (fa) requires three input data designated by the arrows

  or "arcs" bearing the references A (1), B (2) and C (3). The re-

  result of the performance of the function (fa) is the general

  ration of an output given by the arrow or the arc D (4). As a simple example, the function (fa) can be the calculation of a temperature gradient g in a wall having a thickness w, with an outside temperature to and an inside temperature ti, according to the formula: t - ti g = (Equation 1) w To perform this operation, the function unit 26 must receive three values of input data. In the example of figure 3, the outside temperature can be provided by the chemi * or the arc Ao The relative label

  to this arc is the number "l". So the input data re-

  presenting the outside temperature to could be re-

  presented by an information module having the format 22 of FIG. 2, in which the label part 22t contains the value "1" which indicates that the joint data are associated with the arc or with the path A (and therefore represent an outdoor temperature value to). Data area 22b

  would then contain the actual numerical value of the temperature

  outside ture to o Correspondingly, the inside temperature value ti can be provided on arc B having a value

  label "2", which means that its module format

  associated formation would have the value "2" in the labeling area

  quet 22t and the appropriate indoor temperature value ti in data area 22d. The same is true for the wall thickness value w applied to the arc C, having a label value of "3", which means that its information module would contain the value "3" in the zone 22t label and the appropriate thickness value

  wall w in data area 22d.

  When function 26 is executed (e.g.

  according to the example in equation (1) above), the value

  their resulting output is provided on an output arc D having the label "4". The data value calculated for the gradient g can thus be supplied according to an information module format, by an information module having a label zone value "4" (associated with the output arc D) and

  containing in the data area 22d the value of g, calculated

  using the input data that is applied to the

moment considered at node 26.

  By applying FIG. 3 to the real data sequence processor 20 of FIG. 1, it is noted that one of the processing units 25 would have the configuration suitable for implementing equation (1) above. The unit of

  treatment 25a could thus be constituted by a micro-

  processor programmed to implement this equation

  tion, or it could be made up of specialized hardware or firmware intended for implementation

from equation M1).

  To accumulate the data necessary for the units

  25, each data sequence card 23 includes

  takes an input information module (PME) processor

  , described below in more detail. The PME 30

  checks all the information modules transmitted on the bus

  data flow 21 to determine if any of them

  keeps data necessary for one of the processing units

  25 on the same data sequence card.

  In the example just described, in which the processing unit 25a implements equation (1) above, the PME 30 searches for information modules which have tag area values of "1", "2" and "3" 'because

  these information modules are those which contain the

  their data for the outside temperature to, the time

  indoor temperature t. and the wall thickness w, of which i

  the processing unit 25a needs as input data

  very. If such information modules are present on the data circulation bus 21, the input information module processor 31 accepts the module and stores the data contained in the data in an appropriate memory.

information module.

  As soon as the three data values t0, ti and w

  have all been received and registered in PME 30, the uni

  processing tee 25 can immediately perform the function (fa), i.e. it can immediately calculate the

  corresponding gradient value g, in accordance with the equa-

tion (1).

  The resulting value of the gradient g, calculated by the processing unit 25a itself, is supplied in the information module format, to be applied to the data circulation bus 21. To do this, the sequence card of Data 23 (Figure 1) includes an output information module processor (PMS) 31 which assembles information modules for application to the bus. As soon as the processing unit 25a has calculated the new value

  from g, this PMS 31 assembles an information module which

  holds in its label zone 22t the value "4" corresponding

  dant to the arc D (4) relative to the node or to the function 26 (fi-

  gure 3). The PMS 31 places in the data zone 22d of this information module the new value for the gradient g which has just been calculated by the processing unit 25a. The PMS 31 then signals to the bus 21 that this information module processor 23a contains a new information module

  ready to be applied to the data traffic bus.

  Later, when this information module is issued on

  bus 21, it becomes available for any milking unit

  ment which needs the gradient value g as

input data.

  The circulation of information modules on the

  bus 21 is controlled by an arbitration circuit 32 which

  performs an interrogation and access authorization operation. In an embodiment considered by way of example, the data circulation bus 21 can comprise a separate and dedicated interrogation signal line,

  and a separate and specific access authorization signal line

  specialized, going from the PMS 31 of each information module processor 23 to the arbitration circuit 22. A single information module can be transmitted on

  the data circulation bus 21 at any time.

  A representative system can have a rate of 4 MHz, so that the data traffic bus 21 can

  transmit four million information modules per week

  count, one at a time. Each information module can include

  32-bit ter, including a 16-bit 22t label area and

  a 16-bit data area 22d, and these 32 bits are trans-

  nmis in parallel on the data circulation bus 21.

  At all times, the arbitration circuit 32 determines, via the interrogation signal lines, which of the information module processors 23

  which currently contain an information module at-

  attempts to be transmitted to the data traffic bus. AT

  each cycle, the arbitration circuit 32 emits a signal of

  torization of access to only one of the processor modules

  formation 23 which are associated with bus 21, which allows this processor to transmit an information module on the bus

circulation of data.

  The arbitration circuit 32 advantageously uses,

  but not necessarily, a priority technique "tour-

  nante ". Initially, the arbitration circuit scans sequentially

  information module processors. (For example, if there are sixteen processors 23 connected to the data circulation bus 21, the arbitration circuit determines

  first of all if the processor n l contains an information module

  training to transmit, then it controls processor n 2, n 3, etc.) As soon as the arbitration circuit has determined that a

  processor contains an information module ready for transmission

  sion, it sends an authorization signal to this processor

  access. For example, consider that this is the process

  sor n 5. As soon as this processor n 5 has issued the information module

  training on the data circulation bus, the arbitration circuit 32 modifies the sequential order of the corresponding processor n 5, to give it the number having the lowest priority. Then, as each access authorization signal is generated, the order of priority of the corresponding information module processor is fixed

  similarly to the lowest value. This confi-

  guration guarantees access to each data card once

  every 16 cycles. However, it should be noted that this technology

  arbitration is just one example and we can

  could use any suitable bus arbitration technique in combination with the sequence processor

data 20 of the invention.

  The data sequence processor 20 of the fi

  gure i allows complex calculations to be made

  asynchronous, the various constituent functions being ac-

  compline separately in individual treatment units

  empty. Each of these units performs its own function.

  specialized as soon as the necessary input data have been assembled by the associated input information module processor. The "data flow diagram" in Figure 4 schematically represents the type

  of complex computation that can be accomplished by the processor

  data quence 20. Each of the nodes or functions fl to

  f5 appearing in figure 4 represents a process par-

  particular, mathematical, arithmetic, logical or other, ac-

  compli by a respective one of the processing units 25. As an example, the node f2 can correspond to the function (fa) in FIG. 3 and this function can be performed

  by the processing unit 25a. The function f can be displayed

  assigned to the processing unit 25b which is also part of the data sequence card 23a. The functions fl 'f4 and f5 can be assigned to three respective processing units 25c, 25d, 25e in the same information module processor 23a. According to a variant, some of the functions f1 ', f4 and f5' or all of these functions can be assigned to processing units 25 in separate information module processors 23.

  An important feature of the information system

  vention consists in that the allocation of the various functions

  tions to particular processing units is completely arbitrary. You can assign the performance of any function to any processing unit. In

  in addition, the system of the invention also accepts the situation

  tion in which there are more functions to be performed

* only processing units. This can be achieved by doing

  able to operate one or more of the processing units 25 in a time-sharing manner, to perform two functions separately or

  more. As an example, the processing unit can be given

  25a in the information module processor 23 a configuration allowing it to perform the two functions f2 and f3 'The processing unit 25a can for example be

  consisting of a microprocessor having two programs

  separately registered, one to perform function f2 and the other to perform function f3 'In addition, the periods during which such

  processing unit 25a performs the function f2 or the function

  tion f3 are not necessarily fixed. On the contrary, they can be determined dynamically according to

  the availability of the input data necessary for the accom-

  folding of the particular function.

  As an example, function f2 requires data values from arcs A, B and C, corresponding to

  information modules with the labels "1", "2" and "3".

  On the other hand, function f4 requires input data pro-

  coming from arcs G and H, characterized by modules having

  the labels "7" and "8". The information module processor

  input 30 associated partner will accumulate all these information modules

  mation, that is to say the modules having the labels 1, 2, 3, 7 and 8. The input information module processor can then indicate to the processing unit 25a when the appropriate data have been assembled for one or other of the functions f2 and f4 'The processing unit 25a

  can then accomplish the necessary, depending on the availability

data reliability.

  For example, the PME 30 can first receive an information module having the label "1", then an information module having the label "7", and then a

  information module with the label "8". At this point, all

  the data for the performance of function f4 are available, but all the data necessary for

  the f2 function is not yet available. Therefore

  quent, the PME 30 can indicate this situation to the processing unit 25a. This processor will then place itself

  under the conditions corresponding to the performance of the function-

  tion f4 'it will immediately perform this function and it

  will provide an output value which will be put (by the output information module processor 31) into a module format

  information label g "9", associated with the arc

of output I (9) of function f4.

  Then the PME 30 can receive information modules.

  formation having the labels "2" and "3". At this point, all

  your data (with labels 1, 2 and 3) necessary for the performance of function f2 will have been assembled by the PME 30. In the presence of this situation, the unit of

  treatment 25a will itself establish its operating conditions

  function and will perform the function f2 'Of course, the functions f2 and f4 could be assigned to separate processing units (and this is

  generally the case), as for example the units respec-

  tives 25a and 25c. In this case, as soon as the PME 30 has received information modules having the labels "1", "2" and "3", the processing unit 25a performs the function f2 'De

  similarly, as soon as the PME 30 has received information modules

  formation having the labels' 7 "and" 8 ", the processing unit

  25c performs the function f2. For example, if information modules are received in the following order (by label value): "2" ', "7", "1", "3" and "8", the processing unit 25a will start to perform function f2 upon receipt of the information module "3", since all the necessary input data are then available. Unit 25c will begin to perform the function

  f4 when the information module "8" is received.

  In addition, as will be described further below, several values for one or more arcs may be received before a complete necessary data set is assembled to accomplish a particular function. The

  function will be completed upon receipt of the

  seems complete, using the input data for each

  that bow, based on the "first receipt". By way of example, it will be assumed that information modules are received in the following order (by label value): "2", "1", "1",

  "3". At this point, all input data will be available.

  to perform the function f2 'but two values of

  data will have been received for arc A (1). The processing unit

  25a will perform the function f 2 'but it will use the first value received from the two data values of

  arc A (1) (that is, it will use the data value

  born from that of the two information modules with the label "1" which was received first). The value of

  data from the information module received later-

  ment with the label "1" will be kept for use by the processing unit 25a as soon as second data values for the arcs B (2) and C (3) have also been received. The same input information module processor (Figure 1) accepts information modules required for all functions performed by all processing units 25a, 25b, 25c, etc., in the execution section

  function 24 of the same card has data sequence. Ain-

  if, if the processing units 25a, 25b and 25c have configurations intended to perform the functions f2 ′ f5 and f4 respectively, the PME 30 in the processor

  information module 23 will assemble all information modules

  training required for all these functions.

  It will be noted in this example that an input arc I (a) of the function f5 corresponds to an output of another node

  (f4) which is processed on the same data sequence card.

  In this case, the information modules having the label "9" will nevertheless be received by the PME 30 from the data circulation bus 21, at the time of their transmission on this bus by the PMS 31 in the same card to donation sequence "

born.

  Figure 5 shows an example configuration

  of the input information module processor 30. The pro-

  input information module terminator 30 includes a

  requested label memory 33 which stores the identification numbers corresponding to the information module labels required by the processing units in the function execution section 24 of the same processor.

  information module. In the example in which the functions

  f2 'f4 and f5 are accomplished by processing units

  on this information module processor

  or on this data sequence card, information modules

  training relating to arcs A, B, C, F, G, H and I are exi-

  aged. The corresponding label identification numbers "1" t "2", "3", "116", "7" n, "8" t and "9" are therefore recorded

in memory 33.

  When each information module appears on the data circulation bus, a label comparator 34 determines whether this information module is required by the data sequence card in question, by comparing the area

  information module label with all identi-

  required labels which are contained in the manual

moire 33.

  If the information module is required, the comparison

  tor 34 indicates to an appropriate memory input control circuit, 35, to accept the information module and to load the data coming from the information module

  in an appropriate position in a memory 36.

  The memory 36 can advantageously, but not obli-

  temporarily, be of the first-in-first-out type. The memory 36 is also advantageously organized so as to comprise separate data recording zones 36a, 36b, 36c ..., each of them working in a first in-first out mode, for respectively recording only data associated with information modules with the corresponding identification label. By way of example, the recording area 36a can be assigned to recording data area values from information modules associated with the arc A having the label

  identification "1". Similarly, the registration areas

  respective records 36b to 36g can record only-

  data from the data areas of information modules having respective label values "2",

"3", "6", "7", "8" and "9".

  The order in which various information modules appear on the data circulation bus 21 is

  relatively arbitrary or random. M a i s, the process

  input information module 30 assembles data

  incoming entries in the correct order for application to

  the function execution section 24.

  By way of example, the first information module on the bus 21 can have a label "5". If the card

  data sequence does not need this information module

  tion, the label comparator 34 recognizes the fact that the label "5" is not one of those recorded in

  memory 33. This label is therefore not accepted.

  The following information module on bus 21 can

  have a label "3". In this case, the comparator of

  quette 34 acts on the input control circuit 35 in a

  Let’s accept the information module. The donation value

  corresponding data (symbolically identified by the term "1C11) is entered in the first memory position in the recording area 36c. The next information module which is accepted may have a label" 2 ", and its data B1 are entered in the first position in the memory recording area 36b. It may happen that the following information module which is accepted by the SME

  also has a label "3". Its C2 data is in-

  produced in the immediately next position in recording area 36c. Note how two data values from arc C are

  stored in first-in-first-out memory 36.

  However, the function execution section 24 has not yet completed the initial calculation of the function f 2, since it must still receive a first data value from the arc A.

  If this information is received as a result, the

  label processor 34 enters the correct data value

  respondent A1 from the information module with the label "1", in the first memory position in

  recording area 36a. The content of the pre-

  mier in-out 36 then presents the aspect which is

  shown in Figure 5. At this time, a com-

  memory output command 37 recognizes that a complete data set (including here the values A1, B1 and C1) necessary to perform the function f2 'is present in memory 36. A control circuit 37 then takes

  these values in memory 36 (in a first-in-order

  very first out), and it applies them to the exe section

  cution of function 24 for the execution of function f2 'When this function has been executed, the section

  of execution of function 24 emits a data value

  born (i.e. an output value D1 of the function f2 calculated from the input data values A1, B and C1) which is associated with the arc D. This data value D1 is applied to an information module training circuit

  training 38 (figure 5) in the information module processor

  output formation 31. The circuit 38 recognizes the fact that the output data D1 has been produced by the processing unit performing the function f2 ', which means that these data represent data on the arc D, and must therefore be incorporated into an information module having a

  label value "4". Consequently, the training circuit

  information module 38 forms an information module

  tion having the label value "4" and the data value D1. This newly formed information module is placed in a queue of output information modules 39 which can be constituted by a first-in-first-out memory. The introduction of the information module into the queue 39 also acts on an interrogation and access authorization circuit 40, so that it transmits an interrogation signal to the arbitration circuit

  32, by bus 21. This signal indicates that this card has

  particular data quency contains an information module

  tion ready to be issued on the bus. When the arbi- circuit

  trage 32 returns an authorization signal for access to this data sequence card, the control circuit 40 transmits on the bus 21 the information module which has been recorded

  first in queue 39.

  There are certain practical limits with regard to the number of information module processors 23 which can be associated with a single data circulation bus 21 in the configuration of FIG. 1. It is clearly seen that when processors are added of module

  23 additional information to a single bus

  tion of data, we have a greater capacity for

  simultaneous processing, and a greater number of information modules

  mation are therefore produced during a time interval

  given. However, the transfer rate of information modules

  training on the data traffic bus fixes a

  more than the number of information modules that can

  can be transmitted between data sequence cards

  during a given time interval.

  To overcome this limitation, the configuration

  in figure 6 shows how we can significantly increase

  the capacity of the system using two subsystems

  or more data traffic bus themes

  but in mutual relation, each having the configuration

  general tion of FIG. 1. The use of processors of inter-bus transfer information module 41A, 41B, of an appropriate type, makes it possible to ensure the transmission of information modules between the circulation bus subsystems

separate data.

  The system 20 'shown by way of example in FIG. 6 combines the data sequence processor 20 of FIG. 1, having data sequence cards (CSD) 23a, 23b ... 23i, with a sequence processor data 20A similar, comprising a data circulation bus 21A and information module processors or associated CSDs 23j, 23k ... 23m. An arbitration circuit 32A having a configuration similar to that of the arbitration circuit 32 is associated with the data circulation bus 21A. The inter-bus transfer information module processor cards, 41A and 41B, having a similar configuration, interconnect the data flow buses 21 and 21A. These cards, considered together, facilitate the transfer of information modules between buses 21 and 21A. However, all the information modules present on each bus are not transferred to the other. On the contrary, only the information modules which are required for the

  functions performed in information module processors

  mation 23j-23m associated with bus 21A are transmitted from bus 21 to bus 21A. Conversely, only the information modules required for the functions performed in the processors 23a-23i connected to the bus 21 are transferred from the bus 21A to the bus 21. It is thus possible to obtain an optimal throughput of information modules on each of the bus data flow 21 and 21A, without requiring the two data flow buses to process all of the necessary information modules in the complete system. We can express this differently by saying that each of the data circulation buses 21 and 21A only processes the information modules necessary for

  the performance of functions in the mo-

  dule of information which are associated with the respective bus.

  The 41A inter-bus transfer card itself

  seems to an information module processor. Indeed, from the point of view of the data circulation bus 21, the inter-bus transfer card 41A looks exactly like any of the other information module processors

connected to this bus.

  In particular, the inter-bus transfer card 41A comprises an input information module processor A which includes a required label memory 33A. This memory 33A however stores a list of labels for all the information modules required by the sections

  of execution of function 24 of all CSD 23d-23m asso-

  ciées to the data circulation bus 21A. A comparator

  34A compares the labels of each module

  the information present on bus 21 with those required

  by bus 21A (which are stored in memory 33A).

  If comparator 34A indicates that the information module

  present on bus 21 is required by bus 21A, the comparison

  tor validates a door 42A which transmits the information module

  tion of the bus 21 to a transmitter circuit 43A. The transmitter circuit 43A in turn transmits the information module to a receiver circuit 44B in the inter-bus transfer card

41B associated.

  This 41B card, which has exactly the same configuration-

  ration that the inter-bus transfer card 41A, includes a

  output information module processor 31B. It includes

  te a queue of output information modules 39B which introduces the information module transferred from the receiver 44B into a queue or a memory first

  in-out. The PMS 31B also has a circuit

  control circuit for interrogation and access authorization B. Under the effect of the presence of an information module in the queue 39B, this circuit produces an interrogation signal on the circulation bus 21A. The

  arbitration circuit 32A processes the inter-transfer card

  bus 41B in the same way that it

  processes any of the information module processors

  tion 23j-23m which are associated with the data circulation bus

  born 21A. Thus, upon receipt of an interrogation prove-

  from the 41B inter-bus transfer card, it applies a

  access authorization signal, in order of priority ap-

  property. Under the effect of this access authorization signal, the PMS 31B transfers the information module from the queue 39B to the data circulation bus 21A. The transfer of an information module from bus 21 to the bus

21A is thus accomplished.

  Conversely, the transfer of an information module

  tion from bus 21A to bus 21 is carried out via

  diary of the input information module processor 30B of the inter-bus transfer card 41B, of a transmitter 43B

  associated, with a receiver 44A in the transfer card

  ter-bus 41A, and an output information module processor 31A. Of course, the required label memory 33B in the PME 30B contains a list of the labels of all the information modules required for the execution of

all functions on bus 21.

  In the system 20 ′ in FIG. 6, each of the subsystems 20 and 20A operates in a completely independent manner from the other. In fact, each subsystem 20, 20A ignores the presence of the other subsystem. The interface, constituted by the associated inter-bus transfer cards 41A or

  41B, considers the individual system 20 or 20A exactly as

  me any other information module processor

  connected to the associated data circulation bus 21 or 21A.

  The invention is not limited to configurations with

  one or two data circulation buses in Figures 1 and 6.

  On the contrary, we can interconnect a set of subsystems

  temes similar to that of Figure 1, each having their own data traffic bus, to form a system

  global. In addition, the interconnections between the bus lines

  data culation are entirely arbitrary or may

be fully selected.

  Figure 7 schematically shows an example

  of such a system with several data circulation buses.

  In this system, each of the separate data sequence processor subsystems 20B to 20F has its own respective data flow bus 21B to 21F. Each of the subsystems has a configuration similar to that of the

  Figure 1, with its associated information module processors

  ciés 23B to 23F and its own associated arbitration circuit 32B-

32F.

  In the configuration of Figure 7, the sub-

  system 20B is interconnected to subsystems 20C, 20D and

  F by respective pairs of inter-

  bus 41B-41C, 41B-41D and 41B-41F. Similarly, the sub-

  20C system is interconnected to the 20D and 20F subsystems by the 41C-41D and 41C-41F inter-bus transfer cards. Of

  similarly, the 20E and 20F subsystems are interconnected

  connected by the 40E-40F inter-bus transfer cards.

  As in the system described in relation to FIG. 6, each pair of inter-bus transfer cards 41

  transfers, between the interconnected buses, only the modules

  the information required by the receiving bus.

  As shown in Figure 8, the input circuits

  input and output of processor sequence data

  data 20 can be realized by one or more

  input / output (I / O) 45 associated with the traffic bus

  data card 21. Such an I / O card 45 has a configuration

  ration which is largely similar to that of an information module processor 23. However, instead of comprising

  a processing unit 25 contained in the exe section

  cution of function 24, it includes an input receiver

  46 and / or an appropriate output transmitter 47.

  The input information module processor

  30i in the I / O board 45 stores a list of labels-

  tes for all the information modules having data which must be sent by the output transmitter 47 to a certain external device such as a modem, a printer, a cathode ray tube display or the like. So every time

  that an information module is present on bus 21 and con-

  holds data to be sent by the transmitter 47, this information module is accepted by the PME 30i and is directed

  to the output device via the transmitter

tor 47.

  Conversely, data that must be intro

  data on the data circulation bus 21 are applied

  quées via the receiver 46 to a processor of module of information output 31i in which they

  are assembled into an information module, with the label

  appropriate quette. The new information module is in

  continuation introduced into the queue and it is applied to the bus 21 in a manner identical to that implemented by the output information module processor 31, described in

relationship to Figure 5.

  The definition of the configuration and the initiali-

  sation of the overall data sequence processor system can be carried out by an auxiliary computer or a central processing unit (CPU) 50 which is interconnected,

  as shown in figure 9, the de-module processors

  training or data sequence cards, associated with the data sequence processor 20. In particular, each

  information module processor cards 23a, 23b ...

  23i associated with the data traffic bus 21 (as a

  crit in relation to figure 1), can also be in-

  terconnected to the CPU 50 by a separate bus 51. One purpose of this configuration is to allow selection and

  to initialize under computer control 50 the functions

  specific actions that are accomplished by each unit

  25 in each of the data sequence cards

born 23.

  For example, the processing unit 25a can

  be. itself constituted by a microprocessor and a mete

* program memory in which the

  appropriate programs to ensure that the mid-

  croprocessor performs one or more specific functions

  fied fl 'f2' etc. These functions and their corresponding programs need not be set in advance in the processing unit 25a. On the contrary, they can be introduced into the processing unit 25a from the computer 50 at the time when the data sequence processor 20 is initialized to accomplish a certain task.

  Calculation. Such a configuration provides great support.

  crashes in applications in which the processor

  The invention's data sequence is used.

  If a particular user, working on a

  certain project, wishes that the processing unit 25a ac-

  completes the function (fa) of FIG. 3, before accomplishing the actual calculation, it commands the computer 50 to introduce into the processing unit 25a the appropriate computer program to perform the function (fa). We can so

  corresponding use the UCT 50 to load other functions

  appropriate treatment in other treatment units 25 in

  the function execution sections 24 of some of the pro-

  information module terminators or data sequence cards 23 which are associated with the data traffic bus

21, or in all of these processors.

  This function loading operation does not have to be performed before the processor

  with data sequence 20 actually performs its calculation. Ain-

  if, the CPU 50 can really control the processing which is carried out by the processor system 20 and introduce

  dynamically changes in the system at ins-

  appropriate ones. For this purpose, a control card of the

  operation and fault correction 52 in-

  connects the data circulation bus 21 and the bus 51.

  This card 52 can have a configuration (by the fact

  that it includes an information module processor

  very similar to PME 30 in Figure 5) allowing it to detect the presence of information modules having certain

  particular labels, and to control the data values

  associated with them. The computer 50 can then be

  programmed, for example, to react to certain conditions

  data in information modules having certai-

  our labels. Under the effect of the detection of these conditions

  the computer can then change or modify the functions

  one or more of the milking units

  in the information module processor 23. We realize

  thus reads dynamic control of the system.

  A different but related function of the computer-

  50, which is used for both initialization and

  for the dynamic change of function of the processing units

  consists of loading into the label memories

  requirements 33 (Figure 5) of each module processor

  input training 30 the list of labels of in-

  training which are required by the associated function execution section 24. So in the example described above,

  when the UCT 50 establishes the configuration of the processing unit

  25a so that it performs the function f2 of the fi-

  gure 4, the CPU 50 simultaneously introduces into the memory for required labels 33 the labels "1", "2" and "3" which are associated with the information modules containing the data required to perform this function. In the same way,

  the UCT 50 loads in the module training circuit

  training 38 of PMS 31 (figure 5) the necessary information

  so that output data from the processing unit

  25a and associated with arc D are assembled in a mo-

  information package with label "4" required.

  Similarly, if the data sequence processing system comprises more than one data circulation bus, the CPU 50 also initializes the inter-bus transfer cards 41A, 41B (FIG. 6), so as to introduce into the

  label memories required 33A and 33B label values-

  of information modules which must be respectively

  transmitted from bus 21 to bus 21A and vice versa.

  The CPU 50 (FIG. 9) has yet another function which consists in checking the existence of operating faults in the processor 20 while it is operating. For example, if a particular processing unit, namely the processing unit 25a in the information module processor 23, presents a fault during a processing operation, the CPU can recognize this situation. It can for example recognize this situation by the absence of any information module.

  formation having the label "4" (which must be issued by this

  processing unit), for a certain period of time.

  In this case, the UCT 50 could modify the system in a way

  dynamic so that another processing unit 25, function-

  correctly, performs the function that was assigned

  previously to the faulty processing unit 25a.

  Another function of i'UCT 50 is to optimize the configuration of the data sequence processor 20 for a

  particular calculation. For example, if we know that a calculation par-

  particular requires a much greater number of re-

  relating to a certain particular function fx, in relation to the number of calculations for other necessary operations, the CPU 50 can define the configuration of the system so that several processing units 25 have the configuration

  appropriate to perform the function f.

  x A special characteristic of the processor

  data sequence 20 considered is that it does not use

  reads no global memory which all functions are trying to access simultaneously. The speed of calculation in such a global memory system is often limited by the

  concurrent access requests to the common database.

  We therefore eliminate this difficulty as well as the bottleneck

associated Von Neumann settlement.

  It goes without saying that many modifications can

  can be made to the device described and shown, without

depart from the scope of the invention.

Claims (12)

  1. Characterized data sequence processor (20)   in that it comprises: a bus (21) on which one can transfer   put information modules (22), each information module   mation comprising a label part (22t) and a data part (22d), and a set of module processors   information (23a-23c) connected to this bus (21), each pro-   information module ceaser comprising: at least one   processing unit (25a-25c) intended to perform a function   tion specified on certain input data identified by   one or more specific labels, a mo-   input information module (30) for controlling the label part (22t) of each information module on the bus and   to record the data part of each information module   tion whose label part corresponds to one of the labels   specific quets identifying input data for a processing unit (25a-25c) in the processor considered (23a-23c), this processing unit fulfilling its specified function on the data which are thus recorded, as soon as   this data is assembled, and an information module processor   output formation (31) for assembling an information module   training (22) consisting of the data produced as output information from the processing unit, and by a label (22t) identifying this output information, this   information module then being transmitted to the bus (21).   2. Data sequence processor according to the res   dication 1, characterized in that it further comprises: arbitration means (32), in communication via   of the bus (21) with each of the information module processors   tion (23a-23c) connected to the bus, so as to interrogate all the information module processors connected to the bus (21), in order to determine the processors which have information modules awaiting transmission to the bus, and so as to allow these information module processors (23a-23c) to transmit these information modules to the   bus, based on a rotating priority.   3. Set of processors with data sequence (20, 20A), each of the processors being in accordance with claim 1, characterized in that the bus (21, 21A) of each of these processors is interconnected with the bus of another   at least of these processors by an internal transfer processor   ter-bus (41A, 41B) of information module, comprising means (30A) intended to identify, from the label part of information modules present on a first of the interconnected buses, those of these information modules which are required by processing units of a second of the interconnected buses (21, 21A), and to transmit only these information modules required from the first to the second interconnected buses.   4. Data sequence processor according to re-   vendication 1, characterized in that it further comprises: a computer (50) interconnected with the information module processors (23a-23c) so as to condition the units   processing (25a-25c) of these processor modules   training for performing specific associated functions, and correspondingly conditioning input information module processors (30) so   that they record data coming only from   information sheets with label parts (22t) which   represent input arcs of these specific functions.   5. Processor with data sequence (20), charac-   characterized in that it comprises: a bus (21) on which information modules (22) circulate, each information module having an identification label area (22t) and an operand data area (22d), and several data sequence cards (23a-23c) associated with the bus (21),   each of them having at least one processing unit (25a-   c) capable of performing a function which can be specified   on operand data obtained from information modules   training (22) provided by the bus (21) and having certain values identifying input arcs of this function, as well as producing, for application on the bus (21), information modules containing data which result   of the performance of the said function and which have   their label identifying an output arc of this function.   6. Data sequence processor according to the res   dication 5, which can be configured to perform the mutually related functions of a "flow diagram   data ", characterized in that it further comprises a computer   nator (50), interconnected to the different data sequence cards (23a-23c), so as to specify the units of   processing (25a-25c) of these cards the particular functions   res which they must perform, these particular functions being those linked to each other by the "data flow diagram", and so as to specify to these cards the identities of the input and output arcs corresponding to each of the specified functions.   7. Data sequence processor according to the res   dication 5, characterized in that each of the drying cards   data sequence (23a-23c) includes an input information module processor (30) which includes: a required label memory (33) for storing values   identifying the input arcs for all the ac-   complied by processing units (25a-25c) located   on the card has the data sequence considered, and a compa-   label erator (34) intended to compare the label values of each information module (22) present on the bus (21) with the label values recorded in the required label memory (33), and to be accepted from the bus (21), for use in the data sequence card (23a-23c), only information modules for which the comparison has indicated corresponding label values.   8. Data sequence processor as claimed   dication 7, characterized in that it further comprises: a memory (36) intended to temporarily record at least the operand parts (22d) of the information modules which have been accepted, and means for generating a set of operands (37), intended to supply the parts of operand temporarily recorded to each processing unit (25a25c), in the form of a complete set of data   for all the entry arcs required for accom-   folding of the specified function of this processing unit   which has been saved in memory (36).   9. Data sequence processor according to re-   vendication 5, characterized in that each of the cards to   data sequence (23a-23c) includes a mo-   output information module (31) comprising: an information module training circuit (38) for forming   information modules each having a label value-   you identifying an output arc of a function performed by a processing unit (25a-25c) on the sequence card   data (23a-23c), and having in the operator data area   of the data value produced by this processing unit   ment for the corresponding output arc.   10. Data sequence processor according to re-   vendication 9, characterized in that the output information module processor (31) further comprises: a queue   waiting for exit (39) intended for temporary recording-   information modules formed by the training circuit   output information module (38), and interrogation and access authorization means (40) intended to indicate that an information module contained in the queue (39) is ready to be applied to the bus (21), and to direct this information module from the queue (39)   to the bus (21) depending on an authorization signal tion of access.   11. Functional information module processor   based on data, associated with a bus (21) on which information modules (22) are transmitted, each information module comprising a label area   (22t) containing an arc identifier and a data area   born of an operand (22d), characterized in that it comprises: at least one processing unit (25a-25c) intended to perform a function which can be specified, on data   of operand for one or more entry arcs of this function   tion, and to produce one or more output values on   respective output arcs of this function, a process   input information module (30) intended to identify   proud from their label areas (22t) the only ones   information modules (22) transmitted on the bus which correspond   lay at input arcs associated with the unit (s)   of the aforementioned processing (25a-25c), and to save tempo-   the operand data from these identified information modules, and the processing unit (25a-25c)   performing the specified function as soon as a set includes   input operand data set for all input arcs   entry of this function have been recorded by the processor   input information module (30).   12. Information module processor according to claim 11, characterized in that it further comprises an output information module processor (31) intended   to assemble and apply new methods to the bus (21)   information modules, each containing a label area value (22t) identifying an output arc of a   function performed by said milking unit (s)   ment (25a-25c), and an operand data area value (22d) corresponding to an output value that the unit of   processing has occurred for this output arc.