FR2570851B1 - ARITHMETIC AND LOGIC UNIT WITH ACCELERATED RETENTION PROPAGATION - Google Patents

ARITHMETIC AND LOGIC UNIT WITH ACCELERATED RETENTION PROPAGATION

Info

Publication number
FR2570851B1
FR2570851B1 FR8414564A FR8414564A FR2570851B1 FR 2570851 B1 FR2570851 B1 FR 2570851B1 FR 8414564 A FR8414564 A FR 8414564A FR 8414564 A FR8414564 A FR 8414564A FR 2570851 B1 FR2570851 B1 FR 2570851B1
Authority
FR
France
Prior art keywords
arithmetic
propagation
logic unit
accelerated retention
accelerated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8414564A
Other languages
French (fr)
Other versions
FR2570851A1 (en
Inventor
Andre Picco
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EFCIS
Original Assignee
EFCIS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EFCIS filed Critical EFCIS
Priority to FR8414564A priority Critical patent/FR2570851B1/en
Publication of FR2570851A1 publication Critical patent/FR2570851A1/en
Application granted granted Critical
Publication of FR2570851B1 publication Critical patent/FR2570851B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3872—Precharge of output to prevent leakage
FR8414564A 1984-09-21 1984-09-21 ARITHMETIC AND LOGIC UNIT WITH ACCELERATED RETENTION PROPAGATION Expired FR2570851B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8414564A FR2570851B1 (en) 1984-09-21 1984-09-21 ARITHMETIC AND LOGIC UNIT WITH ACCELERATED RETENTION PROPAGATION

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8414564A FR2570851B1 (en) 1984-09-21 1984-09-21 ARITHMETIC AND LOGIC UNIT WITH ACCELERATED RETENTION PROPAGATION

Publications (2)

Publication Number Publication Date
FR2570851A1 FR2570851A1 (en) 1986-03-28
FR2570851B1 true FR2570851B1 (en) 1989-06-23

Family

ID=9307964

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8414564A Expired FR2570851B1 (en) 1984-09-21 1984-09-21 ARITHMETIC AND LOGIC UNIT WITH ACCELERATED RETENTION PROPAGATION

Country Status (1)

Country Link
FR (1) FR2570851B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5487025A (en) * 1993-11-15 1996-01-23 Intergraph Corporation Carry chain adder using regenerative push-pull differential logic

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892036A (en) * 1981-11-27 1983-06-01 Toshiba Corp Addition circuit

Also Published As

Publication number Publication date
FR2570851A1 (en) 1986-03-28

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Legal Events

Date Code Title Description
ST Notification of lapse