FR2569071A1 - DIGITAL SIGNAL PROCESSING DEVICE - Google Patents

Abstract

IN THIS DIGITAL SIGNAL PROCESSING DEVICE, INCLUDING N OPERATORS 2 WHO COMMUNICATE WITH EACH OTHER AND WHICH EACH INCLUDES A COMPUTING UNIT 3 AND A MEMORY 4 CONTAINING THE SAMPLES OF THE SIGNAL TO BE PROCESSED, A SEQUENCER 1 WHICH COMMANDS THE OPERATORS IDENTIALLY WRITING AND READING ADDRESSING 1,5, 6 OF THE N MEMORIES, THE WRITING AND READING ADDRESSING OF N MEMORIES ARE SUCH AS SEVERAL PROCESSINGS CAN BE CARRIED OUT IN PARALLEL BY SIMULTANEOUSLY CARRYING OUT THE SAME ELEMENTARY TRANSFORMATIONS ON LOTS SAMPLES CORRESPONDING TO EQUIDISTANT TAPS ALONG THE ACQUIRED SIGNAL RANGE. APPLICATION TO DIGITAL SIGNAL PROCESSING.

Description

DIGITAL SIGNAL PROCESSING DEVICE

  The present invention relates to a digital processing device

of signal.

  Generally this type of treatment differs from the treatment of

  type by the volume of transactions processed (the latter being higher than

  at least the order of magnitude of the computing power of a general-purpose processor) and the stationarity of the algorithms (the transformations carried out over time on the signal to be processed being

  consisting of immutable sequences of elementary

  possibly come from invariant or slowly varying coefficients in

  time compared to recurrence of calculation).

  There are two types of devices that make it possible to

  a multiprocessor structure (or MIMD, for Multiple Instruction Stream, Multiple Data Stream), the other having a multi-operator structure (or SIMD, for Simple Instruction

Stream, Multiple Data Stream).

  In the case of the multiprocessor structure, the device consists of several processors in relation to each other and each having its sequencer, its computing unit, its memories, etc. With such a structure, the realization of a signal processing application typically goes through the decomposition of the processing chain into a sequel

  more or less linear elementary transformations and by the specialization

  processors based on these elementary transformations. To perform this chain of processing, the processors, often organized into

  "pipeline", each provide one or more of these

  successively; they are therefore differentiated, at least by their program.

  Another possibility of implementing a signal processing application with the multiprocessor structure is to execute the string

  processing in each processor but on a single part-

  samples of the input signal, the processors taking turns in the

  time to ensure that input samples are taken into account continuously.

  Processors no longer need to be differentiated by their

  me. However, since an output sample is usually calculated from c a sequence of input samples, the sequences of input samples stored in the memories of the different processors must then overlap to a large extent, hence the misuse of the input sample. overall memory volume. For example, according to this last mode of use, N processors simultaneously calculate N output samples from sequences of no input samples stored in the memories of these operators and having starting samples remote from a sampling period. . The same input sample must then be stored in as many memories as there are samples in a sequence (if n <N), hence the misuse of the e

available memory.

  In the case of the multi-operator structure, the device does not have

  that a sequencer driving identically several operators (an opera-

  the so-called elementary processor, consisting of a memory and a computing unit), and a means of exchange between operators, of the "ring bus" type, is generally provided. The device performs the same

  program on different input sample streams. With a structure

  multioperator, one can not solve a

  signal that in so far as it is parallelisable, ie to decompose

  sand in identical tasks carried out on different streams of input signals: there are as many waves as there are operators. This is for example the case of a filtering treatment to be performed on each of the output signals of the sensors of an antenna: the signal of each sensor is applied to an operator specific to this sensor. The disadvantage of this structure is that it applies validly only for a limited type of processing of

signal.

  The device according to the invention is similar in structure to the multi-operator devices, thereby benefiting from the structural advantage of a single sequencer which identically controls several operators, but by its operation, in the second aforementioned mode of use of the devices.

  multiprocessors, avoiding however, thanks to a particular organization

  of the input samples in the different memories, and, correlated

  specifically addressing these memories, the misuse

  the amount of memory inherent in this mode of use.

  In the digital signal processing device according to the invention,

  comprising means for acquiring samples of the signal to be processed, N operators each comprising a calculation unit and a memory containing the samples of the signal to be processed, a sequencer which identically controls the N operators, addressing means in writing and read addressing means of the N memories, the N calculation units communicating with each other by a ring bus, each of the N memories comprises an area reserved for the storage of input samples organized in B segments (numbered from 0 to B-1) each containing S samples, N segments of the same number b (b taking the values 0 to B-1) of the N memories being delimited by identical addresses and forming a band of number b, the address d a sample in the memory zone thus obtained for the N operators being then defined by the coordinates (b, n, s) denotes the operator number (n taking values 0 to Nl), b the band number e ts the relative address of this sample in the segment determined by the pair (b, n) (s taking the values of 0 to 5-1), and the write addressing means of the N memories include means to ensure a sequential storage of the samples of the signal to be processed, as and when they arrive, in the memory zone thus obtained, according to priorities

  increasing writing, by address within a segment, operation number

rator, and band number.

  Moreover, the read addressing means of the N memories comprise means for providing, at each memory access controlled by the sequencer, two addresses at each of the N memories: Ap = AINF + Sp and Ac = A SUP + Sp and each operator of number n has means for choosing Ap if n is greater than or equal to np, or A if n is less than np o AINF and ASup are the origin addresses of two adjacent bands of numbers bp and 3b + I and o (bp , nps p) designate the coordinates of the pilot sample relative to the memory access considered, or sample acquired for the most time among the N samples read in the N operators during

the memory access considered.

  The invention will be better understood in the course of the description which follows and

  the examination of the figures that support it. These are given as

  indicative and not limiting of the features of the invention. They represent

  tent: - Figure 1, a diagram showing the organization of the input samples in the different memories of the device according to the invention. FIG. 2a, a rising diagram Plorganization of the input samples in the various memories of the device according to the invention, for an example of digital processing of which the successive steps are shown

in Figure 2b.

  FIG. 3, a block diagram of the device according to the invention, according to

a first embodiment.

  - Figure 4, a block diagram of the device according to the invention, according to

a second embodiment.

  - Figure 5, a diagram illustrating the method of reading samples

memorized input.

  - Figures 6a and 6b, flowcharts showing the different steps

  the read address calculation of the stored input samples.

  FIG. 7, a diagram showing the means of exchange with the medium

  exterior of the device according to the invention.

  The same elements represented in different figures

identical references.

  By way of example, FIG. 1 corresponds to the case where the number of operators N is equal to 4. Each operator is assigned a number n (from -0 to N-1). In the memory of each operator is delimited a set of B adjacent zones, each zone being called segment, each having a

  same capacity equal to S words, and intended for storing samples.

  In each of the N memories, this set of B segments starts at the same origin address, and is called a set of N segments

  delimited by identical addresses and belonging to operators

tincts.

  The location of a sample in the N memories is then defined by the coordinates (b, n, s) the operator number in which this sample is stored, (n being able to take the values 0 to Nl), b the band number (b can take the values 0 to fiB-1) and s is the address. relative of the sample in the segment determined by the couple

  (b, n), (s can take the values 0 to S-1).

  In the memories thus organized, the input samples are stored sequentially, ie only one of the variables (b, n, s) is incremented each time, the variable s varying most rapidly and the variable b varying the least quickly. In other words, the coordinates (b (t), n (t), s (t)) of the sample X (i) written at a time t are deduced from the coordinates (b (tl), n (tl ), s (tl)) of the sample X (i-1) written at time tI as follows: s (t) = s (tl) + I (modulo S) if s (t) = 0 , n (t) = n (tl) + 1 (modulo N) if s (t) i O, n (t) = (tl) sin (t) = 0 and s (t) = O, b (t) = b (tl) + I (modulo B) if n (t) t0ets (t) t0, b (t) = b (t-1) We now explain with an example in relation with figure 1,

  the mode of writing the input samples into the memories thus organi-

  Sees. The number of input samples X necessary to obtain an output sample Y is denoted by f + 1 and the following are considered by way of example:

  following values of N, B, Setf: N = 4, B = 2, S = 3 and f = 3.

  We are interested in the acquisition of NS (equal to 12) input samples X (i) (where i is an index that increments at each sampling period), for example X (15) to X (26). ), this acquisition being spread over a period of time called recurrence (rated R), equal to NS Tech (ie 12 Tech), where Tech is the time interval between two successive input samples - (or period of time) sampling), the input samples X (3) to X (14) having been

  acquired during the previous recurrence R-1, and, inter alia, the samples

  Input lasses X (0) to X (2) during recurrence R-2.

  During the same recurrence, the acquisition (denoted A) of input samples and the processing (denoted T) of already acquired input samples are done simultaneously. Thus, during the recurrence R, NS (ie 12) input samples X (15) to X (26) are acquired and, during a computation time equal to Tc, with Tc <NS Tech, NS + f ( either 15) input samples X (0) to X (14) are processed. The treatment implies that additional samples are taken into account because it is exerted on sequences of f + 1

input samples.

  The memory area containing the input samples required for processing during a recurrence therefore occupies NS + f words. Since the same input sample is used several times during the calculation time Tc to obtain several output samples, this area must be prohibited when writing any new input sample during the time calculation Tc within this recurrence. Acquired samples must therefore be stored, in the case of two bands, in the area

  available of capacity 2NS- (NS + f) samples, ie NS-f sample

  lons. Thus two bands are sufficient provided that we have Tc <(NS-f) Tech.

c

  In the example considered, Tc is equal to 6 Tech and (NS-f) Tech to 9 Tech.

  FIG. 1 shows an example of the location of 2 NS + f input samples X (0) to X (26) (denoted by their indices 0 to 26) in the various memories during the recurrence R, d on the one hand with regard to the processing T of NS + f input samples X (0) to X (14), on the other hand with regard to the acquisition A of NS input samples X (15) to X (26) during this same recurrence. The samples X (0), X (1) and X (2) acquired during the recurrence R-2 have, for example, coordinates (1,2,1) (1,2,2) and (1,3,0 ), and the samples X (3) to X (14) acquired during the recurrence R-1 (3, 1, 1) to (3, 0, 0). These samples are shown with one-way sloped ruts (except for samples X (12) to X (14) which have been shown with vertical ruptures as they correspond to the additional samples mentioned previously) for -indicate that they are samples that are preserved from one recurrence to the next. The samples X (0) to X (14) are those processed during computation time T during recurrence R. X (15) to X (26) acquired during recurrence R are then assigned to as they arrived, the coordinates (0,3,1) to (1,3,0). Samples X (21) to X (26) are represented with hatches inclined in a second direction to indicate that they are samples

  acquired during the recurrence considered outside the calculation time Tc.

  Samples X (15) to X (20) are represented with a grid to indicate that their acquisition is done simultaneously with the treatment (Tc)

  samples acquired during previous recurrences.

  According to the same principle, the location of the input samples X (12) to X (38) in the various memories during the recurrence R + 1 is also represented in FIG. 1. Now, with reference to FIGS. and 2b, the reading mode of the memories thus organized, illustrating it with the help of an example

  processing corresponding to a cross-type digital filtering.

  The transformation performing the cross-type filtering is defined by the relation: f Y (n) = C. X (nj) j = O where Y (n) denotes the output sample obtained from f + 1 samples. input X (nj) by applying respectively coefficients C. To illustrate this example, we choose a number of coefficients f + 1 equal to 4, a number of operators N equal to 4, a number of bands B equal to 3, and one

  number of samples per segment S equal to 4.

  It is assumed that the device has previously acquired input samples X (i), for example X (0) to X (44), whose distribution in the different memories is shown in FIG. 2a, and the calculation of the

Y (i) output samples.

  The elementary transformations performed for this purpose are

  2b o, on the abscissa, each column represents a different operator while the ordinate is the machine time graduated in

  calculation cycles, and the left column indicates the basic transformation

  carried out simultaneously by the four operators for the samples

  Input samples X (i) identified by their single number iL A pilot sample with coordinates (bp, np, sp), relative to a given calculation cycle, is the oldest sample X (i) (c '). that is, having the lowest index i) of all those simultaneously processed by the different

  operators during this calculation cycle.

  At the beginning of the computation (instant t0) the starting samples X (10), X (14), X (18) and X (22), each separated by 5 = 4 sampling periods, are read simultaneously, respectively by the operators of numbers 2, 3, 0 and 1,

  pilot sample being then X {10) of coordinates (0, 2, 2). Samples

  lons X (10) and X (14), both located in the band of number 0, are read with the same address Ap, called pilot address by reference to the pilot sample X {O10) which is located in this band, then that the samples X (18) and X (22), both located in the band of number 1, are read with the same address Ac called the co-pilot address. In the calculation units, these four samples are multiplied simultaneously by

  the appropriate coefficient C3 sent by the sequencer.

  The same is done during the following calculation cycle with samples X (11), X (15), X (19) and X (23) which are multiplied by C2,

  the pilot sample being X (11).

  At this stage of the processing, the calculations started in each of the operators can not finish there, for want to have all the necessary samples in this operator. The calculation then continues in the adjacent operator who has the following samples of operands required. For this purpose, the intermediate results obtained in each calculation unit are transferred to the computation unit adjoining: there are four exchanges made at the same time. Thus C3 X (10) + C2 X (11) is transferred from the computation unit

  from the operator 2 to the calculator unit of the operator 3.

  In general, the operator n in which a calculation can not be completed transmits its partial result to the adjacent operator n + 1 (modulo N) which is terminated, this is the case for f <S, or is transmitted to the adjacent operator n +2 (modulo N) (for the case for f> S) until exhaustion of f + 1 samples. With each transit in the adjacent operator, the read address

  returns by the value which designates the sample of beginning of segment.

  Calculations continue until the same moment of the four correlation results Y (13), Y (17), Y (21) and Y (25) which, as shown in FIG. 2a, are arranged in an area memory of the operator who completes the

  calculation, which has the advantage of minimizing the calculation time.

  Calculations are continued by taking as samples the samples X (1), X (1 5), X (1 9) and X (23), the pilot sample being X (11). Following the same process as before, we get in the

  same calculation time Tc four results Y (14), Y (iS), Y (22) and Y (26).

  At the moment t1, NS, ie 16, output samples Y (13) to Y (28) have been calculated, since the starting samples (X (10), X (11), X (12), etc.) are distant from a sampling period. More generally, if the starting samples were separated by k samples, we would obtain NS samples of output Y. k To calculate the following sample Y (29), we need X (26) to X ( 29), ie 3 previously used samples (f = 3) plus one new sample. The oldest sample is X (26) and we find the same configuration of addresses as at time to with a shift of a band. At that moment, there are 16 samples that will no longer be used and

  which can be replaced by new samples.

  This example of digital signal processing has made it possible to better show the principle of invention. In signal processing, the

  Stationarity of the algorithms is generating temporal parallelism.

  According to the invention, this temporal parallelism is exploited in the following manner: provided that a sufficient slice of operand samples has previously been acquired, several treatments can then be carried out

  in parallel while performing the same transformations

  sample lots corresponding to equidistant

along the acquired slice.

  The advantage of this parallelism requires an arrangement of the multi-operator structure that is now explained in relation to FIG. 3 representing the structure of the device according to a first embodiment of FIG.

realization of the invention.

  As in the case of the multi-operator structure, this device comprises a single sequencer 1 which identically controls N operators at 2N1 each comprising a computing unit (30 to 3N 1) and a memory (40 to 4N -1).

  According to the invention, the memory area reserved for the storage of

  is organized into bands and segments as we have seen

  According to this first embodiment, the sequencer 1 provides at each instant, defined by the memory cycle, two read addresses: a pilot address Ap for access to the band bp containing the pilot sample relative to this memory cycle, and a co-converter address Ac for access to the adjacent band bp + 1 (modulo B), as well as the operator number np in

  which is stored the pilot sample.

  Each operator 2n comprises a comparator (50 to 5N_1) which receives the pilot operator number n and its own number n, and which provides a control signal p to an address selector 6n making it possible to send to the memory 4n of the operator to which he belongs an address Ad equal, either to the pilot address A (if n> np) or to the co-pilot address A (if n <np). In addition to the pilot and co-pilot addresses Ap and Ac and the number np, the sequencer 1 generates the operating code for managing the calculation units 3n and the access to the memories 4n, as well as the coefficients necessary for the processing. The N calculation units 30 to 3N-1 communicate with each other via a

bus ring 7.

  The calculation units 3n comprise the appropriate circuits making it possible to implement the processing of the samples, whether real or complex. These circuits consist of specialized sets of elementary operators and tests arranged so as to perform the algorithms necessary for the processing (FFT algorithm, image processing by

example).

  The computation of the A and Ac addresses is not carried out sequentially because otherwise its duration would be incompatible with the necessary flow at the level of

memories of the operators.

  This calculation is divided into two phases performed by two separate circuits: a relative calculation phase, performed by a circuit called master sequencer, and an absolute calculation phase, performed by a circuit called slave sequencer. The absolute calculation phase for a given memory access is done in parallel with the calculation phase in relative

the next memory access.

  The relative calculation consists of calculating the coordinates (bp, np, sp) of the pilot sample. The calculation is done by incrementation knowing the

  number INC of samples separating two successive pilot samples.

  If (bp (t), np (t), s (t) denote the coordinates of the relative pilot sample

  p to a computation cycle occurring at a time t, (bp (t + 1), np (t + 1), sp (t I + 1) the coordinates of the pilot sample relative to the cycle of

  following calculation occurring at time t + 1, and INC (t + I) the number of samples

  Separating these two pilot samples, we have: I1 s (t + Il) = sp (t) + INC (t + 1) (modulo S) sp (t) + INC (t + 1) - s (t + l) c PP

C1 = S

  np (t + 1) = np (t) + C1 (modulo N) np (t) + C1 - np (t + 1)

G2 = N

  bp (t + 1) = bp (t) + C2 (modulo B) In the embodiment, tests are carried out according to the flowchart of FIG. 6a. In the example of treatment described above, INC was

constant and equal to 1.

  The absolute calculation consists in calculating the pilot and co-pilot addresses Ap (t) and Ac (t) at a time t, knowing the origin addresses AINF (t) and ASUp (t) of two adjacent bands in which the zone treated at this time. moment t is on horseback, using the following relations: A p (t) = AINF (t) + sp (t) Ac (t) = ASup (t) + sp (t) o AINF (t) and Asup, ( t) depend on bp (t) and sp (t) designates the relative address 0 of the pilot sample at this instant t in the segment to which it belongs in the treated area, and o ASUp (t) is equal to A1NF ( t) + S (S being the number

samples per segment).

  Each time the pilot sample enters a new band, the slave sequencer adds S to the values of AINF and ASup. The slave sequencer also receives the value of the ORG origin address of the input sample storage area for the registration of AiNF and ASup when

  The pilot sample goes from band B-1 to band 0.

  The concrete significance of the variables A c Ap, AINF, Asup, sp and ORG appears in FIG. 5 which represents, for example, the area

  storage of samples for entry into the records of four opera-

  the treated area, straddling two successive bands, is

spotted with hatching.

  On the flowchart in Figure 6b, the operations have been shown

  performed by the slave sequencer.

  The master sequencer and the slave sequencer are for example made by means of a calculation unit associated with a random access memory

  downloadable document containing the instructions for carrying out the opera-

  mentioned in this chart.

  In the variant embodiment shown in FIG. 4, the calculation of the addresses Ac and Ap is done in a decentralized manner in each of the operators, whereas in the case of FIG.

  centrally in the slave sequencer.

  This variant has compared to that described above to reduce the number of connections between the sequencer and the operators. The sequencer 1 is simplified and provides the coordinates np and s p of the pilot sample, as well as an address calculation command CA. On the other hand, each operator comprises, besides the comparator 5n ', an address calculation circuit 8n providing the reading address (Ap or Ac) to the memory 4n. For each calculation cycle, the circuits 8n execute, with the n sequencer 1, the operations which are indicated on the flowcharts of the

Figures 6a and 6b.

  Each circuit 8 is for example realized by means of a unit of

calculation.

  The structure of the device according to the invention is also different from the structure of the multi-operator devices by the means allowing the exchanges with the outside, ie the acquisition of the input samples and the return of the output samples. In particular, the acquisition makes it possible to obtain the organization of the samples in memory, in segments and

in strips.

  The means of exchange with the outside, represented in FIG. 7, comprise, according to a first embodiment, a channel 10, referred to as the "word-to-word" input-output channel, connecting the operators 20 to 2N, and making it possible to fill the memory area reserved for the storage of the input samples continuously over time and to empty the memory area reserved for the storage of output samples. The mechanisms controlling the addressing and the reading and writing commands are of the known ADM type (Direct Memory Access) so as to make the running of the programs and the exchanges with the external medium independent. The links between the channel 10 and the memories 40 to 4N-1 are via bidirectional amplifiers 110 to 110. The channel 10 is shared by two ADM controllers 12 and 13, one input and one output, which respectively provide write frenzy

  input samples and the read address of the output samples.

  These addresses are obtained in successive increments to take into account the sequential layout of the input and output samples which is carried out as previously seen according to three levels:

bands, segments and operators.

  In "word-by-word" mode, the external memory-environment exchanges are

  selective: only? designated operator performs a memory cycle.

  However, to naturally treat a treatment application

  signal implementing identical tasks, memory exchanges

  external environment can also be done in "parallel" mode. The acquisition and the restitution are then made simultaneously in all the operators, each having a particular "parallel input-output" channel (140 to 14N 1), the links between channels and operators also being made through

  bidirectional amplifiers (150 to 15Nl).

  These two embodiments have been represented in FIG. 7, the selection between the two being effected by means of mode selectors 160 to 16N-1 selecting one of the two bidirectional amplifier sets 110 to 11N-1 and 150 to 15N. -1 - The device is not modified by the type of samples or treatment performed. In particular, the type of treatment may be

image processing.-

Claims (8)

  1. Digital signal processing device comprising means   acquisition of samples of the signal to be processed, N operators (2n) which   each of them comprises a computing unit (3n) and a memory (4n) containing nn in particular the samples of the signal to be processed, a sequencer (1) which identically controls the N operators, write addressing means and addressing means in reading of the N memories, the N calculation units communicating with each other via a ring bus (7), characterized in that each of the N memories (3n) comprises a zone reserved for the storage of input samples organized in B segments (numbered from 0 to BI) each containing S samples, N segments of the same number b (b taking the values 0 to B1) of the N memories being delimited by identical addresses and forming a band of number b, the address of a sample in the memory area and obtained for the N operators being then defined by the coordinates (b, n, s) we denote the operator number (n taking the values 0 to Nl), b the band number and s the relative address of this sample in the segment determined by the pair (b, n) (s taking the values from 0 to S-1), and in that the write addressing means of the N memories comprise means (10, 11n, 12, 13) for ensuring a sequential storage of the samples of the signal to be processed, as and when they arrive, in the memory zone thus obtained, according to priorities   increasing writing, by address within a segment, operation number - rator, and band number.   2. Device according to claim 1, characterized in that the means for reading addressing N memories comprise means (1 or 1, 8n) for providing, at each memory access controlled by the sequencer (1), two read addresses to each of the N memories: Ap = AiNF + Sp and Ac = A SUP + Sp and in that each operator (2n) of number n has means (Sn, 6n or 5n, 8n) for choosing Ap if nest greater than or equal to np, where Ac sin is less than np, where AINF and ASUP designate the origin addresses of two adjacent bands of numbers bp and bp + 1 and o (bp, np, sp) denote the   coordinates of the pilot sample for the memory access   dere or sample acquired for the most time among the N samples   read in N operators during memory access considered.   3. Device according to claim 2, characterized in that the means for providing the addresses A and Ac comprise means for calculating at each memory access, the coordinates of the pilot sample relating to   Next memory access, by incrementing the coordinates of the sample   pilate relative to the current memory access of a number equal to the number of samples separating two successive samples useful to the same treatment.   4. Device according to one of claims 2 and 3, characterized in that   the means for providing the addresses A and Ac comprise means (1 or 1.8n) for calculating at each memory access the origin addresses AINF (t + 1) and Asup (t + 1) of two adjacent bands of numbers bp (t + l) and bp + 1 (t + 1) SUP pp whose lower band, of number bp (t + 1), contains the pilot sample relating to the following memory connection, by incrementation of the source address AINF (t) relative to the current memory access of a number equal to the number S of samples per segment, if the pilot sample relating to the next memory access changes band with respect to the current memory access without however returning to the number 0 band, by conservation the origin address AINF (t) if it does not change band with respect to the current memory access, or by assigning the origin address (ORG) of the area reserved for storing input samples in the N memories El changes band when returning to the band of number 0, address origin ASUP (t + 1) of the upper band of number b + 1 (t + 1) being obtained in all cases in P   adding the number S of samples per segment to the origin address AiNF (t + 1). -   5. Device according to one of claims 2, 3 and 4, characterized in that   the means for providing the pilot and co-pilot addresses comprise a master sequencer which calculates at each memory access the pilot addresses and a co-pilot for this memory access, and a slave sequencer which calculates at each memory access the coordinates of the pilot sample relatively to access memory followingo   6. Device according to one of claims 2 to 5, characterized in that   the means for providing the addresses A and A are located in the p c I6 sequencer (1).   7. Device according to one of claims 2 to 5, characterized in that   the means for providing the Ap and Ac addresses are located for part {(8n) in each of the N operators.   8. Device according to one of claims 1 to 7, characterized in that   the means for acquiring samples of the signal to be processed comprise N input-output channels (14 n) connected to the N memories (4 n), which enables   memory-external environment exchanges in "parallel" mode.