FR2564677A1 - System for broadcasting television signals with time-division multiplexing of analog components and device for transferring from this system to a system with half the throughput - Google Patents

Abstract

System for broadcasting television signals with time-division multiplexing of analog components, of MAC/packet type, having an instantaneous digital throughput of 20.25 Mb/s during bursts of about 10 mu s and a mean digital throughput of 162 packets of 751 bits per 10 ms frame, in which the digital services to be transmitted simultaneously with the image are, in order to be capable of being transmitted on a network using a second MAC-packet type system having an instantaneous digital throughput of 10.125 Mb/s and a mean digital throughput of 82 or 83 packets per 40 ms frame, grouped into a maximum of 82 packets, or 83 depending on the throughput of this second system, occupying with each frame, in the first system, well-defined spaces from the 162 packet spaces of this first system. Application: reception of television signals transmitted by satellite.

Description

TELEVISIOIN MULTIPLEXING TELEVISION SIGNAL BROADCASTING SYSTEM
OF ANALOGUE COMPONENTS AND DEVICE FOR THE PASSAGE OF THIS SYSTEM
TWO TIMES LOWER FLOW SYSTEM.

 The present invention relates to a system for broadcasting time-division multiplex television signals of analog components, of the MAC / packet type, as well as a device making it possible to switch from this system to a system with a bit rate that is substantially twice as low.

 We know that the EBU has proposed a television standard suitable for satellite broadcasting, the essential characteristics of which are defined in the proposed standard SPB 284. The proposed standard is of the MAC / packet type which uses time multiplexing between the luminance components. , chrominance and digital data, the latter carrying sound and data information.

 Digital data comprising information on the synchronization and the structure of the multiplex are transmitted during line 625 at an instantaneous digital speed of 20.25 Mb / s. At the start of each of lines 1 to 624, a burst of approximately 10 is transmitted duration, at the same instantaneous rate, which comprises 7 synchronization bits and 195 bits representing the useful data and the information on the packet multiplexing of the data. The 624 bursts thus make it possible to obtain a data stream grouped in packets of 751 bits transmitted at the average rate of 162 packets per 40 ms frame, 18 bits remaining unused at the end of the 162nd packet.

 As in satellite broadcasting, frequency modulation is used for video signals which occupies a bandwidth of the order of 27 MHz, there is no difficulty in having digital phase modulation in such a band 20 Mb / s instantaneous speed. This is the system called C-MAC packets.

 In the case of terrestrial broadcasting in UHF and VHF, of distribution on cable in VHF and UHF or on optical fiber and in magnetic or optical recording, the signal to noise ratios are much higher than in the case of satellite broadcasting, which allows the use of modulations that consume a lot less overall bandwidth: amplitude modulation with residual sideband or frequency modulation with reduced band. It is thus possible to hold video information in a channel of 7 or 8 MHz of bandwidth but it practically no longer becomes possible to transmit in the same band a digital bit rate of 20 Mb / s. This is why it has been proposed to MAC / packet systems differing from the previous ones only by reducing the instantaneous digital speed by a factor of 2: 10.125 Mb / s instead of 20.25.

 One of these systems, called D2-MAC packets, uses binary modulation for data, which allows this signal to pass in a band not exceeding 5 MHz, compatible with the bandwidths of terrestrial broadcasting networks, cable distribution networks and HF and FI stages of television receivers, thus allowing the decoding of the signal on the SCART socket of televisions.

In this D2-MAC / packet system, it is possible, for the same instantaneous digital bit rate of 10,125 Mb / s, to obtain an average bit rate of 82 or 83 packets of 751 bits per 40 ms frame. The information contained in line 625 is very close to that provided in the C-MAC packets
Frame synchronization data (FSD): 102 or 103 bits
Unified date and time (UDT) 5 5bits
Static data frame (SDF): 94 bits
Time multiplex (TDMCTL) control information: 3 x 94 = 282 bits
Either a total of: 483 or 484 bits
The main difference compared to C-MAC packets concerns the last information which includes only three repetitions of the repeated data frame (RDF) instead of 5.

 In the case of 82 useful packets per frame, the bursts of lines 1 to 624 include a 7-bit synchronization word, identical to that used in C-MAC packets, and 99 useful bits, which leaves 194 bits unused in the bursts lines 623 and 624.

In the case of 83 useful packets per frame, the bursts of lines 1 to 624 include a synchronization word reduced to 6 bits and 100 useful bits, which leaves 67 bits unused in the burst of line 624.

 In C-MAC packets, it is possible to devote per digital frame a maximum of 160 packets on average called coding blocks (BC) to the transmission of sound data (8 compressed channels with simple protection or 4 linear channels and enhanced protection against errors, for example) and, on average, 2 packets to transport the information making it possible to interpret the coding (blocks of interpretation BI) and the-information making it possible to identify the service (system of identification of services SI) on packets with the address zero.

 In D2-MAC packets, the number of BC packets can be reduced by a factor of 2, by reducing the number of sound channels or by using more economical codings (4 compressed channels with simple protection, 2 compressed channels and 4 7 kHz bandwidth comment channels or even 8 comment channels). On the other hand, the number of BI and SI packets cannot be reduced by a factor of 2 without increasing the access times to the service. This is the reason why the average bit rate proposed for the D2-MAC packet system is either 82 packets per digital frame, which would give the same access conditions as in the case of C-MAC packets, or 83 packets. per digital frame, which would allow more flexibility and more easily include access control information in the case of conditional access programs (pay television).

 The problem of converting packet C-MAC to packet D2-MAC may arise in the case of transmissions from a satellite of a country which has chosen the first standard when it is desired to transmit the lz plus part. important information in a broadcasting or distribution network of the same country or of a neighboring country, a network in which the spacing of the channels does not allow the transmission of the instantaneous digital bit rate of 20 Mb / s.

When the programs are not encrypted, it is possible to solve this problem by completely demultiplexing the original multiplex. The operations that it is necessary to perform are then successively - recovery of the clock - at 20.25 Mb / s and synchronization
-frame contained in line 625; - bit removal at 20.25 Mb / s; - deinterlacing of bits within each packet; - correction of the packet header by Golay code; - read addresses of all packets and select packets
with address 0 (SI packets) and packets with the
addresses of the services kept within the limit of a maximum total
82 or 83 packets per digital frame; - re-striping of bits within each selected packet ;; - separation of data in bursts of 99 or 100 bits placed at the start
lines 1 to 823 or 624; - reshuffling of the bits at the rate of 10.125 Mb / s; - insertion of a 7 or 6 bit synchronization word at the start of
each salvo synthesized taking as synchronization reference
frame received on line 625.

 All of these operations are very complex and must be carried out for each satellite channel of C-MAC packet type that one wishes to transmit on the network, which can lead to a prohibitive cost for small networks of collective antennas.

 In the case where the transmissions are encrypted, it is planned, in C-MAC packets, to link the clock-of one of the generators of pseudo-random digital sequences to the total frequency of the packets, such as the selection of a certain number of packets causes this clock information to be lost at the time of retransmission in D2-MAC packets, it would be necessary, in this case, to decrypt at the head of the network.

The object of the invention is to remedy these shortcomings by imposing constraints on the C-MAC packet system, for example, at the time of the original broadcast in a first system S1 at 20.25 Mb / s.
to the radio broadcaster in order to facilitate subsequent conversion to
To this end, the invention relates to a system for broadcasting television signals å a time multiplexing of analog components, of the MAC packet type, having an instantaneous digital bit rate of 20.25 ib.'s during bursts of Approximately 10 microsecands and an average digital bit rate of 162 packets of 751 bits per 40 ms frame, characterized in that the digital services which it is desired to transmit at the same time as the image are, in order to be able to be transmitted over a network of distribution or broadcasting using a second MAC packet type system with an instantaneous digital speed of 10.125 Mb / s and an average digital speed of 82 or 83 packets per 40 ms frame, grouped into a maximum of 82 packets, or 83 depending on the throughput of this second system, these packets occupying in each frame, in the first system, well-defined places among the 162 packet places of this first system. The broadcaster therefore chooses in advance a maximum of 82 or 83 packets per frame, depending on the speed of the second system 52 at 10.125 Mb / s, D2-MAC -packets for example, and places them in well-defined places among the 162 package spaces offered by the first S1 system. As these places are well defined, it is no longer necessary to read the address of the packets nor consequently to perform the interleaving of the bits of each packet.

The operations to be carried out at the head of the network are then as follows - recovery of the clock at 20.25 Mb / s and synchronization
frame contained in line 625; - bit removal at 20.25 Mb / s; - choice of 82 or 83 packages according to their predetermined places in
the frame; - separation of data in bursts of 99 or 100 bits placed at the start
lines 1 to 623 or 624; - reshuffling of the bits at the rate of 10.125 Mb / s; - insertion of a 7 or 6 bit synchronization word at the start of
each synthesized salvo taking synchronization as a reference
frame received on line 625.

 Furthermore, in the case of encrypted programs, as the places of the packets are known, it is possible to find the original clock for controlling the generator of pseudo-random digital sequences used for encryption.

 It is possible to choose the locations of the 82 or 83 packets so as to simplify as much as possible the operations carried out at the head of the network or the decryption operation.

 A first choice amounts to deciding that the 82 or 83 packets retransmitted in the second system S2 will occupy, in the first system S1, the places of the first 82 or 83 packets. This operation is the simplest as far as the decryption operation is concerned since the control clock of the generator of pseudo-random digital sequences has exactly the frequency of the packets retained in the system 52. This solution however has two drawbacks: size of the memories needed at the head end to carry out the conversion, and the size of the memories needed in the final receiver.

 Indeed, at the head of the network the first 82 or 83 packets, representing 61,582 or 62,333 bits, are received during the digital bursts of the first 316 or 320 lines while they are retransmitted at a rate of approximately half in the bursts of 623 or 624 lines.

The size of the buffer memory B required in both cases (this memory B will be called the second memory) is between 30 and 32 kbits. It is therefore necessary to provide, at the head of the network, a memory of this size per channel S1 received. In the final receiver, whether it operates according to the S1 or S2 system, it is also necessary to be able to spread over 40mus the information of the two sound channels received in approximately 20 ms. This requires a buffer memory of approximately 10 kbits per received sound channel, or a total memory of approximately 20 kbits if it is estimated that the receivers will only be equipped for the reception of two sound channels.

 In order to reduce the capacity of the memories required at the head of the network and in the receivers, it is possible to choose more judiciously the place of 82 or 83 packets by endeavoring, for the majority of the time, to interleave the transmitted packets and the packets not transmitted in the S2 system. It must also be taken into account that the last packet transmitted in the system 52 begins in the burst of line 615 and ends in the burst of line 623, in the case of 82 packets per frame, or begins in the burst of line 616 and ends in the burst of line 624, in the case of 83 packets per frame.

 As the transmission according to S2 of the last packet must begin after the start of the reception of the information corresponding to this packet according to the system 51 'the last packet transmitted according to S2 corresponds at most to the 160th packet transmitted according to S1 in the bursts of the lines 613 to 617.

The most judicious choice, having regard to the memory capacities, amounts to choosing the places of all the even packets except the last (the 162nd) and the places of the 1st and 3rd packets, in the case of 82 packets per frame, or the places 1st, 3rd and 5th packets, in the case of 83 packets per frame. Buffer size
B required at the head of the network is then close to 1.5 kbit in the case of 82 packets per frame and 2.2-kbits in the case of 83 packets per frame, per channel received in the S1 system. In the final receiver, the size of the strictly necessary memories would then be less than 1 kbit per sound channel.

 In the case of encrypted signals, it is not necessary to decrypt at the head of the network since it will suffice, on reception, when it will be known that the signals originate from an S1 system, to count a clock pulse of the pseudo-random digital sequence generator between each of the first 4 or 6 packets, then two clock pulses between the following packets.

The processing of the 483 or 484 bits of data contained in line 625 as well as that of the 99 or 100 bits of data of the burst of line 1 requires special attention because the retransmission of the bits at the rate of 10,125 Mb / s begins as soon as reception of these bits at a rate of 20.25 Mb / s. To process this data, it is therefore necessary to have a buffer memory
A of 256 bits random access (which will be called first memory) whose writing or reading cycle time does not exceed 25 ns.

If we consider that such a memory is too storytelling, we can for example realize A by multiplexing several memories
2 memories of 128 bits, of write or read cycle time of 50 ns or 4 memories of 64 bits, of write or read cycle time.

Another solution for producing the first memory A may consist in using a memory organized in words
64-bit 4-bit memory, 100 ns write or write cycle time or 8-bit 32-word memory, 200ns lock cycle or 200ns read cycle time by preceding this memory with a serial / parallel conversion circuit - and by making it follow a parallel / series conversion circuit, these circuits being produced for example using two shift registers of 4 or 8 stages. However due to the delays introduced by these conversion circuits and the operations in memory , it is then necessary to delay the video signals transmitted according to the system 52
The first fast memory A of 256 bits, which is essential for processing the data contained in line 625 and in the burst of line 1, can be used in buffer memory for the data transmitted in the bursts of lines 2 to 624 to reduce the speed of the second memory B of 1.5 - 2.2 or 32 kbits necessary for the processing of these data. It suffices for this to accumulate the 195 bits of: each burst in memory A during the 10 ijs during which they are received, then transfer this data to a memory B of 1.5 - 2.2 or 32 kbits during the 54 ps which separate two bursts. The speed of memory B is then determined by its reading cycle time which must not exceed 100 ns.

 In the case of an S2 system with 83 packets and an alternate transmission of the useful packets received according to the system S1, the capacity of the memory B can be reduced to 2048 bits if the data transfer is interrupted from A to B each time memory B is completely filled, which occurs during lines 22 to 24, 30 to 32, etc. The bits not transmitted at 13 then remain accumulated in memory A without it being necessary to increase the 256-bit capacity of the latter. This same method can also be applied in the case of an S2 system with 82 packets and could make it possible to reduce the capacity of memory B to 1280 bits. However, it has fewer advantages because it is then necessary to increase the capacity of memory A with at least 276 bits.

A variant of the device according to the invention, which makes it possible both to decrease the capacity of the memory B at the same time as its speed, consists in transferring, during the 54 ps which separate two bursts, both the data from memory A to memory B and the 99 or 100 bits of memory B, which must be transmitted to the next burst, from memory B to memory A. Under these conditions, during the duration of each burst, the data processing is carried out by writing the data or by reading it only in fast memory A, as is already done for line 625 and for the burst of line 1. The entry or exit of the data in Memory
B then takes place only during the periods of 54 ps which separate two bursts and therefore requires only a read or write cycle time of 180 ns.

 The capacity of the required memory B can thus be reduced to 1280 or to 2048 bits in the case where the packets are interleaved during the majority of the transmission time according to the system S1. In order not to exceed this capacity, care must be taken to stop the transfer of data from A to 8 each time B is completely filled. In the case of a 52 to 83 packet system, using a memory B of 2048 bits and a memory A of 256 bits, it is possible to have the data inputs in B and their outputs succeed in two separate time intervals. in the case of an S2 system with 82 packets the same process requires that the capacity of memory A exceeds 256 bits or that that of memory B exceeds 1280 bits. It is however possible to limit the capacities of the memories with these values if one interleaves several periods of writing and reading in the memory B, during the periods of 54 ps which separate two bursts.

 In all cases, it is possible to reduce the speed of memory B, as previously proposed in the case of memory A, either by multiplexing several memories, or by using a memory organized in words of 4 or 8 bits, by making this memory precede this by a series / parallel conversion circuit and by making it follow by a parallel / series conversion circuit.

 In the case where the capacity of memory B does not exceed 2.2 kbits, it may be more economical to replace all of memories A and B with a single fast memory B of capacity 1.5 or 2.2 kbits, having a write or read cycle time of 25 ns. As before, the required cycle time can be increased by multiplexing 2 to 6 memories of reduced individual capacity in the same report, or by using one or more memories organized in 4 or 8 bit words, the memory then being preceded by a series / parallel conversion circuit and followed by a parallel / series conversion circuit. In the latter case, due to the delays introduced by the conversion circuits and the memory operations, it would be necessary to delay the video signals transmitted according to the S2 system.

 It may be worth making a final remark.

In the D2-MAC packet system, the total synchronization and data burst occupies 106 bits and lasts approximately 10.5 us, which is longer than the total burst of the C-MAC packet system which lasts only approximately 10 ps. This was made possible, without reducing the duration of the video signals, by recovering two transition periods of, 2 us located before and after each burst in the C-MAC packet system.

 If one does not want to delay the video signals while passing from the system S1 to the system S2 one notes that, in the bursts of lines 1 to 624, the synchronization signals of S2 begin before the reception of those of S1 but that the beginning transmission of the 99 or 100 data bits of 52 begins immediately after the reception of the 195 data bits of S1 begins. If the 6 or 7 synchronization bits of lines 1 to 624 are synthesized from the frame synchronization extracted from line 625, it is therefore not necessary to delay the video signals.

 In the case of line 625, the 483 or 484 bits previously detailed begin with 6 or 7 line synchronization bits.

If you want to treat these bits in the same way as the other bits on line 625, it is necessary to delay the video information by about 0.6 us, which can be done using a line analog delay in passive circuit or charge transfer type for example. To avoid this drawback and to have video signals transmitted according to the S2 system synchronous with those received according to the S1 system, it suffices to synthesize the first 6 or 7 line synchronization bits of the line 625 from the frame synchronization extracted from the same line, as is done for lines 1 to 624, and to process in memory A only the following 477 bits.

Claims (15)

CLAIMS: 1. System for broadcasting time-division multiplex television signals of analog components, of the MAC / packet type, having an instantaneous digital bit rate of 20.25 Mb / s during bursts of approximately 10 us and an average digital bit rate of 162 packets of 751 bits per 10 ms frame, characterized in that the digital services which it is desired to transmit at the same time as 1 t image are, in order to be able to be transmitted over a distribution or broadcasting network using a second system of the MAC- type packets with an instantaneous digital bit rate of 10,125 Mb / s and an average digital bit rate of 82 or 83 packets per 40 ms frame, grouped into a maximum of 82 packets, or 83 depending on the bit rate of this second system, these packets occupying each frame, in the first system, well-defined places among the 162 packet places of this first system. 2. System according to claim 1, characterized in that the 82 or 83 packets retransmitted in the second system occupy, in the first system, the places of the first 82 or 83 packets. 3. System according to claim 1, characterized in that the 82 or 83 packets retransmitted in the second system occupy, in the first system, the places of all the even packets except the 162nd and last, and the places of the 1st and 3rd packets or the places of the 1st, 3rd and 5th packets depending on whether the capacity of the second system is 82 or 83 packets per frame. 4. Interface device between a first system according to one of claims i to 3 and the second system, characterized in that, for the transition from the first to the second system at the head of the redistribution or redistribution networks, it comprises a 256 bit maximum capacity random access memory that allows immediate conversion of the data rate from 20.25 to 10.125 Mb / s for the data contained in line 625 and the data contained in the burst of line 1. 5. Device according to claim 4, characterized in that this rapid memory is produced by means of two, three or four slower multiplexed memories, of reduced individual capacity in a ratio 2, 3 or 4. 6. Device according to claim 4, in which the fast memory is organized in 4-bit or 8-bit words and in that this memory is preceded by a series / parallel conversion circuit and followed by a parallel conversion circuit /series. 7. Device according to one of claims 4 to 6, characterized in that the fast memory is also used to store the useful data received in the bursts of lines n01 to 617 then to transfer them, during the intervals between two bursts , to a second, slower memory read back at the read rate, 125 Mb / s- for the duration of the bursts transmitted according to the second system. 8. Device according to one of claims 4 to 6, characterized in that the fast memory is used to store the useful data received in the bursts of lines 1 to 617 and in that, during the intervals between two bursts, both the data received by the first memory are transferred to a second memory and the data which must be transmitted during the next burst are transferred from this second memory to the first memory, to be read in this latter memory during their transmission pen before the duration of the bursts. 9. Device according to one of claims 7 and 8 when these depend on claim.2, characterized in that the capacity of the second memory is at most 32 kbits. 10. Device according to one of claims 7 and 8 when these depend on claim 3, characterized in that the capacity of the second memory is close to 1.5 kbit, when the digital bit rate of the second system is 82 packets per frame, or close to 2.2 kbits, when the digital bit rate of the second system is 83 packets per frame. 11. device according to one of claims 7 and 8 when these depend on claim 3, characterized in that the capacity of the second memory is 1280 bits when the digital bit rate of the second system is 82 packets per frame, or 2048 bits when the digital bit rate of the second system is 83 packets per frame, and in that the transfer of data from the first to the second memory is interrupted each time the second memory is completely filled. 12. Device according to claim 4 when it depends on claim 3, characterized in that one uses a single rapid random access memory, called the third, of capacity 1.5 or 2.2 kbits, depending on whether the digital rate of the second system is 82 or 83 packets per frame, this third memory making it possible to process all the data received in line 625 and in the bursts of lines 1 to 624. 13. Device according to one of claims 7 to 12, characterized in that the second or third memory is produced by means of 2 to 6 multiplexed memories, of individual capacity reduced in a ratio 2 to 6. 14. Device according to one of claims 7 to 12, characterized in that the second or third memory is organized in words of 4 or 8 bits and is preceded by a series / parallel conversion circuit and followed by a circuit parallel / serial conversion. 15. Device according to one of claims 4 to 14, characterized in that the first 6 or 7 bits of each line which represent the line synchronization signal are not stored but are synthesized from the frame synchronization extracted from line 625, this processing of the first bits applying to line 625 as to the others.