FR2555380B1 - LOGIC LEVEL TRANSLATION CIRCUIT - Google Patents

LOGIC LEVEL TRANSLATION CIRCUIT

Info

Publication number
FR2555380B1
FR2555380B1 FR8318399A FR8318399A FR2555380B1 FR 2555380 B1 FR2555380 B1 FR 2555380B1 FR 8318399 A FR8318399 A FR 8318399A FR 8318399 A FR8318399 A FR 8318399A FR 2555380 B1 FR2555380 B1 FR 2555380B1
Authority
FR
France
Prior art keywords
logic level
translation circuit
level translation
circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8318399A
Other languages
French (fr)
Other versions
FR2555380A1 (en
Inventor
Didier Dedeurwaerder
Sylvain Kritter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EFCIS
Original Assignee
EFCIS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EFCIS filed Critical EFCIS
Priority to FR8318399A priority Critical patent/FR2555380B1/en
Publication of FR2555380A1 publication Critical patent/FR2555380A1/en
Application granted granted Critical
Publication of FR2555380B1 publication Critical patent/FR2555380B1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
FR8318399A 1983-11-18 1983-11-18 LOGIC LEVEL TRANSLATION CIRCUIT Expired FR2555380B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8318399A FR2555380B1 (en) 1983-11-18 1983-11-18 LOGIC LEVEL TRANSLATION CIRCUIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8318399A FR2555380B1 (en) 1983-11-18 1983-11-18 LOGIC LEVEL TRANSLATION CIRCUIT

Publications (2)

Publication Number Publication Date
FR2555380A1 FR2555380A1 (en) 1985-05-24
FR2555380B1 true FR2555380B1 (en) 1986-02-21

Family

ID=9294285

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8318399A Expired FR2555380B1 (en) 1983-11-18 1983-11-18 LOGIC LEVEL TRANSLATION CIRCUIT

Country Status (1)

Country Link
FR (1) FR2555380B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866308A (en) * 1988-04-11 1989-09-12 International Business Machines Corporation CMOS to GPI interface circuit
JP3836719B2 (en) * 2001-12-21 2006-10-25 日本テキサス・インスツルメンツ株式会社 Level conversion circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4096398A (en) * 1977-02-23 1978-06-20 National Semiconductor Corporation MOS output buffer circuit with feedback
JPS5567235A (en) * 1978-11-14 1980-05-21 Nec Corp Output circuit
US4307308A (en) * 1979-11-19 1981-12-22 Gte Laboratories Incorporated Digital signal conversion circuit

Also Published As

Publication number Publication date
FR2555380A1 (en) 1985-05-24

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Legal Events

Date Code Title Description
D6 Patent endorsed licences of rights
ST Notification of lapse
ST Notification of lapse