FR2551579A1 - INTERNAL HIGH VOLTAGE LIFT (VPP) LIMITATION CIRCUIT - Google Patents

Abstract

AN INTEGRATED CIRCUIT MEMORY DEVICE IS EQUIPPED WITH A CIRCUIT TO GENERATE A LINEAR RAMP VOLTAGE BETWEEN 5V (VCC) AND 21V (VPP) AT A RAMP SPEED OF 16VMS. AN INHIBITION MODE IS PROVIDED AND DURING THIS, AN INTERNAL NODE A CORRESPONDING TO THE INTERNAL VOLTAGE VPP IS MAINTAINED AT THE VOLTAGE VCC BY A DOOR WITH T1-T10 TRANSISTORS. A PROGRAMMING MODE IN WHICH AN EXTERNAL PROGRAMMING VOLTAGE IS INTEGRATED ON A MOS T5 CAPACITOR IS ALSO PROVIDED. THE PROGRAMMING VOLTAGE RISE ON THE CAPACITOR IS MAINTAINED AT 16VMS BY THE ACTION OF A TRANSISTOR SWITCH, SO AS TO LOWER THE EXCESSIVE EXTERNAL PROGRAMMING VOLTAGE TO THE GROUND OF THE CIRCUIT IN RESPONSE TO AN EXCESSIVE OVERVOLTAGE RISE. THE CAPACITOR.

Description

The invention relates to integrated circuits More particularly, it

  relates to an internal circuit used to adjust the rise time of the internal high voltage (Vpp) in

  an integrated circuit memory device.

  Solid memory devices such as E 2 PROM devices which are manufactured using a thin oxide tunneling technique are subject to accidental rupture of the oxide when a write or erase voltage is applied on both sides. other of the thin oxide layer, for example between the substrate and the floating door, exceeds a level

  maximum tolerance To avoid such an accidental rupture of the oxide, an external high voltage programming signal (Vpp) is processed by means of an external circuit or device to obtain a pulsed signal having an exponential waveform d '' an RC time constant of 600 us.

  Thus, the solution of the prior art to prevent accidental rupture of the oxide consists in conforming the external high voltage Vpp with an external circuit formed of components supplied by the user to limit the time of rise of an internal voltage Vpp generated from external voltage These signal shaping circuits increase the overall complexity of the circuits because they require additional components and circuit installation space. Consequently, the energy requirements of the circuits are increased and the initial establishment and maintenance of the circuits is further complicated. This is particularly true because prior art waveform conforming circuits are typically of an RC type having variable capacitances or variable resistors that 'It is necessary to optimize to ensure correct functioning of the circuits.In addition, these circuits lack precision and as a result, they are subject to operation

  degraded under varying environmental conditions.

  In a typical application of an E PROM device where the external high voltage Vpp = 21 V, the maximum voltage allowed on either side of the thin oxide zone of the device must be limited to approximately 11.4 V. provide a linear ramp at a speed of 16 V / ms, when the external high voltage Vpp = 21 V, limits an internal high voltage Vpp provided for on either side of the oxide zone of the circuit to approximately 11.5 V Consequently, we recognize that we can use an internally generated linear ramp speed of

  16 V / ms for example, instead of the exponential waveform 5 of 60 ms RC generated externally, and still satisfactorily limit the voltage applied on either side of the thin oxide zone with tunnel effect of the device This idea makes it possible, in part, to advantageously replace the external high-voltage programming circuit with internal cooked circuits.

  In particular, the invention provides a linear ramp generator circuit located inside the device for generating a linear ramp voltage between 5 V (Vcc) and 21 V (Vpp) while maintaining a ramp speed 15 of 16 V / ms The internal linear ramp generator cooperates with a bypass circuit which conducts so as to direct the programming voltage towards ground, thus limiting the voltage applied on either side of the thin oxide zone. the invention avoids the possibility of an accidental rupture of the thin oxide during a programming mode for writing or erasing the device. This protection is advantageously provided independently of a high

  external voltage supplied to the device.

  In the preferred embodiment of the invention, the 25 E 2 PROM can operate in a programming inhibition mode and in a programming mode In the programming inhibition mode, a first node of internal circuits

  is maintained at an internal low voltage (Vcc) by the operation of a transistor gate in response to a programming inhibition signal The first node of internal circuits is directly coupled to the internal circuits of the device and therefore provides a internal high voltage power bus Vpp.

  In the programming mode, the dull high voltage Vpp ex35 is integrated on a metal oxide silicon (MOS) capacitor to supply the internal high voltage (Vpp) in such a way that the voltage thus generated rises in a linear waveform Si the internal high voltage Vpp rises at a speed exceeding 16 V / ms, a switch to

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  transistors is actuated so as to divert the excess current to a circuit ground, thus limiting the excessive rise in the internal high voltage Vpp supplied to the device. Consequently, a limiting circuit integrated on a monolithic silicon substrate is proposed in which the ramp speed of an internal programming signal is fixed at a predetermined elevation speed, for example 16 V / ms and in which the speed ramp does not depend on the external programming voltage or the rise time of the external voltage Consequently, there is no need to process or pulse an external high voltage signal or to provide complicated circuits input signal waveform The number of components of the cir15 baked and the line routing space are thus minimized

  while the energy consumption of the circuits is reduced.

  Furthermore, there is no need to initially adjust external waveform circuits or to maintain their fit, and excessive maintenance is also not necessary due to degradation of the qualities of the external circuit due to at varying input signal and environmental conditions. Figure 1 is a diagram of an internal ramp speed pulse circuit according to the invention; Figure 2 is a graph of the voltage on either side of a thin oxide layer as a function of time for various programming voltage input signals in an integrated circuit memory device; Figure 3 is a graph of a linear ramp cor30 responding to an internal programming voltage provided by the invention; FIG. 4 is a graph also representing a linear ramp corresponding to an internal programming voltage provided by the invention and FIG. 5 is a graph of a linear ramp of

  the internal programming voltage provided by the invention.

  The preferred embodiment of the invention generates a linear ramp between 5 V (Vcc) and 21 V (Vpp) at a speed

  of 16 V / ms ramp The preferred embodiment is

  presented by FIG. i and comprises transistors T 1 to T 10 coupled together between the voltage Vcc, the voltage Vpp

and the mass.

  Two operating modes are provided in this preferred embodiment, a programming inhibition mode and a programming mode In + e programming inhibition mode, the external voltage Vpp = 21 V and the programming voltage PGM = voltage Vcc The internal voltage Vpp (node A in FIG. 1) is maintained at voltage Vcc by 10 the transistor Tl ,, the transistor T 2 is cut off because its gate (node B in FIG. 1) is kept at ground by the transistor T 4-, the circuit node C is discharged to ground by the transistor T 8 and the circuit node D is polarized by

  so as to conduct to ground the current passing through the transistor T 9.

  In the programming mode, the external voltage Vpp = 21 V, direct current, and the programming voltage PGM = 0 V (PGM) The transistors T 1 and T 4 are switched off in the absence of the PGM voltage. voltage at node B, supplied via transistor T 3, rises towards the external voltage Vpp This voltage rise, in turn, varies the internal voltage Vpp (circuit node A) towards the voltage external Vpp via the transistor T 2 Correspondingly, there is a rise in voltage 25 on either side of the transistor T 5 (which has the configuration of a MOS capacitor) The current supplied to the circuit node C by the transistor T 5 is: ic = CT 5 d V / dt (1) To obtain a linear ramp speed d V / dt = 16 V / ms 30 in the preferred embodiment of the invention in which CT 5 = 20 exp 10 12 F, i = 0.32) A The passage of the current 5 through the transistor T 8 is fixed by the transistors T 9 and T 10 and can include a ni minimum ramp or offset calf

  of initial point, determined by the transistors T 9 and T 10.

  In the preferred embodiment of the invention, an initial offset of 5 V is ensured at the ramp voltage The current passing through the transistor T 9 is independent of the voltage Vcc since the transistor T 9 is in the region of function -

saturation.

  If the ramp speed of the internal voltage Vpp (node A in Figure 1) exceeds 16 V / ms, the current i increases according to equation (1) above Consequently, the voltage at the 5 circuit node C s This results from the fact that the transistor T 8 is in the saturated state As the voltage at the circuit node C increases, the transistor T 6 is made conductive and leads to the ground of the circuit the excess voltage present at the node of circuit B, passing through transistor 10 T 7 The conduction of transistor T 2 is consequently reduced, which decreases the ramp speed at the new BA circuit node, the ramp speed of the internal voltage Vpp (node

  A in Figure 1) is also reduced.

  FIG. 2 is a graph of the voltage on either side of a thin layer of oxide, in an integrated circuit memory device, as a function of time, for various programming voltage input signals. In FIG. 2, the normal exponential waveform of 600 us RC is compared with various other waveforms, including the linear 20 V ramp of 16 V / ms generated by the preferred embodiment of the invention. see from the graph that various ramp values can be chosen according to the needs of the thin oxide layer of the integrated circuit in question. Consequently, the invention is easy to adapt for the purpose of use in any memory device with integrated circuits which uses the writing and erasing mode with a thin oxide tunnel effect. It follows that the ramp values provided by the embodiment of the invention can

  be easily modified to suit various circuit parameters.

  FIGS. 3 to 5 show various operating characteristics of the preferred embodiment of the invention. In FIGS. 3 to 5, the term C Ex refers to a line enabling circuit When the line C Ex is low, the internal linear voltage ramp Vpp I starts; when the line C Ex is high, the internal voltage Vpp I discharges in its initial state of 5 V, direct current (Vcc) The terms Vpp I = Vppi = Vip all refer to the internal signal of voltage Vpp (circuit node A in FIG. 1) The index "i" is used to indicate an internally generated signal The term TA refers to the ambient temperature at which the measurements represented were taken in this case, the ambient temperature, that is to say approximately 25 C Finally, the term Vppx refers to the signal input which required an exponential waveform of 600 ps RC in prior art circuits The subscript "x" is used to indicate a signal

applied externally.

  Figures 3 and 4 show the ramp speed of the internal voltage Vpp on various embodiments of the invention More particularly, Figures 3 and 4 are graphs of a linear ramp corresponding to a voltage of

  internal programming provided by the exemplary embodiment of the invention.

  FIG. 5 is a graph of a linear ramp corresponding to an internal programming voltage Vpp I, the external voltage Vpp (Vppx) being at 21 V and 15 V The graph

  of FIG. 5 illustrates the fact that the dull ramp speed in20 ensured by the exemplary embodiment of the invention is independent of the external voltage Vpp.

  It can be seen that, when the invention is incorporated into an integrated circuit memory device, the ramp speed of the internal voltage signal Vpp is maintained at 16 V / ms 25 (or otherwise, as desired, in various modes of equivalent execution) and is therefore not a function of the external voltage Vpp nor of the voltage Vcc Therefore, there is no need to pulse the external voltage Vpp nor to use the complicated external synchronization circuit and shape generator wave 30 required in prior devices Consequently, the invention ensures a saving of functional elements and improved reliability of the operation of the circuits while avoiding the rupture of the oxide due to an excessive voltage drop during a mode of write or erase programming, in a solid memory device with integrated circuits. The above has been indicated by way of example Miscellaneous

  equivalent embodiments of the invention are possible.

  For example, we can provide a different ramp speed

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  by varying the capacitance of the transistor T 5 in accordance with the ramp speed desired for a particular technology or a particular device.

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Claims (4)

  1) Circuit used to control the rise time of the internal voltage in an integrated circuit and characterized in that it comprises: a first node (A) on the integrated circuit for receiving a voltage from a source external to that here and to draw an internal voltage therefrom for the integrated circuit; a capacitor (T 5) on the integrated circuit, having a first terminal coupled to the first circuit node, for integrating a current received from the external voltage source at a speed corresponding to a predetermined voltage rise time; current reduction means provided on the integrated circuit and coupled to a second terminal of the capacitor 15 (T 5), these means providing a signal used to control the rise time as a function of the integration of the current, received from the external source, by the capacitor, and a switch provided on the integrated circuit, presenting a control terminal coupled so as to receive the signal of control of time of rise (PGM), this switch being able to limit the rise of the external source voltage in response to the elevation time control signal, so that the external source voltage is brought to the first node (A) at a predetermined and set speed. 2) Circuit according to claim 1, characterized in that the current reduction means comprise in   in addition to low-voltage reference means serving to establish a minimum initial voltage of the ramp generator.   3) Circuit according to claim 1, characterized in that the integrated circuit constitutes a memory device with integrated circuit.   4) Circuit according to claim 3, characterized in that it further comprises means for alternately selecting and deselecting the operation of the ramp generator circuit during a corresponding programming mode of the circuit and a mode of inhibition of the circuit programming.   ) Internal ramp generator used to generate, in an integrated circuit memory device, a voltage of i 9 2551 2551579   chosen internal linear ramp having a voltage rise time independent of an external voltage source, characterized in that it comprises: a first transistor (T 3) having a first bor5 not coupled to the external voltage source, a second terminal and a control terminal coupled to a first (B) ramp generator signal node; a second transistor (T 2) having a first terminal coupled to the external voltage source, a control terminal coupled to the first ramp generator signal node (B) and a second terminal coupled to a second (A) node ramp generator signal; an integrating capacitor (T 5) having a first terminal coupling Ce to the second node of ramp generator signal, this capacitor Atant coupled so as to integrate a voltage supplied passing through the second transistor (T 2), in function from the first transistor (T 3), and drawn from the external voltage source, to supply the internal linear ramp voltage to the second ramp generator signal node (A), this capacitor (T 5) having a second terminal coupled to a third ramp generator signal node (C); a third transistor (T) having a first terminal coupled to the third ramp generator signal node (C), a second terminal coupled to a ramp generator ground node and a control terminal coupled to a fourth node (D ) ramp generator signal; a reference voltage source transistor (T 9) coupled to the fourth ram30 signal generator node () so as to maintain the third transistor (T 8) at a chosen saturation speed corresponding to an initial voltage offset of ramp, and a fifth transistor (T 6) having a first terminal coupled to the first ramp generator signal node (B), a second terminal coupled to the ramp generator ground node and a control terminal coupled to the third node (C) of ramp generator signal, so that a charge integrated by the capacitor (T 5) and corresponding to the internal linear ramp voltage present at the second 2551579   ramp generator signal node (A) controls the saturation of the fifth transistor which (T 6) in turn controls the saturation of the second transistor which (T 2) correspondingly conducts the voltage supplied by the external source to distance from the second ramp generator signal node (A) and alternately, conducts the external voltage, passing through the fifth transistor (T 6), to the ground node of ramp generator.   6) Generator according to claim 5, characterized by O 10 the fact that it further comprises: a sixth transistor (Tl) having a first terminal coupled to an internal voltage source, a second terminal coupled to the second node (A) of ramp generator signal and a control terminal coupled to receive a programming control / programming inhibit signal (PGM), and a seventh transistor (T 4) having a first terminal coupled to the first node (B) of ramp generator signal, a second terminal coupled to the ramp generator ground node and a control terminal coupled to receive the programming inhibit programming signal (PGM), so that the internal ramp generator can operate as a linear ramp voltage generator when a programming mode is selected by supplying a programming control signal, and the internal ramp generator is inhibited when a mode of inhibition of programming is chosen by supplying a control signal programming inhibition.