FR2549317B1 - Circuit de remise sous tension pour circuit logique - Google Patents

Circuit de remise sous tension pour circuit logique

Info

Publication number
FR2549317B1
FR2549317B1 FR8311612A FR8311612A FR2549317B1 FR 2549317 B1 FR2549317 B1 FR 2549317B1 FR 8311612 A FR8311612 A FR 8311612A FR 8311612 A FR8311612 A FR 8311612A FR 2549317 B1 FR2549317 B1 FR 2549317B1
Authority
FR
France
Prior art keywords
circuit
power
logic
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8311612A
Other languages
English (en)
Other versions
FR2549317A1 (fr
Inventor
Sylvain Kritter
Daniel Vellou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EFCIS
Original Assignee
EFCIS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EFCIS filed Critical EFCIS
Priority to FR8311612A priority Critical patent/FR2549317B1/fr
Publication of FR2549317A1 publication Critical patent/FR2549317A1/fr
Application granted granted Critical
Publication of FR2549317B1 publication Critical patent/FR2549317B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
FR8311612A 1983-07-12 1983-07-12 Circuit de remise sous tension pour circuit logique Expired FR2549317B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8311612A FR2549317B1 (fr) 1983-07-12 1983-07-12 Circuit de remise sous tension pour circuit logique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8311612A FR2549317B1 (fr) 1983-07-12 1983-07-12 Circuit de remise sous tension pour circuit logique

Publications (2)

Publication Number Publication Date
FR2549317A1 FR2549317A1 (fr) 1985-01-18
FR2549317B1 true FR2549317B1 (fr) 1988-10-07

Family

ID=9290762

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8311612A Expired FR2549317B1 (fr) 1983-07-12 1983-07-12 Circuit de remise sous tension pour circuit logique

Country Status (1)

Country Link
FR (1) FR2549317B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625633B1 (fr) * 1987-12-30 1990-05-04 Sgs Thomson Microelectronics Circuit de remise sous tension pour circuit integre en technologie mos
US5187389A (en) * 1991-05-03 1993-02-16 National Semiconductor Corporation Noise resistant low voltage brownout detector with shut off option

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2433328A1 (de) * 1974-07-11 1976-01-29 Philips Patentverwaltung Integrierte schaltungsanordnung
JPS5542410U (fr) * 1978-09-08 1980-03-19
US4296338A (en) * 1979-05-01 1981-10-20 Motorola, Inc. Power on and low voltage reset circuit
JPS56122225A (en) * 1980-02-29 1981-09-25 Fujitsu Ltd Power on reset circuit

Also Published As

Publication number Publication date
FR2549317A1 (fr) 1985-01-18

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Legal Events

Date Code Title Description
CL Concession to grant licenses
ST Notification of lapse