FR2547080A1 - Method and device for checking the operation of digital equipment supplying a train of data at high frequency - Google Patents

Abstract

The present invention relates to a method and to a device for checking the operation of digital equipment supplying a train of data at high frequency. The method is characterised in that a repetitive train TR of digital data at high frequency f is recorded by samples I, II, III, IV etc. during each stimulation period tau , each sample being constituted by a constant or variable number M of megabits, in that the samples I, II, III, IV etc. thus recorded are read between the end of one sampling and the end of the following sampling, and in that the samples I, II, III, IV etc. thus read are multiplexed so that the original repetitive train TR of digital data at high frequency f is reconstituted into a train TLR of reduced frequency. Application to checking the operation of telemetry multiplexers used for data on board a satellite.

Description

 The present invention relates to a method and a device for verifying the operation of digital equipment providing a high frequency data stream, such as 100 megabits / second or more, for the purpose of verifying remote control multiplexers. for data on board a satellite, including high frequency data from synthetic aperture radar data processing equipment.

 In general, a telemetry multiplexer verification chain includes. a multiplexer stimulation memory, simulating signals to be multiplexed on board the satellite,. the multiplexer to check,. a primary synchronizer,. a secondary synchronizer, and. a verification computer.

 Solutions have been proposed in the prior art to solve the problem posed by such a verification by using a means adapted to the analysis of errors of digital data streams at high frequency.

A first solution has been to develop specialized information processing units operating at high data frequencies, since said analysis is unlikely to be possible at frequencies of 100 megabits / second or more with secondary synchronizers and conventional computers. more so if we want to encrypt the error rate or if we want to implement fault finding programs
Another proposed solution could be to use a high performance magnetic recorder, which would then be replayed at a reduced frequency.

 However, the solutions of the prior art have very serious disadvantages, particularly - as regards the development of specialized information processing units, the latter do not exist on the market and it is therefore necessary to make them to build, which entails very high costs, and - as regards the use of a high-performance magnetic recorder, the cost of such a recorder is very high; furthermore, it is impossible to have an error analysis result in real time, which implies extensions of the verification times and the increase of the related costs.

The present invention accordingly has a goal of
Providing a method and device for checking equipment providing a high frequency data stream that better meets the requirements of the practice than previously known methods and devices for the same purpose, including - high frequency digital data are reconstructed at a frequency which is a fraction of the original train frequency - in that the verification strings can be realized with a sensible economy of means, because the secondary synchronizer and the verification computer can be conventional equipment thanks to the reduced frequency of the reconstructed train, and - in that the detection of failures in the digital circuits of the equipment-to check is possible even in the presence of noise.

The present invention relates to a method for verifying the operation of digital equipment providing a high frequency data stream, such as 100
Megabits / second or more, especially for the verification of multiple telemetry sensors used for satellite data, including high frequency data from synthetic aperture radar data processing equipment, the equipment to be verified being stimulated by repetitive stimulation signals of which period is known, in response to which signals this equipment provides a repetitive train of high frequency digital data whose period is equal to the stimulation period, which method is characterized in that the repetitive train of high frequency digital data is recorded in samples during each stimulation period, the time elapsed between the end of one sampling and the beginning of the next sampling being equal to the said stimulation period and each sample being constituted by a constant or variable number of megabits, the samples thus recorded are
read between the end of one sampling and the end of the next sampling, and the samples thus read are multiplexed, so that the original repetitive train of high frequency digital data is reconstructed into a data stream whose frequency is reduced. at a fraction of the frequency of said original train, and this for each stimulation period and for each sampling.

According to an advantageous variant of this embodiment, in the case where the number of megabits sampled during each sti mu period is constant, the recording of each sample is carried out
by recording a first part of each sample
and registering the remaining inde
the first part of the recording operation without any break in continuity, just as the reading of each sample, which takes place between the end of a sampling and the end of the next sampling, is performed by reading the first part of each sample between the end of a sample and the beginning of the next sample, while the second part of each sample is read immediately following the sampling.
reading of the first part, namely during the next sampling, the time elapsed between the end of one sampling and the beginning of the next sampling being always equal to the stimulation period.

 The present invention also relates to a device for verifying the operation of a digital equipment providing a high frequency data stream, such as 100 megabits / second or more, notaaen.t for the verification of telemetry multiplexers which are used for data on board a satellite, including high frequency data from synthetic aperture radar data processing apparatus, and whose verification chain includes a pacing memory which is a recycled memory, that is, which provides said equipment to verify repetitive stimulus signals of known period, said verify multiplexer which provides a repetitive train of high frequency digital data in response to said stimulus signals and whose period is equal to the stimulation period, a primary synchronizer, a secondary synchronizer and a verification computer, which device is characterized in that said verification chain comprises, between the primary synchronizer and the secondary synchronizer, two memories which perform, alternately and during successive stimulation periods, the sample recording of said repetitive data train high frequency numerals, the time elapsed between the end of one sampling and the beginning of the next sampling being equal to the said stimulation period and each sample being constituted by a constant or variable number of megabits, which two memories These samples are read from the sample during the time elapsing between the end of one sampling and the end of the next sampling, the samples thus read being multiplexed so that the original repetitive train of data High Frequency Numbers are reconstituted in one tr and data whose frequency is reduced to a fraction of the frequency of said original train, and this for each stimulation period and for each sampling.

 According to an advantageous arrangement of this embodiment, upstream and downstream of said two memories are placed two switches, the first of which distributes alternately to these two memories the frequencies of the repetitive train of high frequency digital data under the control of a bit counter which receives a clock signal from the primary synchronizer, while the second switch also receives alternately from said two memories and under the control of said bit counter, the samples read at a reduced frequency.

According to an advantageous modality of this arrangement, the bit generator is a programmable coapteur which progresses the number of
Megabits sampled during each pacing period depending on the verification phase of the equipment concerned.

 According to an advantageous variant of this embodiment, in the case where the number of megabits sampled during each stimulation period is constant, a main memory ef fe ctue seldom records a first part of each sample while two secondary memories perform alternately, and immediately following the recording operation corresponding to the main memory, the recording of the remaining part of each sample as well as said main memory reads the first part of each sample between the end of one sampling and the beginning of the next sampling while said two secondary memories read alternately, and immediately following the reading performed by the main memory, the remaining part of each sample during the next sampling , the reading of each complete sample always taking place between the end of an sampling and the end of the next sampling and the time elapsed between the end of one sampling and the beginning of the next being always equal to the said stimulation period.

 In addition to the foregoing, the invention also comprises other provisions, which will emerge from the description which follows.

 The invention will be better understood with the aid of the additional description which follows, which refers to the accompanying drawings in which - Figure 1 illustrates the method of the invention for reconstructing a high frequency digital data stream in a frequency reduced by a factor of 5 - FIGS. 1A and 1B also illustrate the same method for a reduction factor of the original frequency which is equal to 3 and 4, respectively - FIG. 2 shows schematically a chain of verification according to the invention of equipment providing a high frequency digital data stream; FIG. 3 shows, in the form of a block diagram, or black box, the device according to the invention, and FIG. 4 illustrates a variant of the method of the invention, illustrated by FIGS. 1, 1A and 1B. , to reduce the need for memory.

 It should be understood, however, that these drawings and the corresponding descriptive parts are given solely by way of illustration of the subject of the invention, and in no way constitute a limitation thereof.

As an example, digital equipment to check
EV, providing a high frequency data stream f, consists of a multiplexer at 100 megabits / second is essentially to detect failures in the digital circuits of this equipment, and this even in the presence of noise.

 In particular, it is a matter of verifying the operation of a telemetry EV multiplexer used for data on board a satellite, including high frequency data from the synthetic aperture radar data processing apparatus.

 The insertion of such an EV multiplexer into a conventional verification chain including, in order, a memory of stimulation of the multiplexer EV, the multiplexer EV to be verified, a primary synchronizer SP, a secondary synchronizer SS and a computer of OV verification, is unlikely for the analysis of errors of digital data streams at high frequency, in particular by the limits imposed by the SS secondary synchronizer and the OV computer truth, and this especially if you want encrypt the error rate or to implement fault finding programs.

 However, the present invention makes it possible to insert said high-frequency EV multiplexer in a conventional verification chain because it makes it possible to reconstruct a high-frequency digital data stream into a prefixed frequency-reduced train: thus it is possible to use a secondary SS synchronizer and an OV verification computer quite classically located thanks to the reduced frequency of the original train to be checked.

The equipment to be verified EV is first stimulated thanks to the memory of stimulation, which is a recycled memory, MSR, that is to say which provides to this equipment
EV repetitive stimulation signals whose period
T is known. The equipment EV, in response to said signals will provide at its output a repetitive train TR <cf. FIG. 1) of high frequency digital data, for example f = 100 megabits / second, the period of which is equal to said stimulation period T. If the stimulation period T = 1 second, this implies that the number of bits in FIG. each period T is T = 100 Megabits.

According to the method of the invention, during the first stimulation period T1, in the first memory M1, at the output of said equipment EV, a sample plum I of the repetitive train TR of high frequency digital data f which, for example, has a number M of sampled bits equal to 25% of the total number T of bits, i.e.
Megabits.Then, during the second period of stillation # 2, we record in a second memory M2, a
second sample II whose size M may vary,
for example, between 25% to 50% of T, namely between 25 and 50 Megabits and so on for the third and fourth samples, III and IV, during the stipulation periods t3 and T4 :: in Figure 1 ( as well as in FIGS. 1A, 1B and 4 referring to other examples of application of the method according to the invention) we have assumed, for reasons of smplification, to carry out sampling whose size N remains constant for one period from stimulation T to the other.

 The time elapsed between the end of a naqe sample (ie the end of memory use) and the start of the next sample (ie, the start of use of the other memory) is equal to the stimulation period T.

 Now, the memory M1 is read during the time that elapses between the recording completed in the memory M1 and the recording completed in the memory N2, and so on at each pacing period T.

 Referring always to Figure I and assuming that the size M of each sample is constant, it is evident that the reading of the first sample I, and therefore of each subsequent sample, II, III, IV, is recorded. at a frequency of 100 megabits / second, is in a time five times greater than the recording time: this means that each of the memories M1 and M2 is read at a frequency five times lower, namely at 20 megabits / second, so that the multiplexing between the outputs of these two memories provides a continuous train TLR digital data reconstructing the original train TR at a frequency five times lower and equal - as already said - at 20 megabits / second.

 FIGS. 1A and 1B illustrate the method of reconstructing a TR train of high frequency digital data f into a frequency reduced LRT gear by a factor of 3 and 4, respectively. It may be noted that, in the case of reconstruction at a frequency three times lower, the third stimulation period T is not used, just as the fourth and the fifth stimulation period T4 and 5, respectively, are not used. no longer used in the case of reconstruction at a frequency four times and five times lower, respectively: therefore in general the '> e-th period of stimulation TV, corresponding to a reduction factor equal to v, is not used in the aforementioned reconstruction method.

 The first of the examples (see FIG. 1), which, given the following, is given by way of illustration of the process according to the invention, corresponds to a reduced frequency of 20 Megabits / second which, while being the smallest of the reduced frequencies obtained in said examples (see FIGS. 1, 1A and 1B), is still too high to be accepted by conventional equipment, for which it is necessary to go down to five megabits / second, which implies in the case in question a reduction of the frequency f of 100 megabits / second of the original TR train by a factor @ equal to 20.

For the application of the method according to the invention, it is necessary to know the number T of megabits supplied by the item EV to be verified, as well as the desired reduction factor @: this is equivalent to setting the size M of each sample, so the memory capacity of memories M1 and M2 ie, this is equivalent to setting the number n of samplings necessary to completely "explore" a train TR of high frequency digital data f, where n is equal to
Figures 1A, 1B and 1 then allow the desired reduction factor V to be expressed using the expression n + 1.

The minimum value of n is 2, which means that the frequency is reduced by n + 1 = 2 + 1 = 3 times only, while the maximum value of n is T, in this case each
sample being composed of a single bit at each stimulation period #, which corresponds to a reduced frequency of n + 1 = T + 1 time. It is thus clear that the reduction factor # = n + 1 can be enormous, but that the corresponding verification times can become prohibitive, so that n must be fixed between these two extreme values taking into account the said relationship existing between the reduction factor v and the verification time. It should be emphasized that report No. 5 N can even be changed depending on the verification phase.

 it is interesting to note that the reconstruction of a TR train of high frequency digital data f into a TLR train of reduced frequency digital data f / thXl) is valid even in the presence of errors, systematic and random, contained in the original TR train.

Indeed, as for the systematic errors, because the complete cycle of the original signal is reconstructed, these errors can not escape. As for the random errors, these can occur in a part of the original train TR that has not been sampled; however, sampling does not destroy the statistical distribution of errors: in other words, if the verification is long enough, the random error rate with respect to the amount of data checked respects the probability of errors.

 Figure 4 shows a very advantageous variant of the method according to the invention, which allows a significant saving of memory necessary for sampling and is applicable whenever it is necessary to have fixed n.

 To show how this is possible, let us first refer to Figure 1 for which n = 4, this value of n being given - assuming T = 100 Megabits per stimulation period - by n = T = 100 = 4: in this M 25 we see that the memory M1 is empty at 80% when the memory M2 begins its recording cycle and vice versa.

This suggests, then, to perform each sampling using a PM main memory that records
25
80% = (100 - 20)% = [100 - (25 - 4 + 1)]% of each sample, two further secondary memories MS1 and MS2 being used alternately and immediately following the main memory MP, to record 20% = (25 - 25)% of each sample.

4 + 1
The reduced frequency reading of each sample is performed, then, using the main memory Mp and, alternatively and immediately following the latter, secondary memories MS1 and MS2. The advantage of this variant of the method is that the total requirement in the sampling memory is, in this case, (80 + 20 + 20)% = 120% of each sample instead of 200%, which corresponds to using said two memories M1 and M2 only, each having a capacity equal to 100% of each sample.

If we now refer to Figure 1A, still under the assumption of T = 100 Megabits per stimulation period #, we have that the ratio n = T = 100 = 2 and that
M 50M each of said memories M1 and M2 is empty at 66.6% when the other memory begins its recording cycle.

In this case, the main memory MP must sample
read 66.6% = (100 - 33.3)% = [100 - (50 - 2 + 1)]% of each sample, while each of the two secondary memories MS1 and MS2 must sample 33.3% = (50 - 50)% 2 +% 1 of each sample, which implies a total memory requirement of (66.6 + 33.3 + 33.3)% = 133.3 M instead of 200%.

Similarly, in the case illustrated by Figure 1B, with
T = 100 Megabits per stimulation period #, we have that the ratio n = T = 100 = 3 and that each of the two memories
M 33.3
M1 and M2 is 75% empty when the other one starts
recording cycle.

In this third case, the main memory
MP must sample 75% = (100-25)% = [100- (33.3- 33.3)]% of each sample, while each of the two secondary memories MS1 and MS2 must sample 25% = (33 , 3 - 33.3) of each sample, which
3 + 1 implies in this other case a total memory requirement of (75 + 25 + 25)% = 125% instead of 200%.

On the basis of these examples, we can generalize the sampling of a high frequency digital data stream f into a reduced frequency train f / (n + 1).
T n being fixed and equal to M, using a main memory MP and two secondary memories MSI and MS2, taking into account that the capacity P% of the main memory Mp and the capacities Si po and S2 % of secondary memories
MS1 and MS2, expressed as a percentage of each sample, are given by the following expressions
P% = tT - (M- n + ÓM S1% = S2% = (M - M)%
n + 1 where M = T.

not
For example, to achieve a reduction of the frequency f = 100 Megabits / second to f '= f / (n + 1) = 5 Megabits / second, namely a reduction factor v = n + 1 = 100 = 20, this implies that, always with T = 100 Megabits per stimulation period T, the sampling memory requirements are as follows, considering that T 100 n = v-1 = 20-1 = 19 and that M = n = 19 :
P% = 95%
If% = S2% = 5%, that is, the total memory requirement is (95 + 5 + 5)% = 105% instead of 200%.

FIG. 3 shows the functional diagram, or black box "BN, of a device according to the invention which, using the method of the invention for previously imposed values of the number T of megabits per stimulation period. T and the reduction factor, namely the
T ratio n = M, where M is the size of each sample, must be able to match a train TR of high frequency digital data f, a reconstructed data LRT train at reduced frequency of said reduction factor v = n + 1 , ie at a frequency f / (n + 1).

 A device which makes it possible to achieve this result is inserted, in accordance with the invention, into the verification chain (the general composition of which has been indicated at the beginning of this description). This chain includes an MSR recycled pacing memory (which is highlighted by the arrow r in Figure 2); that is, that a memory is used which repeatedly provides signals to the EV equipment which, in response, provides a TR train of high frequency digital data having the same period as that of the stimulation.

 The repetitive TR train is found at the output of the EV equipment mixed with noise, which is indicated in FIG. 2 by the summation of said EV equipment output signal and the noise signal, which is shown schematically by FIG. the noise generator GB, the resulting signal being processed by the primary synchronizer SP which provides, in particular, the repetitive train of digital data at 100 megabits / second, after processing.

According to the invention, this high frequency digital data train TR is distributed using a switch Ai, alternately and during successive stimulation periods T, with two memories M1 and M2 which are inserted between the primary synchronizer SP and the secondary synchronizer SS and which perform sample recording of said high frequency digital data stream f. The number M of bits sampled during each stimulation period #, namely the size of the sample, can be constant or variable: FIGS. 1, 1A, 1B and 4 refer to a constant number M =, so that the ratio n between the number T of megabits per stimulation period T and the number M of megabits sampled during each period T
of #, namely the ratio n = M, is also constant.

 The time that elapses between the end of a sample swims, performed by the memory MI, and the beginning of the next sampling, performed by the memory M2, is equal to the stimulation period T.

 During the time that elapses between the end of a lesson.

At the sampling and the end of the next sampling, each of the memories Mi and M2 alternately performs the reading of the previously recorded sample: since both said memories NI and M2 are multiplexed, this results in a reconstructed digital data stream. via a switch A2 at a reduced frequency with respect to the frequency of the original digital data stream.

The two switches AI and A2 distribute the high frequency samples and receive the reduced frequency samples, respectively, under the control of a bit counter CB: the latter may advantageously be of the programmable type if it is desired to change the
T ratio n = M, ie whether it is desired to change M following the verification phase of the EV equipment.

In the case where the ratio n, and therefore M, is constant, it is advantageous to use a main memory
MP, to be used in conjunction with two secondary memories MS1 and MS2 as indicated below, so as to very substantially reduce the memory requirement.

 The main memory MP is made to record a first part of each sample, while the memories MS1 and MS2 perform, alternately and during successive stimulation periods, the recording of the remaining part of each sample, and this immediately. following the main memory MP.

 Reading. at reduced frequency of each sample is carried out as follows - the main memory MP reads said first part of each sample between the end of one sampling and the beginning of the next sampling, while the two secondary memories MS1 and MS2 read alternatively and immediately following the MP memory, said remaining part of each sample, and this during the following sampling t obviously, the reading of each complete sample always takes place between the end of a sampling and the end of the sample. # next sampling and the time elapsed between the end of one sampling and the beginning of the next sampling is always equal to the said stimulation period T.

The verification chain of FIG. 2 is closed by a secondary synchronizer SS which provides signals resulting from a decommissioning of the train
Reduced frequency reconstructed TLR f / (n + 1) to a 0V verification computer, which also produces the stimulation signals to control the MSR recycled pacing memory.

As already mentioned, the secondary synchronizer
SS and the OV verification computer may be relatively simple equipment due to the reduced frequency of the reconstructed digital data stream.

 As is apparent from the above, the invention is not limited to those of its modes of implementation, implementation and application which have just been described more explicitly; it encompasses all the variants that may come to the mind of the technician in the field, without departing from the scope or scope of the present invention.

Claims (1)

CLAIMS IV, ...) during each stimulation period (X), the time elapsed between the end of one sampling and the beginning of the next sampling being equal to the said stimulation period (X) and each sample being constituted by a constant or variable number (M) of megabits, in that the samples (I, II, III, IV, etc.) thus recorded are read between the end of a sampling and the end of the following sampling, and in that the samples (I, II, III, IV, ...) thus read are multiplexed, so that the original repetitive train (TR) of high frequency digital data (f) is reconstituted into a train (TLR) of data whose frequency is reduced to a fraction of the frequency (f) of said original train (TR), and this for each stimulation period (T) and for each sampling.  1 - A method of verifying the operation of a digital equipment providing a high frequency data stream, such as 100 Megabits / second or more, in particular for the verification of telemetry multiplexers used for data on board a satellite, including high-frequency data from synthetic aperture radar data processing apparatuses, the verification equipment (EV) being stimulated by repetitive stimulation signals of known period (#), in response to which signals this equipment provides a repetitive train (TR) of high frequency digital data (f) whose period is equal to the pacing period (T), which method is characterized in that the repetitive train (TR) of high frequency digital data (f) ) is recorded by samples (I, II, III, III, IV, ...;) is read immediately following the reading of the first part, ie during the next sample, the time elapsed between the end of a sample and the beginning of the next sample always being equal to the stimulation period (T). Ion (I, II, III, IV, ...), which takes place between the end of one sampling and the end of the next sampling, is performed by reading the first part of each sample (I, II, III, IV, ...) between the end of one sampling and the beginning of the next sampling, while the second part of each sample (I, II,  A method according to claim 1, characterized in that, in the case where the number (M) of megabits sampled during each stimulation period (T) is constant, the sample sample record (I, II, III, IV, ...) is performed by recording a first part of each sample (I, II, III, IV, ...) and recording the remaining part independently of the recording operation of the first part and without solution of continuity, as well as the reading of each sample IV, ..) thus being multiplexed so that the original repetitive train (TR) of high frequency digital data (f) is reconstructed into a data stream (TLR) whose frequency is reduced to a fraction of the frequency ( f) of said original train (TR), and this for each stimulation period (T) and for each sampling. III, IV, ...) of said repetitive train (TR) of high frequency digital data (f), the time elapsed between the end of one sampling and the beginning of the next sampling being equal to said stimulation period ( X) and each sample (I, II, III, IV, ..) being constituted by a constant or variable number (M) of megabits, which two memories (M1 and M2): of trimmings of samples (I , IL, III, IV, ..) perform the reading of these samples (I, II, III, IV, ..) during the time that elapses between the end of one sampling and the end of the next sampling , the samples (I, 11, III,  (T) successive, sample recording (I, II,  30 A device for verifying the operation of a digital equipment providing a high frequency data stream, such as 100 Megabits / second or more, in particular for the verification of telemetry multiplexers which are used for data onboard a satellite, including high frequency data from synchronous aperture radar data processing apparatus, and whose verification chain includes a memory memory which is a recycled memory (MSR), i.e., which provides said equipment for checking repetitive stimulation signals whose period (T) is known, said checking multiplexer which provides a repetitive train (TR) of high frequency digital data (f) in response to said stimulation signals, and whose period is equal to the pacing period (#), a primary synchronizer, a secondary synchronizer, and a verification computer. on which device is characterized in that said verification chain comprises, between the primary synchronizer (SP) and the secondary synchronizer (SS), two memories (M1 and M2) which perform alternately and during periods of stimulation  4 - Device according to claim 3, characterized in that, upstream and downstream of said two memories (M1 and M2) are placed two switches (A1 and A2), the first (A1) distributes alternately to these two memories (M1 and M2) the different samples (I, II, III, IV, ..) of the repetitive train (TR) of high frequency digital data (f), under the control of a bit counter (CB) which receives a signal of of the primary synchronizer (SP), while the second switch (A2) also receives alternately from said two memories (M1 and M2) and under the control of said bit counter (CB), the samples <I, II, III, IV, ..) at reduced frequency.  5 - Device according to claim 4, characterized in that the bit counter (CB) is a programmable counter which programs the number (M) of megabits sampled during each stimulation period (T) as a function of the verification phase of the concerned equipment (EV).  60 Apparatus according to claim 3, characterized in that, in the case where the number (M) of megabits sampled during each stimulation period <T) is constant, a main memory (MP) performs the registration of a first part of each sample (I, II, III, IV, ..), while two secondary memories (MS1 and MS2) perform alternately, and immediately following the registration operation corresponding to the main memory (MP) recording the remaining part of each sample (I, II, III, BV, ..), as well as said main memory (MP) reads the first part of each sample (I, II, III, IV,) between the end of a sampling and the beginning of next sampling, while said two secondary memories (MS1 and MS2) read alternately, and immediately following the reading performed by the main memory (MP), the remaining part of each sample (I, EH, III, BV, ..) during the next sampling, the reading of each sample (I, II, III, IV, ..) complete always taking place between the end of a sampling and the end of the next sampling and the time elapsed between the end of one sampling and the beginning of the next being always equal to the said stimulation period (#).