FR2545957A1 - High-throughput binary multiplier - Google Patents

High-throughput binary multiplier Download PDF

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Publication number
FR2545957A1
FR2545957A1 FR8307793A FR8307793A FR2545957A1 FR 2545957 A1 FR2545957 A1 FR 2545957A1 FR 8307793 A FR8307793 A FR 8307793A FR 8307793 A FR8307793 A FR 8307793A FR 2545957 A1 FR2545957 A1 FR 2545957A1
Authority
FR
France
Prior art keywords
bits
multiplier
group
latches
multiplicand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8307793A
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English (en)
French (fr)
Other versions
FR2545957B1 (enrdf_load_stackoverflow
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EFCIS
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EFCIS
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Filing date
Publication date
Application filed by EFCIS filed Critical EFCIS
Priority to FR8307793A priority Critical patent/FR2545957A1/fr
Publication of FR2545957A1 publication Critical patent/FR2545957A1/fr
Application granted granted Critical
Publication of FR2545957B1 publication Critical patent/FR2545957B1/fr
Granted legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR8307793A 1983-05-10 1983-05-10 High-throughput binary multiplier Granted FR2545957A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8307793A FR2545957A1 (en) 1983-05-10 1983-05-10 High-throughput binary multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8307793A FR2545957A1 (en) 1983-05-10 1983-05-10 High-throughput binary multiplier

Publications (2)

Publication Number Publication Date
FR2545957A1 true FR2545957A1 (en) 1984-11-16
FR2545957B1 FR2545957B1 (enrdf_load_stackoverflow) 1989-01-13

Family

ID=9288750

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8307793A Granted FR2545957A1 (en) 1983-05-10 1983-05-10 High-throughput binary multiplier

Country Status (1)

Country Link
FR (1) FR2545957A1 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2611286A1 (fr) * 1987-02-23 1988-08-26 Dassault Electronique Circuit integre multiplieur, et son procede de composition

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON COMPUTERS, volume C-24, no. 9, septembre 1975 (NEW YORK, US) C.I. TOMA "Cellular logic array for high-speed signed binary number multiplication", pages 932-935 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2611286A1 (fr) * 1987-02-23 1988-08-26 Dassault Electronique Circuit integre multiplieur, et son procede de composition

Also Published As

Publication number Publication date
FR2545957B1 (enrdf_load_stackoverflow) 1989-01-13

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ST Notification of lapse