FR2532136A1 - Addressing device and method of supplying addresses for video systems. - Google Patents

Abstract

The addressing device for a video image memory processing system is characterised in that it comprises means 20 of determining the lone addresses selected from the desired image memory addresses which it is required to select, means 23 of updating the addresses selected from the desired addresses, at a slower rate than the normal frame rate, and an addressing interpolation means 24 for calculating all the desired addresses having to be selected, on the basis of the data available on the addresses, in the spatial and temporal modes, so that all the addresses having to be selected are available, updated, at normal frame rates.

Description

 The invention relates to a video image processing system intended, inter alia, for the production of special effects on television.

 In known systems used for special effects, video information, for example, is received by an image memory acting as a buffer and, in order to produce the desired special effect, an output processor receives, in a a typical case of data coming from selected addresses within the image memory, for reconstructing an image whose shape or dimensions are different from those of the image introduced into the memory.

 While such systems operate in a limited range of special effects as currently available, their mode of operation hampers their flexibility.

 One of the aims of the invention is to provide a system capable of providing greater flexibility in the handling of images while maintaining their quality, so that the resulting image is not substantially degraded.

The invention has as its object a video processing system for manipulating the shape of the images, characterized by
frame recording means for receiving information on the image points in several locations equivalent to a video frame
addressing means for accessing selected locations of the image memory several times within a frame triode, depending on the necessary manipulation
processing means for processing the image information at any given location each time this location is selected,
and control means for varying the provided processing according to the density of the image information at a given image location, indoors
a frame period.

In another aspect, the invention is directed to an addressing device for an image memory processing system characterized by
means for determining only selected addresses from the desired addresses of the image memory whose access is requested
means for updating the selected addresses among the desired addresses at a slower rate than the normal frame rate
and address interpolation means for calculating all the desired addresses to be accessed from the available address data in the spatial and time modes so that all addresses to which access is to be available are available, updates, at normal frame rates.

The invention will now be described, with reference to the accompanying drawings, in which
Fig. 1 shows a basic embodiment of the system which relates to one aspect of the present invention.
Fig. 2 shows different aspects of image manipulation
Fig. 3 shows in more detail the aspects of the system of FIG. 1 relating to treatment
Fig. 4 shows other details of the treatment
Fig. 5 shows another aspect of image manipulation
Fig. 6 shows a system able to provide appropriate manipulation of addresses
Fig. 7 shows address interpolation techniques for the system corresponding to a second aspect of the present invention.
Fig. 8 shows a configuration for address interpolation, for processing spatial manipulation
Fig. 9 shows a plot for spatial interpolation and temporal interpolation of addresses.

 Fig. 1 shows a basic embodiment corresponding to one aspect of the invention. A processor 10 receives the incoming image information along with the information previously recorded in the image memory 11.

 The address x, y accessed from the image memory, and designating a given point of the image, is determined by the output of the addressing device 12. In addition, a control parameter Z is provided by the addressing device for controlling the processing within the processor 10.

The arrangement represents a radical departure from the known systems because, in reality, the addressing device defines the form of the front-to-front image produced by a process which establishes an image by accessing certain locations in the memory of the memory. image more than once inside the frame period, so that it is actually made sure that all the points of the original image alllen, somewhere even if their locations differ from their original locations. picture elements
In addition, the addressing mechanism produces the control parameter so that it is certain that correct fractions of the image points are added to the image memory.

The processing and addressing device will now be described in more detail. The addressing and recording device is more complicated than it appears at first sight, since a system has been devised whereby the points of the image can be considered as part of a grid of cells and that these image points do not necessarily have to be assigned to a single cell, but may have parts assigned to a certain number of cells as shown in FIG. 2 Thus a normal image (without processing), constituted by several image points, would be recorded in successive cells of the image memory, as represented by the image points P2, P3 and P4 of FIG. 2 (a), and the addressing device 12 can be considered to produce a normal addressing sequence, the value of Z
being fixed, typically, equal to the property. Although only the picture elements P1 to P4 are shown, it is clear that, with this mode of operation, all the cells of the picture memory would contain a picture element. .

 The representation of FIG. 2 (b) shows the change of points in the image, an image (always of normal dimensions) is moved horizontally and vertically by half a point of image. For simplicity, only P1 and P2 are represented. The picture elements P1 and P2 can now be considered as each having 4 parts allocated to neighboring memory cells.

In practice, the part of a given picture element that is added to a cell is known from the x and y address provided by the addressing device 12, which is constructed to produce a main address and a remainder, giving the part assigned to a given cell and including the parameter Z.

Thus, for FIG. 2 (b), the image memory 11 and the processor 10 controlled by the addressing device 12 initially receive the image element P1 and, after processing, partially attribute it to the images. cells C1 and C2 and the appropriate cells on the next line, Cq and Cr The picture element P2 is then processed and placed in C2, C3, Cr and Cs.In practice, the
This process takes into account the information already allocated from the picture element P1 in the cell C2, for example in such a way that this cell location is selected for a read operation followed by the dependent processing. Z value supplied, and then the processed output signal is written into the memory.

 In practice, when the rerouting takes place without changing the dimensions of the image (zoom), the parts of the still image elements allocated to a cell always add up to 1 at the end of the processing.

In the case illustrated in FIG. 2 (b), four operations
reading, processing and writing will be necessary
to produce the desired image information, Z equal,
in this example, d 1A.

 Fig. 3 shows an embodiment of the processor 10 suitable for providing the necessary manipulation of the base image.

 A multiplier 15 receives the incoming information and, after multiplication, it transmits it to a summator 16. The value of Z is always chosen between 0 and 1.

 In the example of FIG. 2 (a) above, as already explained, the value of Z can be considered as 1, and in the arrangement of FIG. 2 (b), it will be 1/4, since three quarters of the relevant picture elements are used to produce the information inside cell C2. Thus, provided that the contents of the memory are reset to zero at the beginning of each image, the interpolation for producing the information for each cell is automatically performed simply by the succession of the operations of the recording-processing-recording.

However, this mechanism is only suitable for shifting the image as it is. If there is a change in the dimensions of the image, further manipulation is necessary to avoid errors in the constitution of the image, as will now be explained with reference to FIG. 2 (c). A halving of the dimensions of the image is represented (without offset), so that the picture element P1 is inside the cell C1 and P2 is partly inside the cells C1 and C2. Similarly, P3 is entirely inside the cell C2 and P4 is partially inside C2 and 6. If we did not proceed now to the adaptation of the quantity of data, the informrtions The result would be twice as much as C2 (for example, the intensity of the image). It is therefore necessary to provide
the means to adapt to this situation, and fig. 2 (c) shows that the adaptation coefficient (K) must be
1/2 to provide the desired adaptation to each cell.

 Thus, although it is a simple case, the general rule is really consistent with this explanation of the fact that K is the reduction ratio. We have successfully achieved reduction ratios of 32. Although K can be considered fixed for a given reduction (for example K z 3 for a reduction in a ratio of 3), it is not necessary that the reduction be the same for the whole of the image and in fact, the variable reduction gives place to a large number of special effects that can be achieved with this system.

Although the mechanism of the following operations
(reading - adding a new image point
manipulated - record) in a single cycle may initially seem simple, it is, in fact, a very powerful tool that performs interpolation and filtering in a single operation or a sequence of operations without additional sophisticated apparatus is needed.

 Considering fig. 2 (d), it can be seen that the reduction and the offset can be achieved by moving the addressing of a half-picture element (for simplicity, only P1 and P2 are shown).

 Although fig. 3 shows the basic mechanism in question, it has been somewhat simplified, and FIG.

4 shows a more complete system for providing the desired treatment; we see how the fractional part of the address and the density compensation discussed above are used. There is now a multiplier 20 to give the density compensation.

 As shown in fig. 2 (b), an image element may be manipulated in such a way that four portions are allocated to each of four neighboring cells.

In order to be able to perform this operation at reasonable speeds, it is necessary in a typical case to add additional processing and memory to the mechanism of FIG. 3, where the four points should be calculated sequentially during an input picture element. The multiplier, the adder and the separate image memory of FIG. 3 have been replaced by four picture memories 34 to 37, each provided with its multipliers 30 to 33 and its associated adders 16 to 19, respectively. The output signals from the image memories are received by the summation stage 38 to produce the combined output signal. Such a system allows the resulting image element to be available for each of the four recording cells that this concerns and for their corresponding treatment. LB addressing mechanism 12 is now represented as producing the x, y prlnciptal address for the four respective image memories (A, B, C and D) and, furthermore, the fractional part (Z) of the address (a, b, c and d) and the density compensation coefficient (K). The main picture for the picture element P1, for any of the situations shown, will be A = C1, B = C2,
C = Cq and D = Cr. The fractions vary. Thus, for fig. 2 (a), a = 1 and bt c and d = 0, K = 1.

 For fig. 2 (b), when it is P1, the fractional addresses a, b, c and d are 1/4, and K = 1.

Any combination of these portions is always equal to 1 due to the presence of summation stage 38.

 For the situation of Fig. 2 (c), for the picture element P1, we have aaa and b, c and d = O and K = 1/2 for the picture element P2, A, B, C and D are as above but a and b are 1/2 and c and b are zero with R 5 1/2.

 It should be remembered that each of memories 34 to 37 is a full frame memory. Therefore, when something is registered in the system, the addresses always express four different but adjacent cells but, on reading what is in the system, the address of each of the image memories is the same. In other words, for treatment, you have to access four cells, but when you read, you have to access a single cell.

The presence of the multiplier 20 effectively reduces
the volume of incoming data, which is necessary when a reduction is made because, otherwise, an accumulation of contributions from many image points in a cell would result in too much information density.

 For special effects, the compression is not the same for each cell inside the frame.

 For the sake of clarity, the multiplier 20 has been shown separated from the multipliers 30-33, but in practice the multiplier 20 could, in a typical arrangement, be incorporated in the dividers 30, 31, 32 and 33.

 Another special effect will now be decried to illustrate the flexibility of the system. Fig. 5 shows an effect equivalent to turning page P.

The only fact of producing the "shape" that one wants allows to carry out the correct succession of addresses as well as the correction for the establishment of the image. Thus, at the edge E of the page P, there will be a greater accumulation (but it is compensated by the multsplier 20) than in the part which overlaps B.

 In practice, it will be apparent that the flap F is transparent, so that the information relating to the image below is also visible.

 If it is desired to make the flap opaque, so that the image below is not visible, this can be achieved by the read-replace-record operation cycle, which can be achieved simply by removing the connection between the output of the image memory 91 and the adder 14, in the configuration of FIG. 3. In a typical case, it is convenient to produce an identification "index" through the addressing device, so that the system knows which zone is above the other.

 Fig. 6 shows in more detail how the addressing mechanism 12 can work for any desired shape.

The above examples show that the addressing sequence chosen by the user defeats
the shape and dimensions of the output image and also compensates for the accumulated information by providing x, y, z, and K parameters.

 The simple forms of fig. 2 can easily be generated by the keyboard 21 for introduction into the computer 201 so as to provide the sequence of desired cell address locations to be accessed, as well as to introduce the necessary value of Z and K .

 Thus, the grid of the image memory cells may or may not be within the boundaries of the shape of the desired image; when this is the case, these addresses are selected during manipulation.

 Alternatively, standard mathematical formulas can be introduced to produce the desired shapes in the calculator 20. In the case of a circle, for example, the normal equation of the manuals for the circle is introduced, and simply by defining the address from the cell of its center and the radius of the circle, it is then possible to determine if a certain cell address is, or not, inside the circle, and this defines the shape of the image which results from it.

The desired shape area is also an indication of the reduction ratio and this can therefore also be calculated to determine the value of K. The value of the reduction (K) for a given area of the image can be determined, for example, using standard surface calculation techniques (see pp. 129-131 in the Hewlett manual
Packard UP 25 of 1975), K being proportional to the area.

 The calculated values of x and y are then passed to the disk memory 23, together with the appropriate value of K for that cell and in a given form.

In practice, disk 23 contains a variety of shapes, including shape suites to allow
the transformation of images from one form to another. A
Once forms have been introduced, the calculwr 20
is no longer necessary, and the system uses only the
disk memory 23 as a source of data on the forms.

Although disk access is much faster than accessing the computer, it is usually not fast enough to cope with video addressing rates. In order to overcome this problem, an additional device represented by the address interpolator 24, which operates as illustrated in FIG. 7. In practice, the disk memory contains only approximate data on the cell addresses, as shown by the points K, L, M,
N, K and L typically represent the first and eighth successive addresses of picture elements horizontally and M and N the equivalent address points, eight lines down. The Q, R, S and T points are, in a typical case, the equivalent address points eight frames further. Thus, updating the addressing at this rate can be performed by the disk and the addresses located between the available points are interpolated from them, both spatially and temporally, as shown in the figure.

It has been revealed that this technique does not give any noticeable degradation of the produced image.

 Although the computer 20 has been described as providing all the values of x, y, Z and K when only the approximate addresses are provided to the disk 23, it may be appropriate to provide only approximate values correspondingly for the others. settings ; in this case, these are also interpolated to obtain all the desired information. Alternatively, the parameters can be calculated by following the address interpolating process in interpolator 24, using the calculation discussed above.

 The address interpolation technique that has been described also works when the disk produces a series of effects and, while the change in addressing is produced by the disk and updated every eight frames (in this example ), the interpolation of addresses produces a progressive change! on the huilt frames by giving more importance to the neighboring frame than to the distant frame.

 Fig. 8 shows an arrangement for producing the spatial address interpolation. The approximate addresses arrive at the address delay circuit 41, which gives a delay equivalent to eight address lines. The delayed address is transmitted to the multiplier 42 and the approximate address of the moment is transmitted to the multiplier 43 before addition in the adder 44. The output signal of the adder is transmitted to another delay circuit 45 whose delay is equivalent to eight picture point addresses, and this delayed output signal is transmitted to the multiplier 46. The non-delayed output signal of the adder 44 is transmitted to the multiplier 47 before being received by the adder 48, which also receives the output signal of the multiplier 47. multiplier 46.

In practice, the assembly of FIG. 8 is double to give the necessary interpolation for x address and yo address
Thus, from fig. 7, when the approximate addresses K,, L, M, g are available, any other interpolated address, for example the address W, can be determined from them. The values of k and 1 vary between Q and 1, from typically, in steps del / 8, when the addresses are calculated. These values, for the multipliers, can be conveniently provided by look-up tables attacked step by step by the addressing clocks.

The spatial address interpolator is included in the arrangement of Fig. 9 for producing the time interpolation. For simplicity of explanation, the output of the disk memory 23 is shown as being provided by a first-form memory 23A (for example, containing the addresses K, L, M, M in Fig. 7).
and a memory 233 of second form (containing the va
their Q, R, S,) 4 After spatial interpolation, the
Address values are available for time interpolation using the multipliers 52 and 53. The resulting output signals are available through the adder 54. The values of t> also vary between 0 and 1 in increments. of 1/8 for this it is convenient to use a table to consult 55th This allows the gradual introduction of any change in the form of the address between the eight periods of frame.

 The system has been described as having buffered addresses operating about eight addresses and eight frames, but this value is not imperative.

 In practice, although the system has been generally described with respect to manipulation intensity values for video information, when manipulating color data, this system could be, in a typical case, tripled, so that one of the parties processes the luminance data and the other the chrominance data (for example the color difference).

In the NTSC system, this is coded as respectively Y, I and Q information. This makes it necessary that, although a relatively large number of image memories are required, the results obtained justify such a configuration. .

 Alternatively, the color can be processed on the basis of red-green-blue.

 Although the system has been described for use with special effects in television broadcasts, it can be used for other types of video systems requiring the manipulation of the image in a completely free form after their production.

Claims (10)

 REVENDaCATIONS  address interpolation means (24) for calculating all the desired addresses to be selected from available address data in the spatial and temporal modes, so that all addresses in front of selected ones are available, up to date, at normal frame rates.  means (23) for updating the selected addresses among the desired addresses, at a slower rate than the normal frame rate, and  means (20) for determining only the selected addresses from the desired scene memory addresses which it is necessary to select,  1> Addressing device for an image memory processing system, characterized in that it comprises  2. Device according to claim 1, characterized in that the aforementioned determining means comprise a memory (23) for storing at least one addressing sequence.  3. Device according to claim 2, characterized in that the updating means mentioned are designed to select different parts of the memory mentioned.  4. Device according to claim 3, characterized in that the mentioned memory and the aforementioned updating means are provided by a mobile recording medium (23) containing only the mentioned mentioned addresses of image memories from selected frames. .  5. Device according to any one of claims i to 4, characterized in that there are generating means (20 to 22) for determining the desired addressing sequences before reception by the mentioned memory.  6. Device according to any one of claims 1 to 5, characterized in that the address interpolation means mentioned include  a first spatial address interpolator (40) for determining all desired addresses from the available information associated with a first frame,  a second spatial address interpolator (40) for delivering all desired addresses from the available information associated with the next available frame, and  a time address interpolator (52-54) for outputting the desired addresses associated with intermediate frames from information provided by the first and second spatial address interpolators mentioned.  Apparatus according to claim 6, characterized in that each of said spatial address interpolators comprises an arithmetic processor (42 to 44; 46 to 48) for variably providing synthesized addresses according to their spatial relationship with the address information that is available.  8. Device according to claim 7, characterized in that the interpolator mentioned time addresses comprises an arithmetic processor (52 to 54) for variably providing synthesized information addresses, depending on their temporal relationship with the information on the addresses that are available, the addresses included in a frame being modified during intermediate frame periods to effect a progressive change from frame to frame.  9. Device according to one of claims 7 and 8, characterized in that an arithmetic information generator (55) variably controls the desired synthesis, on a time basis.  10. A method of providing addresses to an image memory processing system, characterized in that it comprises the following steps  supplying the selected addresses only from among the desired image memory addresses which it is necessary to select,  updating the selected addresses among the desired addresses at a slower rate than the normal frame rate,  estimating all the desired addresses to be selected by interpolating available address information, in the spatial and temporal modes, so that all addresses to be selected are available, updated at normal frame rates.