FR2526612A1 - Digital energy level measuring circuit for signal transmission system - has transcoding, squaring and memory circuits, esp. for echo canceller - Google Patents

Abstract

The digital energy level measuring circuit is preceded by a transcoding circuit providing signals in linear digital form, from compressed coded digital signals. The energy level measuring circuit includes a squaring circuit connected to the first input of a multiplier-accumulator circuit. The second input of this circuit is connected to the output of a permanent memory containing attenuation coefficients. The output of the multiplier-accumulator circuit is connected to an active memory and to a register comprising bistable flip-flops. The output of this register is connected to a circuit transcoding into energy levels. The active memory is also connected via an interface to the first input of the multiplier -accumulator circuit.

Description

DIGITAL DEVICE FOR MEASURING ENERGY LEVELS
ESPECIALLY FOR ECRO CANCELLER
The present invention relates to a digital device for measuring energy levels, in particular for an echo canceller.

 Known from US Pat. No. 4,129,753 is an energy measurement device (400) for an echo canceller comprising two square risers followed by a summator which is itself followed by a delay cell.

This known device does not allow the energy of the incident signals to be measured with good resolution and is not intended to operate in timeshare on a large number of channels. In addition, the measurement results act all or nothing on the convergence speed of the echo canceller, and if at least one of the samples of the incident signal is false, the convergence time may be greatly increased .

 The present invention relates to a digital device for measuring energy levels having a high resolution and which can calculate very quickly to allow time-sharing operation on a large number of channels.

 The present invention also relates to a device for measuring energy levels in the device controlling the speed of convergence of an echo canceller.

 The measuring device according to the present invention is preceded, where appropriate, by a transcoding circuit supplying signals in linear digital form from digital signals coded in compressed code, for example, and comprises a circuit for elevation at square connected to a first input of a multiplier circuit. accumulator whose second input is connected to the output of a read-only memory containing attenuation coefficients, the output of the multiplier-accumulator circuit being connected to a random access memory and to a register with flip-flops whose output is connected, if necessary, to a circuit for transcoding into values of energy levels, said random access memory being moreover connected, by means of an interface device to said first input of the multiplier-accumulator circuit. When the multiplier-accumulator circuit is a circuit with two series of m input terminals, and the measurement results are presented on an output bus with n wires, n being greater than, but less than or equal to 2m, the device interface comprises a circuit with m three-state gates whose inputs are connected to the m most significant output terminals of the multiplier-accumulator circuit, and whose outputs are connected to a series of m corresponding input terminals of the multiplier- accumulator, this circuit with doors being in parallel with a register comprising m cells whose least significant cells (p = n - m) have their inputs connected to the e output terminals of weight immediately lower than said high weights of the output terminals already used of the multiplier-accumulator, the remaining cells, if n is less than 2m, of the register being forced to zero, and the m + p output terminals used of the multiplier-accumulator being on the other hand connected to n = m + p corresponding wires from said output bus.

 The transcoding circuit comprises several read-only transcoding memories connected - respectively to the most significant wires of the output bus, to the most significant wires of this bus, and to the least significant wires of this bus, the outputs of these memories dead memories being connected in parallel, the inputs CS and / or a ("Chip Select") of these memories being connected to a discrimination circuit with two dead memories or with two OR circuits, the inputs of which are respectively connected to weight wires strong and to middleweight wires of said output bus, so as to inhibit two of the three transcoding memories.

 The present invention will be better understood on reading the detailed description of an embodiment taken as a nonlimiting example and illustrated by the appended drawing, in which: - Figure I is a simplified block diagram of a canceller of echo comprising a measuring device according to the invention; - Figure 2 is a block diagram of a preferred embodiment of the measurement device of Figure 1, and - Figure 3 is a block diagram of a preferred embodiment of the circuit of transcoding into values of levels of the device in Figure 2.

 FIG. 1 shows the simplified block diagram of an echo canceller comprising the measuring device of the invention. It is however understood that this measuring device can be plugged in differently in the echo canceller, or can be used in another type of echo canceller, or else can be used in another device in which one or more digital signals must be produced representing the energies of one or more signals.

The echo canceller shown in Figure 1 is of the type described in the article by DLDUTTWEILER published in "IEEE Transactions on
Communications ", Vol. COM-26 nO 9 of May 1978, with however some modifications which will appear on reading the description below.

 The echo canceller 1 shown in FIG. 1 is designed to operate in timeshare on thirty-two channels for example, but to simplify the drawing and the explanations, we will only describe here the processing of a single channel, being it is understood that for time-sharing processing on several channels, memories and registers of corresponding capacity are provided. The echo canceller 1 cooperates, on the one hand with a signal transmission device (not shown), such as a cable or satellite transmission system possibly associated with a switch, and on the other hand with a 2-wire / 4-wire hybrid (not shown) to which a subscriber called "close subscriber" is connected.

The signal transmission device is connected to terminals 2 and 3, and the hybrid is connected to terminals 4 and 5. The signal arriving at terminal 2 from a distant subscriber via said transmission system will be called later "incident signal". The samples on terminals 2, 5 and 3 are respectively denoted X Xn, yin, and ERn
Terminal 2 is connected to a delay line device 6 in which N successive samples of the incident signal can flow, the number N defining the order of the digital filter from which the echo canceller 1 is made. The device 6 is preferably a random access memory, this memory then being connected, in a manner known per se, to an address counter (not shown). The output of the device 6 is connected both to a convolver 7 and to a first input of a correlator 8. The output of the convolver 7 is connected to a first input of a subtractor 10, the other input of which is connected to the terminal 9. The output of subtractor 10 is connected to terminal 3 and to the input of a measuring device 12. Terminal 2 and terminal 5 are also connected to the input of measuring device 12 whose output is connected to the input of the device 9 responsible for carrying out the detection of double talk and for adjusting the control of the coefficients of the digital filter.

 The operating principle of the echo canceller is well known per se, and will not be described here. It will only be specified that, unlike the echo canceller known from the aforementioned article, that of the present invention does not operate in floating point because it uses in the convolver a fixed point multiplier, for example the multiplieraccumulator TRW n0 TDC 10105, the quadratic integrator, described below with reference to Figure 5 also works in fixed point.

 In the case where the device 6 is, as specified above, a random access memory, the shifting of the different successive samples of the incident signal is done fictitiously by permuting the addressing of this memory, as indicated for example in the request French Patent No. 79 21 769. If it is desired that the digital filter of the echo canceller be of high order, it is possible to use, for device 6, several random access memories connected in cascade, each of these memories vives being associated with a convolver and a correlator, as indicated for example in the above-mentioned French patent application.

 We will now describe in detail, with reference to FIG. 5, the measurement device 12. The terminals 2, 3 and 5 are connected, inside this device 12, by a multiplexer 11, to the addressing inputs of one or more square elevation read only memories 13, the number of these read only memories depending on the capacity of the memories used and on the width of the digital words processed. In the present example, two memories are used in parallel, thus presenting sixteen outputs. The outputs of the memories 13 are connected, by a bus 14, to one of the two inputs, referenced 15A, of a multiplier-accumulator 15, which is in the present example the integrated circuit TDC 10105 of TRW. The other input , referenced 15B, of the multiplier-accumulator 15 is connected by a bus 16 to the outputs of a set of read-only memories 17 in which are attenuation coefficients memorized making it possible to carry out an integration of levels of incident signals as explained below. below. In the present example, the set of memories 17 comprises two read only memories connected in parallel and thus having sixteen outputs. The outputs of the memories 17 are connected to the other input of the multiplier-accumulator 15.

 The outputs of the multiplier-accumulator 15 are connected by a bus 18 to a random access memory 19 and to a register 20. The random access memory 19 is on the other hand connected, by the bus 18, and via an interfacing device 21, to the bus 14. In the present example, the device 21 comprises a set 22 of sixteen doors with three states connected to the sixteen most significant wires of the bus 18, and a register 23 with sixteen cells of which the eight most significant cells are forced to zero and the inputs of the other eight cells of which are connected to the eight least significant wires of the bus 18, the sixteen outputs of the register 23 being connected to the bus 14.

Still in the present embodiment, said circuit
TDC 10105 has two outputs 15C and 15D which correspond respectively to the sixteen most significant binary elements and to the sixteen least significant binary elements of the multiplication-accumulation result. The sixteen terminals of the output 15C are connected to the sixteen most significant wires of the bus 18 with twenty-four wires, while the output 15D is connected, internally to the circuit, as symbolized by the broken line 24, at the input 15B, and therefore to bus 16 which has sixteen sons. Of course, the results appearing on the output 15D are multiplexed in a manner known per se with the coefficients coming from the memories 17. The eight most significant wires of the bus 16 are connected via a set 25 of eight three-state doors to the eight wires of low weight of the bus 18. However, it is understood that if there were a multiplier-accumulator with twenty-four outputs accessible from the outside, the device 21 would comprise only a set of twenty-four doors with three states, The set 25 of doors would be deleted, the operation of the device 12 would be simplified by the same amount, and the memories 17 should no longer contain more than two kinds of coefficients, as will appear on reading the explanations below. Likewise, if we were content with a lower resolution for the measurement result, using at most only the sixteen most significant outputs of circuit 15, the bus 18 could be with sixteen wires, and we could delete items 23 and 2 5.

 The outputs of register 20 are connected by a bus 26 to a circuit 27 for transcoding into energy level values, the output of which is referenced 28.

 There is shown in Figure 3 a preferred embodiment of the circuit 27. In this Figure 3, there is shown by a rectangle 29 the arrival of the bus 26 at the entrance of the circuit 27. This rectangle 29 symbolizes the row of weights bus 26 wires, taken in descending order from left to right. In the present example, the bus 26 has twenty-four wires (of weight 20 to 223). The ten least significant wires (20 to 29)) are connected to the addressing inputs of a low level coding read-only memory 30.

Eleven medium-weight wires (for example from 26 to 216) are connected to the addressing inputs of a read-memory memory -31 for coding of medium levels, and the eleven most significant wires (213 to 223) are connected to the addressing inputs of a high level coding memory 32.

In addition, seven wires of highest weight (217 to 223) are connected to a circuit 33 with OR function, and the seven wires of immediately lower weight (210 to 216) are connected to a circuit 34 with OR function. The output of circuit 33 is connected to the input CS ("Chip Select" or validatiorss of memory 32 and to inputs C2; (inhibition> of memories 31 and 30. The output of circuit 34 is connected to input CS of memory 31 and at the input> of memory 30. The above circuits with an OR function can be read only memories.

 The outputs of memories 30, 31 and 32 are connected to output 28 by a common bus 35 comprising, in the present example, eight wires.

 We will now explain the operation of the preferred embodiment of the measurement device described above, the operation of the echo canceller being known per se, will only be recalled insofar as it depends on the operation of the measurement device. .

 The three samples Xn, Yn and ERn of coded digital signal, in code compressed on eight binary elements in the present example, occur at the rate of the MIC frames, every 3.9 microseconds. The memories 13 ensure both the decompression of the input samples and their square elevation. In the present example, taking into account the quantization half-step during the decompression of the signals, we present the results of elevation squared on twenty-four binary elements. The samples Xn, Yn and ER n of the same channel will be processed successively in the measurement device 12. The sample Xn, for example, occurring at time tn is squared by the circuit 13.The output of circuit 13, presents, for a first memory page, the sixteen most significant bits of the result, and for a second memory page the eight least significant bits preceded by eight zeros. The sixteen most significant binary elements of the word Xn produced at the output of the memories 13 are sent to the corresponding input register (connected to the input 15A) of the circuit 15, The other input register (connected to the input 15B) of the circuit 15 receiving memories 17 addressed in a manner known per se, under the control of a sequencer (not shown), the coefficient 2 c (for the most significant), the value and meaning of which are given below .

 As soon as the circuit 15 receives from said sequencer a suitable clock signal, it performs the mutual multiplication of the two words written in its two input registers, and sends them to its accumulator. The least significant part of the word Y2 n is then presented at the input 15A of the circuit 15, The input 15B receiving memories 17 the coefficient 2-c (least significant). The result of this second multiplication is added to the previous one and stored again in the accumulator of the circuit 15. Then, said sequencer controls the addressing reading of the random access memories 19 to read the previous measurement result coming from the circuit 15 and relative to the previous one incident signal. Of course, if the instant tn is the initial instant, that is to say the instant when the first sample of the incident signal arrives, the content of the memories 19 is zero or made such. The word read in the memories 19 has twenty-four binary elements; the sixteen most significant binary elements pass through the gates 22 made passable by said sequencer and arrive at the corresponding input register of the circuit 15, while the other eight binary elements are registered in the register 23. This register 23 has sixteen cells, said eight other binary elements are written in the eight least significant cells, while the other eight cells are forced to zero. Circuit 15 receives, at the same time as said sixteen most significant binary elements coming from memories 19 , a coefficient (1-2-C) of the memories 17. Another next clock signal controls the reading of the input registers of the circuit 15 and therefore the mutual multiplication of their respective contents which are immediately sent to its accumulator to be added to the previous multiplication result. A next clock signal is sent to register 23 which sends its content (sixteen binary elements of which the eight most significant are nt null) to the corresponding register of the multiplier-accumulator 15 which receives in its other input register, from the memories 17, the aforementioned coefficient (1-2 c). On the next clock signal, the circuit 15 performs the mutual multiplication of the contents of its input registers and sends the result to its accumulator, this result being added to the result obtained previously and kept in the accumulator of the circuit 15. At a following clock signal, the content of said accumulator is sent on the bus 18, in particular to the memories 19 and to the register 20 which memorize this content at a following clock signal. Said content memorized in the memories 19 will be processed, as described above, as a "previous result" during the processing of the sample arriving at the tilloning echo instant tn + l immediately after the instant tn, while the content stored in the register 20 is then converted by memories 27 to supply a value, for example in dBmO, on terminal 28.

 The formats of the words involved in the four multiplications carried out by the circuit 15 can vary according to the applications, but the four multiplication results must be framed according to the same format, that is to say that they must be consistent with each other in order to allow successive accumulations in the accumulator of circuit 15.

 We will describe below, by way of example, a format that can be used in the case of application to an echo canceller.

 The numbers presented, on the bus 14, at the input 15A with sixteen binary elements of the circuit 15, comprise sixteen binary elements. The result of the mutual multiplication of two numbers of sixteen binary elements each has a maximum of thirty-two binary elements.

Since the bus 18 is only provided for twenty-four binary elements, the eight least significant binary elements of the result of the multiplication are neglected. It is for this reason that among the sixteen wires of bus 16 (wires connected to both input 15B and output 15D), only the eight most significant wires are connected via the set of doors 25 to the eight least significant wires of bus 18. In the present example, the twenty-four wires of bus 18 are assigned weights 20 to 223 respectively.

We assign to the binary elements of Xn2 of most significant (produced on page 1 of the memories 13) the weights 8 to 23 respectively, and to the binary elements of X2n of least significant the weights 0 to 15. Consequently the coefficient 2-c will be shown on the format (2 6, 2-1) for the first product and on the format (2-8, 27) for the second product. So the result
2 c of these two multiplications Xn 2-c may have values limited to 2-8 in low weight and 223 in high weight. The result of these two multiplications is stored in the accumulator of circuit 15.

 The previous energy measurement result temporarily stored in memories 19, and relating to the previous incident signal Xn-1 (at the time of processing of xn), is defined on twenty-four binary elements. Let be in 1 and in-1 the respective values of the part represented by the sixteen most significant binary elements and by the part represented by the eight least significant binary elements of this preceding result which is delimited by 20 and 223 by assumption.

 During the third multiplication performed by circuit 15, the value E> 1 is multiplied by (1-2-C). The value of En 1 is delimited by 28 and 223, and the value of (1-2-C) is delimited, just like that of by par 21 and 2-16. Consequently, the result of this third multiplication is delimited by 2 8 and 223. The result of this third multiplication can therefore be added to the result of the first two multiplications in circuit 15.

During the fourth multiplication carried out by circuit 15, the value in 1 limited by 2 and 27, to which circuit 23 adds eight null binary elements going from 28 to 215 (which makes a total of sixteen binary elements from 20 to 215 is multiplied by (1-2 c). However, to obtain the same limits as above for the multiplication result (in order to be able to add this fourth result to the first three), it is necessary to change the limits of the coefficient (1-2- C) .The lower limit of this coefficient must be 2-8 so that the lower limit of the result remains 2 8 This limitation is not excessive, because it leads to the suppression of the result values ranging from 2-9 to 2-16 which can actually be considered negligible. Consequently, the values of (1-2C) used for the fourth multiplication range from 2-1 to 2-8 only and are presented on the eight least significant outputs of memories 17, whereas these same values used for the third multiplication are presented on the eight other most significant outputs of the memories 17. In addition, for the fourth multiplication, one naturally presents 11011 on the eight most significant outputs of the memories 17 since, by hypothesis, the values where 2-c is between 2- and 2-8, (1-2-C) is always less than 1.Finally, the fourth multiplication result is added, in circuit 15, to the sum of the first two, and the end result, namely;
x2n. 2-C + E2 (1-2C) + e (1-2-c)
n-1 n-1 is sent, on the bus 18, to memories 19 and to register 20. This final result is limited by 20 and 223, that is to say that the eight least significant outputs (2 -1 to 2-8) of circuit 15 are not taken into account.

 In the example described above, the format (223, 20) chosen to represent energy allows level measurements between + 3.14 dBmO and -66 dBmO.

2
However, in another example, we can choose for the term xn the limits (219, 20), that is to say that any value of x2 greater than n (220-20) is replaced by this same maximum value, which is easy to achieve since the squared elevation of xn is performed by read only memories. In this case, the format of the energy still represented on twenty-four binary elements is (219, 2-4). The coding range is then between -6 dBmO and -78 dBmO, knowing that level 6 dssmO represents a signal level greater than or equal to -6 dssmO and that level -78 dBm0 a level less than or equal to - 78 dBmO.

 The coefficient 2-c is determined experimentally to ensure a compromise between an integration over a sufficiently long period of the energy of the measured signal and an adaptation sufficiently faithful to the variations in level of this signal.

If xn, Xn + 1, xn + I, n + 2 ... are called the different successive samples of the incident signal, the device 12 successively supplies the input of the register 20 with the following values, assuming that the content of the memory 19 is zero on the arrival of xn: - on the arrival of x x2 2-cnn - on the arrival of xn + 1: x2. 2-c. (1-2-c + x2 2-c - upon arrival of xn + 2: xn2. 2-c (1-2-c) 2 + x2 2-c (1-2-C) + xn + 1 . 2-C
Xn + l
etc ...

 We therefore see that as new samples arrive, the value (xn. 2 c) representative of the instantaneous power of the incident signal at the arrival of sample xn, is more and more attenuated whereas the value (x2n. 2-c) corresponding to the most recent samples of rank m, is little attenuated. Indeed, even if the number 2-c is small (for example 2-5), the expression (1 -2-C), which multiplies the value (xn. 2-c), and which is raised to the power (ml) at the arrival of the sample xn + m, is worth approximately 0.5 for m = 23 and about 0.1 for m = 73 (for c = 5). Consequently, at a given instant, a few milliseconds after the arrival of the first sample, the device 12 supplies to the input of the register 20 a signal representing the "updated" integral of the energy of the incident signal. energy is an updated integral due to the fact that all the samples of the incident signal constantly circulate in the accumulator of circuit 15, but are attenuated at each turn, the oldest being the most attenuated, and the fact that the result takes account of it fairly quickly abrupt and strong variation of the incident signal.

 Indeed, if from a first sample and for a hundred samples for example (that is to say for 12.5 ms at a sampling frequency of 8 kHz) the level of the incident signal has a value v, the value of the signal on terminal 20 tends towards v, and if suddenly in the 101st sample the level of the incident signal goes to the value nv to maintain it, we collect at the input of register 20 a signal of value v2 + 1 / 32 (n2v2) approximately at the arrival of the 102nd sample, and the value of this signal tends towards n2v2 if the level of the incident signal is maintained at the value nv for a hundred samples or more. quickly returns (for example after a few samples) to the value v, the value of the signal level at the input of the register 20 also quickly returns to v2. We therefore have an integration of the incident signal.

 In the coding device of FIG. 3, the three memories 30 to 32 ensure the actual coding, while the two memories 33 and 34 select one of the first three memories according to the level to be coded. The content of memories 30 to 32 depends on the chosen coding pitch and on the representation of the coded numbers.

 In an exemplary embodiment, the memories 30 to 34 have a capacity of 2k bytes, and the coding results (energy levels) are represented by a word of eight binary elements. Consequently, 256 coded values are therefore possible ("00" to "FF" in hexadecimal notation).

In said exemplary embodiment, the coding pitch being 0.25 dB, the coding range goes from -6 dBmO to -69.75 dBmO. It will be noted that for the weak levels, the coding pitch is increased as a function of the number of significant bits representing the energy in linear coding,
Thus, from -60 dBmO for example, the step progressively increases from 0.25 dB to 3 dB for the difference between the last two coded values. The level -6 dBmO, coded "FF" in hexadecimal, therefore represents all the levels greater than or equal to this value, while the level -69.75 dBmO, coded "00" represents all the levels less than or equal to this value. This unsigned representation of the coded levels was chosen because all the levels are negative and it makes it possible to use all the 256 possible coding values.

 Finally, it will be noted that the two read only memories 33 and 34 fulfill the function of an OR gate with seven inputs in the aforementioned example.

Claims (4)

 l.Digital device for measuring energy levels, in particular for an echo canceller, preceded, if necessary, by a transcoding circuit supplying signals in linear digital form from digital signals coded in compressed code for example , characterized by the fact that it includes a square elevation circuit (13) connected to a first input (1SA) of a multiplier-accumulator circuit (15) whose second input (1su) is connected to the output d '' a read-only memory (17> containing attenuation coefficients, the output of the multiplier-accumulator circuit being connected to a random access memory (19) and to a flip-flop register (20) whose output is connected, if necessary, to a transcoding circuit (27) into energy level values, said random access memory being also connected, by means of an interface device (21) there said first input of the multiplieraccumulator circuit.  2. Device according to claim 1, in which the multiplier-accumulator circuit is a circuit with two series of m input terminals, and in which the measurement results are presented on an output bus with n wires (18), n being greater than m, but less than or equal to 2m, characterized in that the interfacing device (21) comprises a circuit with m doors with three states (22) whose inputs are connected to the n most significant output terminals of the multiplier-accumulator circuit, and the outputs of which are connected to a series of n corresponding input terminals of the multiplier-accumulator, this gate circuit being in parallel with a register (23) comprising m cells of which the p least significant cells (p = n - m) have their inputs connected to the R output terminals of weight immediately lower than said high weights of the output terminals used of the multiplier-accumulator, the remaining cells, if n is less than 2m, of the register being forced to zero , m + p bo The output reins used of the multiplier-accumulator being on the other hand connected to the n = m + p corresponding wires of said output bus.  3. Device according to claim 2, in which the multiplieraccumulator is a TDC 10103 type circuit with twice sixteen inputs and thirty-two outputs of which twenty-four outputs are used, and of which the sixteen least significant output terminals (15D) are internally connected (24) to a series of sixteen input terminals, characterized in that the interfacing circuit, which therefore comprises sixteen three-state doors in parallel with a register with sixteen cells including the eight most significant cells are forced to zero, is connected by its output to the series of inputs (15A) of the multiplier-accumulator not connected internally to outputs of the multiplier-accumulator, and by the fact that the eight most significant input terminals of l the other series of sixteen input terminals (15B) of the multiplier accumulator are connected by an eight-door circuit with three states to the eight least significant wires of said output bus (18).  4. Device according to any one of the preceding claims, characterized in that the transcoding circuit (27) comprises several read-only transcoding memories connected respectively to the most significant wires (32) of the output bus, to the wires of average weights (31) of this bus, and to low weight wires (30) of this bus, the outputs of these read-only memories being connected in parallel (28), the inputs CS and / or CS ("Chip Select ') of these memories being connected to a discrimination circuit with two read only memories (33 and 34) or with two OR circuits, the inputs of which are respectively connected to high order wires and to medium weight wires of said output bus, so as to inhibit two of the three transcoding memories.