FR2518781A1 - DISTRIBUTED DATA PROCESSING ASSEMBLY AND TRANSMISSION CONTROLLER - Google Patents

Abstract

THE INVENTION CONCERNS DISTRIBUTED PROCESSING SETS. IT RELATES TO AN ASSEMBLY HAVING A MAIN CONTROL BODY 29 ENSURING THE TRANSFER OF DATA BETWEEN PROCESSOR MODULES 12. EACH PROCESSOR MODULE HAS A SHARED MEMORY WHICH CAN BE LOCATED IN A WINDOW OF THE ADDRESS SPACE OF THE PRINCIPAL BODY 29 ORDER. AFTER ESTABLISHMENT IN THE WINDOW, THE MAIN BODY 29 HAS ACCESS TO THE IMPLANTED SHARED MEMORY SO THAT DATA CAN BE WRITTEN IN OR READ FROM THE IMPLANTED MEMORY. APPLICATIONS TO TRANSMISSION CONDUCTORS.

Description

The present invention relates to data processing assemblies and

more precisely sets

  of data processing having several processors distributed

  tis. Data processing sets which have a single processor (often called a CPU) are limited by the size and speed of the processing set itself. data processing of a set is the addition of one or more

  processors, instead of increasing the size or -

  the speed of a single set of treatments

  often refers to "distributed treatment units"

  thus having more than one processor The distributed architecture

tie can be of different types.

  A first solution has been the coupling of

  that CPU added to the common line

  of the whole, linking the main central processing unit

  memory and I / O devices.

  A disadvantage of this solution is that each central processing unit must compete with the other central units for access to the common line for the purpose of transferring the data to the memory or any of the input devices. exit or for the

  receiving data from the memory or one of its

  Another disadvantage of this solution is that it generally increases the complexity of the software used. These two disadvantages can reduce

  the working speed of each central unit.

  can be particularly troublesome in

  real-time applications such as transmission controllers that often handle and transfer large amounts of data between

  input-output devices which can not tolerate

  significant delays in the central units, due to

  to the congestion of the common line of the whole.

  A variant of the above-mentioned architecture comprises combining, with each additional processing central unit, an input-output device intended to form a single module. Each module may comprise a transfer logic circuit with direct access to the memory. in some cases, an execution memory associated with the central unit This solution can reduce the

  disadvantages of some of the congestion problems.

  of the common line since data transfers

  be the input-output device and the central unit of

  processing of the module may take place outside the

  However, even in the case of this solution, significant delays caused by the congestion of the common line of the whole can still appear, and the programming of the central unit must tolerate these delays. addition, the addition of each

  module comprising a central unit and a device for

  treate-output, connected to the common line of the whole,

  the software complexity of the whole.

  Several different schemes of

  For example, U.S. Patent No. 3,551,894, suggests a set in which each processor has its own common line data series assuring the connection of the processor to each device to which data must be transferred Other proposals include

  the whole represented in the United States patent of

  No. 3,815,095, according to which each processor comprises a multiplexer which selectively accepts data from

  several common lines, each common line being

  In these two sets, congestion problems of the common data line are reduced since each processor has its own common line of output data connected to each destination of the data. However, physical interconnects: between the processors are relatively complicated given

  the high number of common lines In addition, this solution

  It does not lend itself to the addition of additional processors.

  because the common data line of each processor must be connected to each device with which it communicates. Another solution for improving data transfers between distributed processors has associated with each processor a shared memory (or a dual channel) through which all data transfers to other processors incorporated into the set are performed. The advantage of this architecture is that after a processor has completed the processing of a part of the data, the processed data can be placed in the shared memory for transfer to another processor The source processor is then free to move to other tasks and is not delayed by waiting for the availability of the common line for data transfer. Such a shared memory architecture is shown in US Patent No. 4,149,242. described in this patent also comprises a separate common line of data connecting each processor module to the processor module with which it must communicate. The shared memories of the processor modules can be interconnected by a single common line of the set so that the complexity of the use of

  several lines of data linking the processes

  The data transfers between shared memories can be executed by a central computer or a central data transfer set.

  coupled with the common line of the ensemble Such an archi-

  tecture is described in the United States patent of

  nc 4 181 936 and in the article "Dual Port RAM Hikes Throughput In Input / Output Control Board",

Electronics, August 1.7, 1978.

  In the assembly described in this article above, each distributed processor has an input-output section

  and a shared memory intended to form a module pro-

  All data transfers between the process.

  The shared memory is assigned a single portion of the address space of the set which is determined by all the locations addressable by the computer. central or other central data transfer set coupled to the common line of the set When data needs to be transferred

  shared memory from one processor to another, the

  central user addresses the source shared memory and reads the -data The destination shared memory is then addressed so that the data is written As each processor module appears to the whole of the same

  way that another block of memory, additional modules

  can be added to the set with a minimal effect on the common-line of the set and the software of it -However, a disadvantage of this solution is that each shared memory occupies a separate-part of the space addressing the set Thus, the number

  of modules that can be added to the common line of the

  seems to be limited by the total address space of the

  For example, if the central processor has an address space of 64k (that is, 65536 memory addressing locations) and each block in the shared memory occupies 8k (8192 slots). ) of this space, the assembly allows the use of 'only eight modules, the central processor having more space remaining for

  addressing other devices such as the central memory.

  In addition, since each shared memory has a single block of addresses, the central processor can address only one shared memory at a time. In many applications, it is desirable that data can be written

  simultaneously in multiple processors.

  The invention relates to an improved assembly

  distributed treatment allowing the implementation of a

  large number of distributed processors.

  It also concerns a perfect architecture

  shared memory in which data can be written simultaneously in one or more shared memories. It also relates to a controller of transmissions having a distributed processing architecture which

  facilitates the addition of new processor modules.

  More specifically, the invention relates to a

  appears to be distributed with several modules

  processors coupled to a common line of the set Each processor module has a shared memory and a processor that communicates with the other processor modules through the shared memory The shared memory of each processor module is coupled to the common line of the processor. together and can be reached either by the processor of the module or by a main control member also coupled to the common line of the assembly The main controller carries out the transfer of data from the shared memory of a first module processor to that of another processor module via the common line of the set The main controller transfers the data by addressing the shared memory of the original processor module (i.e. the source shared memory), by reading the data, and then by addressing the destination shared memory in order to

that the data be written there.

  All shared memories related to the common line of the set have the same address vis-à-vis the main body of control Thus, all shared memories are given the same part of the space

  addressing the main control organ, through the

  For example, the shared memories occupy the same amount of the address space of the main controller irrespective of the number of shared memories connected to the line.

common to all.

  Where a particular shared memory needs to be addressed in order for data to be read or written there, the principal controller authorizes the acceptance and

  the recognition of the address signals from the or-

  main control unit by the shared shared memory

  the other shared memories connected to the common line of the set are not allowed to recognize the address signals Before the write operation, the main controller may allow any number of memories shared to accept

  address signals and thus ensures the simultaneous writing of

  stored in any number of

  shared connected to the common line of the whole.

  Other features and advantages of the

  will become apparent from the following description,

  with reference to the accompanying drawings, in which:

  Figure 1 is a block diagram of a transmission controller according to the invention; Fig. 2 is a block diagram of a control unit of a data link of the transmission controller of Fig. 1; Fig. 3 is a block diagram of a main controller of the transmission controller of Fig. 1;

  FIG. 4 is a diagram showing the implan-

  tation of parts of two shared memories of a set

  data link control, in the window of

  shared memory of the main control organ in the

  address space of this main body; Fig. 5 is a more detailed block diagram of the parallel input-output channel and the shared memory of the data link control assembly of Fig. 2;

  FIG. 6 is a block diagram of the circuit

  baked memory selection logic of Figure 5;

  FIG. 7 is a block diagram of the circuit

  fuzzy logic of Figure 5; and FIG. 8 is a block diagram of a

251878 1

  line interface module of the communications controller

of Figure 1.

  Figure 1 shows a controller of trans-

  Missions 10 having a distributed processing archture and including a plurality of processor modules 12 which are coupled to a common line 14 of the set Each processor module has a plurality of output channels 16 which are connected to various peripheral devices such as terminals 22. with cathode ray tube and printers

  24 per line In addition, one or more primary computers

  cipals 26 can be connected to an input channel 16-

  exit. The routed controller 10 switches the data to be transferred between the various devices connected to the

  input-output channels of the controller For example the con-

  tr 81 eur 10 can play the role of a group controller-

  several cathode-ray tube terminals 22 and acts as an auxiliary processor with respect to

a main computer 26 -

  Each processor module has a data link control assembly and one or more line interface modules 18 which provide the coupling between the I / O channels 16 and the control assemblies.

  of the module 12 The link control unit 20

  data sound introduces the data transmitted by the

  input-output channels 16 of the associated modules 18 of

  line interface, performs the necessary processing and

  transmits the data to the processor module to which the

  recipient is connected (eg a printer

  24) The destination control set executes a processing

  addition of data where appropriate and trans-

  sends the data to the recipient device via

  of the appropriate interface module 18 and channels

suitable input-output.

  Each interface module 18 includes cir-

  In addition, each module 16 includes circuitry for processing the "link level" functions, which are required for the particular device or category of devices connected to the channels 16. specified by the "protocols": used by devices connected to the interface module A protocol is a set of rules or data transmission procedures observed by

  transmitter and receiver devices.

  their transmitters must observe the data transmission procedures provided for by

  transmission and reception connected to the input channels

controller output 10.

  Link level functions represent

  subset of these rules and include the establishment

  and disconnection of a link and the provision of

  in the appropriate format These link level functions

  are implemented by the interface module under

  the control of the data link control command set

  Advanced level operations of the protocols that depend on: the particular application are performed

  by the data link control unit If the

  positive recipient of data entered uses a

  protocol different from that used in the

  source, the command set can be programmed to transform the source device protocol

  in protocol of the recipient device.

  Each link control assembly 20 has

  shared memory that is accessible through the process

  the local link control unit and also by a main controller 29 which carries out the

  transfer of data blocks between sets of

  linkage When a block of data has to be transmitted

  4 rd, the link-control source assembly transmits signals to the main controller by the common line 14, thereby indicating to it that it contains data stored in its shared memory and which must be

  transferred As the description makes clear

  follows, the principal control organ

  plants a shared memory block of the link control source unit (containing the data) in a part of the address space of the main body of the

  This part of the address space of the

  Main ordering gane can be called "window of *

  shared memory "of the address space of the main body

  After determining the identity of the link control destination set, the

  The main controller also implements a block of the

  shared memory of the command recipient set in the shared memory window of the main controller, and then reads data from shared memory

  source and writes the data into the shared memory of

  recipient, each data word being transferred by the

  intermediate of the common line 14 of the set.

  Each processor module 12 also has a common line 30 of the link control assembly.

  interface module, allowing the transmission of data

  of the input and output signals and control signals between the processor module link control assembly and the interface modules associated therewith. Fig. 2 shows an exemplary data link control assembly having a set 32 of microtreatment

  which communicates with the interface modules 18 and the

  very elements of the link control assembly by an internal common line 34 An interface circuit 35

  of the link interface module constitutes a tamper circuit

  pon between the internal common line 34 and the common line

  of the control assembly and the interface module.

  The micro processing assembly 32 includes a high speed microprocessor which may be a "Zilog" microprocessor

  Z 80 A for example, described in the brochure "Z 8 OA CPU Tech-

  nical Manual "Microprocessor assembly 32 also includes a buffer circuit for the data lines,

  address and command of the internal common line 34.

  The set 32 microtreatment, under the

  the program stored in a passive memory 36 and a local random access memory 38, reads the input data from the interface modules 18. The data is then stored in the local memory 38 for

  subsequent transfer or they are directly trans-

  shared memory 28 for transfer

  to the appropriate order recipient assembly.

  In the embodiment shown, the

  shared memory 28 includes a block of 8 k bytes (8,192)

  direct access memory The 8k bytes of memory

  are divided into two sections, an input section and an output section of 4 k bytes each. The shared memory 28 has dual channels for providing access.

  both by the micro-treatment unit 32 and the

  The data to be transferred to another link control set is placed in the input section of the shared memory. This data is then read by the main controller.

  and kept in the output section of all

  order taker Each shared memory 28 has a

  logic circuit intended to solve the problems of encum-

  caused by attempts by the main body

  29 and the local micro-treatment group to have

  simultaneously access to the shared memory 28 of the set

corresponding order.

  Control signals flowing between the-or-

  main controller 29 and a link control assembly are flowing through a parallel input-output channel

  of each set of control For example, link-

  Microtreatment 32 may transmit an interrupt signal through the input-output parallel channel 40 and the common line 14 of the assembly to the main controller, or vice versa.

  the main control unit retains an authorization signal

  in the parallel channel 40 so that it implements an input section or an output section of the shared memory 28 in the address space of the main controller The implementation operation is described more

251878 1

  in detail later in this memo.

  The link control set also has a

  circuit 42 forming counter and timer for transmitting

  put synchronization signals to the process module

  In the embodiment shown, the cir-

  cooked 42 is made using a straw "Zilog" Z 80 A-

  CTC which is compatible with the microprocessor "Zilog" Z 80 A. The circuit Z 80 A-CTC has four independent channels, two of which are used for the transmission of interrupt signals

  ordered by a horio 4 e at the set 32 microtreatment.

  The other two channels transmit clock signals

in real time.

  As shown in FIG. 3, the main control member has a microtreatment assembly 44 which can be analogous to the microtreatment assembly 32 of each control assembly. The control member 29 also has its own local memory 46. which is connected to the set

  44 microtreatment by the common line 10 of the set.

  A control member 47 may be used for

  a flexible disk (not shown) when charging

  programs in the memory 46 of the main controller and in the local memory 38 (FIG.

  each set of link control.

  In the embodiment shown, the

  appears to be microtreatment of the main

  Mande has a memory address space of 64 kilobytes.

  Thus, it can address a maximum of 65,536 locations

  individual memory in read operations and -

  An address space of micro-processing set

  of the 64 k main control unit is

  practically in FIG. 4 by a rectangular zone

  The upper part of area 48 represents the address O and the lower part the last address

  of the space is 65,536 (designated by the reference "64 K").

  Part of the address space of the organ

  The main command is reserved for a window 50 of

  shared memory which is used for the addressing of

  shared memories 28 of the linkage command set 20

  In the particular case considered, 8 k bytes of the

  address space of the main control device are

  used at the shared memory window 50 since each link control assembly memory has 8k memory locations The window 50 is subdivided into a section 52 and an output section 54 each having an address block of 4k bytes "

  The set 32 microtreatment of each

  Apparently, this link control has a 64 kilobyte address space. Such 64k memory slots for two link control assemblies 20a and 20b are represented by two-rectangles 56 and 58 in FIG. command set memory space

  link, a shared memory is identified by a reference

  28a, 28b, for the memory spaces of the sets a and 20b respectively As indicated previously,

  each shared memory is subdivided into a section of

  In FIG. 4, the input sections of the shared memories 28a and 28b are indicated by references 60a and 60b respectively, while the output sections are identical.

  perished by references 62a and 62b respectively.

  The main control member 29 implements the input section 60a of the shared memory of the set a in the input section 52 of the address space of the main control member 29 so that it This transfers the data from a control source set such as set 20a to a destination set such as set 20b. The main controller 29 then implements the output section 62b of the memory space. of the assembly 20b in the output section 54 of the address space of the main control member Ce-last

  can then address the data held in the sec-

  60a to read the data as if the memory locations of section 60a were

  part of the local memory of the main communication organ

2518781-

  In the same way, the main control organ addresses the memory locations inside the section.

  62b of the set 20b so that it writes the data

  read in the set 20 a in the output section-

  62 b of the set 20 b The particular layout of an input or output section of the shared memory of a link control set in the address space

  of the principal control organ by that body is de-

  will be described in more detail later in this memo.

  Although Figure 4 indicates that the address block

  its reserved for the shared memory window is in the block of addresses comprising the last 8 k bytes of the address space of the main controller, the window 50 can be anywhere in the space

* Addressing the main body Similarly, the block of

  shared memory placements may be anywhere in the memory space of the link control assembly In addition, the sizes of the shared memory and the address space of the main controller are data purely for illustrative purposes only and

non-limiting.

  When the implementation function and the trans-

  data from a command-link set to

  another must be ordered, the whole source of com-

  the data to be transferred, transmits an "interrupt request" signal to the main body 29 of the

  control via the parallel channel 40 input-

  output (Figure 2) of the control assembly.

  5, the parallel channel 40 has a parallel circuit

  In the embodiment of FIG.

  presented, this circuit 64 is a programmable device

  two-channel circuit which constitutes an interface circuit

  TTL logic (transistor-transistor logic) between the main organ 29 and the microtreatment assembly

  32 of the link control assembly The parallel circuit 64 may, for example, be an integral circuit chip.

  "Zilog" parallel input-output control which is compatible with the "Zilog" microprocessor Z 80 A.

  The parallel input-output circuit 64 has several

  order registers intended to preserve

  control devices such as interrupt signals and authorization signals When a link control unit interrupts the main controller,

  the set 32 microtreatment of this set of com-

  Mande puts a bit in a control register of the circuit 64 and thus causes the creation of an interrupt request signal in a line 66, this signal reaching,

  by an interrupt logic circuit 70 and the Ignè com-

  mune of the set, to the set 44 of microtreatment

of the main control organ.

  When this microtreatment assembly 44 of the main organ receives an interrupt request, it transmits an "interrupt recognition" signal by

  the common line 14 The parallel input-output circuit 64

  of the particular link control set which has formed the interrupt request signal responds by transmitting the contents of a command register in

  the common line 14 through a set of transmitters-

  receivers 68 connecting the circuit 64 to the common line 14.

  The data thus transmitted to the

  mune 14 following a signal of recognition of inter-

  ruption, are called "interrupt vector" and are

  introduced by the micro-treatment set 44

  Interruptor indicates to the principal

  the identity of the particular input / output circuit 64 (and thus the particular control unit) which

  formed the interrupt request received, as well as the sub-

  particular program allowing the processing of

  interrupt request The contents of the order register

  of the interruption vector is for example established by the

  appears to be microtreatment of the main organ

  where the unit is powered up.

  The parallel input-output circuits 64 have an integrated logic circuit for determining the channel having the highest hierarchical order among the circuits

251? W 81

  Parallel entrance-exit straws that require

  Rupture at the same time The parallel flake circuits of the link control units, via the internal logic interrupt circuit, can be interconnected in garlands to provide automatic control following the interrupt hierarchy, without external logic circuit However, in the case of a

  large number of link control assemblies and in

  sequence of a large number of parallel input circuits

  output related to the common line 14, it may be desirable

  table to add a logical reading circuit by early

  tion to allow the use of a large

  Such circuits An example of a forward-looking logic circuit is described in the "PIO Technical Manual" brochure and is represented by the circuit

  logic of interrupting FIG. 5, for each

  seems to control link and by the interrupt control logic circuit 72 (Figure 3) for the organ

main 29 of command.

  As shown in FIG. 5, the shared memory 28 of each control assembly includes a dual channel direct access memory 74 to which both the local microtreatment assembly 32 and the control main body 29 may have access. memory channel 74 is connected by a set of transceivers 76 to the internal common line 34 of the link control assembly while the other channel is connected by a set

  transceivers 78 to the common line 14 of the

  The transceivers 68, 76 and 78 may for example be formed by glitter integrated circuits.

  forming doors LS 244 and LS 245.

  The local micro-treatment unit 32, when

  it wants access to the memory 74 to direct access of the shared memory 26, addresses this memory 74 by placing address signals (corresponding to the locations in

  memory 74) in the internal common line 34 of the

  seems to control A logic circuit 80 selection -

  memory decodes the high order bits of the address signals and forms a "select" signal transmitted by

  a line 82 to a logic circuit 84 of associated clutter

  when the latter is not

  if addressed by the main control member 29, the congestion logic circuit 84 forms an authorization signal "transmitted by a line 86 to the transceivers 76 so as to

  that they transmit the address signals and the

  data lines of the internal common line 34 of the

  seems to command to the direct access memory 74 of this

  In this way, the local microtreatment set 32 can address

  memory 74 of shared memory 28 and can write data to the input section

  memory 74 for transfer to another

  seems to link control After writing data

  in the input section, the local microtrail

  32 establishes a control bit in the parallel circuit.

  I / O channel 64 so that it creates a signal of

  interrupt procedure as previously described at this time.

  Also, the microtreatment assembly 32 also triggers the counter and timer circuit 42 to create a local interrupt request signal transmitted by a line 88-to the local set 32 when the interrupt of the together is not recognized by the main body

  of control-29 during a predetermined period.

  After recognition of the request signal for in-

  disruption of the whole and determination of identity

  of the link control set that requests the

  In this case, the master controller 29 implements the input section of the shared memory 28 of this set of channels in the input section 52 of the shared memory window 50 of the address space of the device. The principal organ for this purpose is the principal

  29 control addresses the parallel circuit 64 input-

  output of the link control set which is requested

  deur, and it sets an input section control bit of an implementation control register in the circuit

  parallel 64 of the parallel channel 40 input-output.

  Channel 40 has a 90 address decoder

  I / O which decodes the address signals

  the main controller and generates an I / O parallel circuit authorization signal which, via a line 92, reaches the parallel circuit 64

  input-output when the address signals correspond to

  to the address of the implementation control register of this parallel circuit 64 The authorization signal of

  this parallel circuit peimet to the control register of im-

  planting the parallel circuit 64 to accept the data from the main controller and transmitted by the common line 14 of the assembly via

transceivers 68.

  When set to one, the control bit of the input section of the layout control register creates a layout control signal in the input section which is transmitted by a line 94 to a logic circuit 96. memory selection The command signal

  of the entry section authorizes the acceptance of

  through the input section of the shared memory 28 of this link control assembly, address signals from the main controller and

  transmitted by the common line 14 of the set as

  Figure 4 The implant control register

  a second bit which is set by the main body

  control pad 29 so that it forms a recognition signal.

  birth of input transmitted by a line 93 to the circuit 42 forming counter and timer The arrival of the signal of

  input recognition causes creation by this circuit

  cooks 42 of a local signal for a trans-

  put by line 88 to the local micro-treatment unit.

  After implantation in the address space, the main controller can address the input section by transmitting the address signals through the common line 14 of the set. The same address signals are presented. to the shared memory 28 of each link control set but only the input section which

  is located in the address space of the main body

  command line responds to address signals from

  of this organ The high order bits of the address signals

  have been decoded by the logic memory logic circuit 96 of the shared memory 28 which forms a "selection" signal transmitted by a line 98 to the logic circuit

  84 when the control signal for implan-

  input section, transmitted via line 94, is active If the local microtreatment set

  does not already have access to shared memory 28, the circuit

  congestion logic 84 creates an authorization signal transmitted by a line 100 to the transceivers 78 so that the low order address bits are transmitted through the set of transceivers 78 to

  the random access memory 74 of the shared memory -

  The main controller which thus has access to the input section of the link control source set, can read the initial part of the data which

  are kept there so that it determines the identity of the

  seems recipient of link control These signals

  data are transmitted to the common line 14 of the

  seems via the transceivers 78

  which are authorized by the main control organ.

  The output section of the shared memory of the link control destination set is then located in the output section 54 of the output window.

  shared memory of the address space of the main body

  command in a similar way to the one

  described for the entry section. Thus, the main body

  The central control unit sends the order

  planting of the input-output parallel circuit 64 of the

  appears binding command recipient so that it establishes

  blisse an output control section control bit of the implementation control register which causes the creation of an implementation control signal in the output section transmitted by a line 95 to the corresponding set of

  link control This implant control signal

  authorized the acceptance by the Exit Section of

  the shared memory 28 of the recipient-de-com-

  address signals and data signals from the main controller via

  of transceivers 78.

  In addition, several output sections can be implemented in the shared memory window of the main control unit. Thus, this unit can set the output section layout control bit in several connection control sets.

  before addressing the output sections of the memories

  In this way, the main body

  Command master can read the data in the input section of the link control source set and can write data in one or more sets

  bind command recipients.

  After the master controller 29 has transferred the data from the input section of the link control source set to the output section of a link control destination set, this body sets a a fourth bit of the implementation control register of the input-output parallel circuit of the destination control-link assembly so that it

  creates an output request signal transmitted by a

  104, from the parallel circuit 64, the circuit 42 forming counter and timer This circuit 42, when receiving the output request signal, creates an interrupt request transmitted by the line 88 to the microtreatment assembly 32 , this signal indicating to this set that data has been transferred to the output section of its shared memory The microtreatment assembly 32, following the interrupt signal, reads the data in the output section of its memory shared, treats

  data and transmits them to the external recipient

  through the appropriate interface module 18 and the appropriate input-output channel 16 of the processor module. The logic circuit 96 of memory selection of the shared memory Ue 28 is represented in more detail

  in FIG. 6 This logic circuit 96 includes a deco

  1/8 110 which may be an integrated circuit chip LS 138 for example The decoder 110 has three inputs

  of selection A, B and C connected to the three bits of high order

  Addressing of the SA 12-SA 14 set respectively,

  and an authorization entry connected to the address bit of

  the highest SA 15 from the common line 14 of the

  These four address bits of the high-order set are used for the selection of a particular block of

  4k bytes of memory locations addressable by the or-

main control unit.

  The logic circuit 96 of memory selection

  further comprises an AND port 112 having an input of

  version connected to the input section layout control line 94, from the input-output parallel circuit 64 (FIG. 5) * and an inverting input connected by a connection 114 to one of the eight outputs of the decoder 110 In the embodiment shown, the branch 114 is shown connected to an output 116

  decoder 110 This output line 116 is active, -

  that is, at a low logic level, when there is a particular combination of states of the address bits SA 12-SA This combination of states constitutes the address of the input section of the shared memory of each link control set The address of the input section with respect to the main controller is easily shifted by simple connection of the -connection

  114 to another output of the decoder 110.

  The output signal of the AND gate 112 is connected to the input of an NI gate 118 which has an output 120 connected to the inverting input of a second AND gate 122 The output of the latter is connected to the memory selection line 98 giving access to the main controller

  which is connected to the logic circuit 84 of congestion (FIG. 5).

  If the control signal for implantation of the section

  line 94 is active (local level).

  low) and if the address of the input section in

  shared memory is presented at the entries of the deco-

  110, the memory selection signal 98 becomes active <low logic level) when the main controller has access to the memory <the signal "SMMREQ" is active) If the local set 32 of microtreatment has not already access to the shared memory, the logic circuit 84 congestion (Figure 5) allows the transmission by

  the transceiver 78 of the address signals (and

  data) from the main communication organ

  command to memory 74 with direct memory access from

  In this way, the implant control signal

  input section allows the input section of the shared memory to accept address signals

  from the main control organ.

  The memory selection logic circuit 96 further includes an additional AND gate 124 which has inverting inputs connected to the control line 95 if the output section is implanted and to one of the decoder outputs 110 by a branch 126 The output signal of the AND gate 124 is transmitted to the other input of the NOR gate 118 The logic circuit operates

  analogous and forms a transient memory selection signal.

  put by line 98 when the address of the output section is presented to the decoder 110 while the signal

  control of the outlet section of the li-

  Figure 95 is active during a memory request transmitted by the main controller 29. At this time, the output sections of the shared memories 28 can be assigned any 4 kbyte address block in the space of the memory. addressing the main control member by selectively connecting the connections 126 to the decoders

  110 link control sets.

  Referring now to FIG.

  the logic circuit 84 of the memory of the shared memory-28, comprising two rockers D 130 and 132

  tipper 130 is established whenever the main body

  The central control has access to the shared memory 28 of the

  seems like link control Similarly, the rocker 132

  is established whenever the local microtitre set

  Thus, the D input of the flip-flop 130 is connected to the memory selection line 98 of the main controller, from the logic circuit 96.

  the memory selection of this organ Line 98 of

  the section is also connected to the input of a NAND gate 134 which has another input connected to the output Q of the second

  When the main communication organ

  mande tries to access shared memory 28 (the

  memory selection signal is active) while the

  seems local microtreatment already has access to shared memory (132 toggle established) a waiting signal is

  transmitted by a line 136 to the common line 14 of the

  (Figure 5), this signal reaching the microtreatment assembly of the main controller This operation prevents simultaneous access of the main controller to the shared memory while the whole

  microtreatment unit of the Liaison Control Unit.

  its has access to shared memory Likewise, a door NOT-

  ET 138 creates a waiting signal transmitted by a line

  140 to the local assembly 32 microtraitemient when the en-

  Binding Control Sequence Seeks Access to Shared Memory (Active Memory Select Signal) While the Main Controller Already Has Access

  to the shared memory (the rocker 130 is established).

  The rockers 130 and 132 can not change

  in the presence of a clock signal which is trans-

  put at the clock inputs CLK of the rockers 130 and 132.

  However, a delay circuit 142 transmits the clock signal.

  sits at the clock input of the second toggle switch 132 so that it introduces a delay such as the clock signal

  arrives at the rocker 130 before arrival at the rocker 132.

  Thus, if the main control organ and the local micro-treatment unit 32 seek access to

  same time to shared memory, the clock signal ar-

  first bank to the rocker 130 so that the output Q of the rocker 130 changes state first Thus, the Q output of the rocker 130 becomes active (high logic level) and causes the transmission of a waiting signal by the

  line 140 to the local microtreatment unit.

  When the Q output of the rocker 130 becomes active, the Q output also becoming active (low logic level) so that an authorization signal is transmitted via the line 100 to the transceivers 78 (Figure 5) connecting the common line 14 of the set to the memory 74 to direct access of the shared memory 28 The output of the rocker 130 is also connected to the erase input CLR of the second rocker 132 Thus, when the Q output of the rocker 130 becomes active, the output the toggle switch 132 becomes inactive (high logic level) so that the transceivers 76 (FIG. 5) which connect the internal common line 34 of the link control assembly to the random access memory 74 of the shared memory 28 do not In this way, the common address and data lines of the common line 14 of the set are connected to the direct access memory 74, and the common address and data lines of the internal common line 34 of the link control assembly are not connected to the memory 74 when the rocker is established The Q output of the rocker 132 is connected

  similar to the CLR erase input

  their 130 so that it is restored and that the transmitter-

  receiver 78 can not function when the output of the rocker 132 becomes active The transceiver

  76 can then transmit the address and data signals.

  from the local micro-treatment unit 32 to the

  28, while decoupling the common lines

  address and data of the common line 14 of the

  seems to have direct access memory 74.

  As previously indicated, each link control set can control up to four line interface modules 18 through which the data

  are exchanged with peripheral devices.

  Figure 8 shows in more detail an example of an information module.

  The main role of each of these modules 18 is to ensure a series-parallel conversion of

  For example, module 18 can assemble

  5 to 8 bits from a series of

  binary data came from an input-output channel 16.

  The assembile characters are then introduced by the linkage command set. Similarly, the module 18 serializes the parallel data from the set of

  link control, in a transmitted sequence of impulse

  binary via the channel

  16 input-output, to-a peripheral device.

  In the embodiment shown, each

  interface module with four input-output channels,

  Each of them is indicated by a dotted line as indicated by reference numeral 152. Each input-output channel 152 comprises a control circuit 154 which

  serial communication which puts the data in

  matte suitable for serial data communication as

  described above This communication control circuit

  in series can be achieved for example in the form of

  of a parallel controller flake integrated circuit

  Zilog I / O port Z 90 as previously described, furthermore having a chip-like integrated circuit of

  serial I / O control "Zilog" Serial I / O.

  The serial input-output circuit is a device

  tif programmable dual channel

  asynchronous, synchronous and synchronous bit types, for example "IBM Bisync" protocols (communications

  synchronous bits), "HDLC" (data link control)

  high level), "SDLC" (data link command)

synchronous births) and other serial protocols

  serial and parallel input-output of the serial communication control circuits 154, under the control of

251878 1

  the link control system, fulfill the functions

  data link processing procedures such as creating and verifying verification data

  cyclical redundancy, the automatic introduction of

  synchronization or etiquette and the introduc-

  automatic deletion of a zero.

  Each input-output channel 152 has gates

  156 to return loop controlled by an output bit -

  of the input-output parallel circuit These doors 156 are used in internal test mode in which the circuit

  Serial I / O is disconnected from the set

  and the outputs of the serial I / O transmitter

  channel are connected to the inputs of the input receiver-

  serial output In this way, each set of

  The liaison officer can check whether the data are suitable

nally transmitted.

  The cathode ray tube terminal, the

  or another external device is connected to the communications controller 10 at the connector 158 Each of the output channels 152 of the module 18

  interface shown in FIG. 8 is intended to cor-

  respond to the RS-232-C interface standard.

  158 to 25 pins Games 160 and 162 of riders

  putting variable afflation of the command lines and

  data at connector 158 and the input and output pins of the cir-

  serial and parallel cooked circuit 154 respectively.

  For example, the RS 232-C line interface module can be connected to function as a terminal.

  data or data communications equipment.

  A set of suppression circuits 164

  transient protection protects the various components of

  transmission controller 10 against transient currents and voltages occurring in any of the control signal lines and data signals, from the external device connected to the communications controller 10 at the connector 158 A set of

  RS-232 driver circuits 166 and receivers 168 of

251878 1

  RS-232 type transforms the voltages according to the RS-232 standard into voltage levels-which are-compatible with the circuitry of the interface module 18 and the controller. Additional isolation is ensured by a set of optical couplers or optrons. the module 18

  shown in Figure 8 was indicated as satisfactory

  to the RS-232 physical interface standard, the

  their 10 transmissions may have other modules of

  line terface allows the coupling of devices

  -10 external that require interfaces of other standards.

  A bit frequency detection circuit 172 is for determining the transmission frequency of the data read by the link control assembly, which set can then program a generator 174 to

  bit rate for transmitting hor-

  at a frequency appropriate to the frequency of transmission.

  The detected bit frequency detection circuit 172 may for example be in the form of a Zilog Z 80 counter-timer circuit, and the bit frequency generator 174 may be a circuit chip.

integrated COM 5016 for example.

  The link control assembly may address the serial communication circuit 154, the bit frequency detection circuit 172, or the bit frequency generating circuit 174 by transmitting suitable address signals decoded by

  a logic circuit 176 for decoding address and verifying

  parity cation This circuit 176 transmits a signal of auto-

  to the integrated circuit which is addressed by the control unit The common line 30 of the control unit

  link and the interface module is connected to the cir-

  integrated cooking of the input-output channel 152 by a game

  of common data line transceivers 178.

  Interruptions transmitted to the set of

  link control are created by the input circuits-

  serial and parallel output of the control circuit 154 These circuits can implement the incorporated daisy-chained interrupt hierarchy structure When many of these circuits are interconnected, = a circuit

  anticipatory consultation logic can be used

  This circuit is represented by the common line interrupt and logic control circuit 180 and the interrupt logic circuit 182.

  (Figure 2) of the link control assembly.

  The above description clearly shows

  that the transmission controller according to the invention can handle a large number of processor modules and is not limited by the address space of the main controller which transfers data from one processor module to another. , the architecture described above allows the simultaneous transfer of data to several modules

processors.

  It is understood that the invention has been described and shown only as a preferred example and that we can bring any technical equivalence in its constituent elements without departing from its

frame.

Claims (3)

- - CLAIMS -   1 data processing assembly, characterized in that it comprises: - several processors (12) for processing data, each processor having a memory   (28) to store data to be trans-   to the shared memory of another processor and to receive data from the shared memory of another processor, all the shared devices having an address block in common; and a device for transferring data from one shared memory to another, this transfer device   comprising an addressing device for each of the   shared memory (28) so that the data is read from a shared memory or written to a shared memory, and a device for allowing acceptance, by a particular shared memory, of an address from the data transfer device , all unauthorized shared memories ignoring the address from the   data transfer device.   2 Data processing set, characterized in that it comprises-: -   a common line (14) of the set, a plurality of processor modules (12) each having a processor (20) and an associated shared memory (28) connected to the common line of the set, each shared memory having a block address, in relation to the common line of the whole, in common with the other memories   shared, each processor having a writing device   of data in the associated shared memory, the data being intended to be transferred to the shared memory of another processor module, and a device   of reading data in shared memory, these data   which have been transferred by the shared memory of another processor module, and a main control member (29) connected to the common line of the assembly and intended to transmit   common E address signals to all shared memories   (28) so that data can be read in a machine.   chosen shared memory and be written in at least   a chosen shared memory, the main organ of communication   an apparatus for transmitting an authorization signal to a particular processor module so that it selects the shared memory of that module, each processor module (12) having further   an authorization device controlled by a signal from   and intended to allow acceptance by the -   shared memory of the associated processor module, signals   addressees from the main communication organ   mande. 3 assembly according to claim 2, characterized in that   each shared memory (28) has a sec-   input <60 a, 60 b) having an address block, relative to the common line of the set, which is common to the input sections of the other shared memories, and an output section having an address block, relative to the common line <14) of the set, in common with the output sections of the other shared memories,   the device for transmitting a signal of   terization includes a device for transmitting an input authorization signal to a processor module   (12) so that it selects the section of   trea (60a, 60b) of the shared memory of this processor and an output authorization signal transmitted to one or more processor modules to select the output sections <62a, 62b) of the shared memory the selected module or processor modules, and   the authorization device comprises a   positive to authorize acceptance by the secton   input of the associated shared memory,   addresses following an authorization signal from   to allow the output section of the associated shared memory to accept coded signals 251878 1   of address following an exit authorization signal.   4 -An assembly according to claim 2, characterized in that the validation device comprises a register connected to the common line (14) of the assembly and intended to maintain the authorization signal from the main control member and several gates controlled by the authorization signal and connecting the shared memory to the common line of the set so that the address signals from that common line and the data signals transmitted to and from the shared memory , when the operation of it is   authorized, may be exchanged.   Data processing set, characterized in that it comprises   a plurality of data processing devices (12)   each having a memory comprising a block of   shared memory (28) having a common block of addresses with the shared memory blocks of the other processing devices, a device for transferring data from one shared memory block to another, having an address space which includes a shared memory window (50) delimited by the shared block of addresses of the shared memory blocks of the processing sets, and a device for implementing the shared memory block of one or more processing devices (12) in the window (50) shared memory of the device   data transfer so that the shared memory im-   planted accepts an address contained in the common block of addresses and that the shared memories not implemented do not accept this data.   Controllers & transmissions characterized in that it comprises: a common set line (14), several input-output channels, several processors (12) each associated with at least one input-output channel and having a device interface providing the coupling between the processor and   the associated input and output channels, each process   Furthermore, the memory device has a shared memory connected to the common line of the set and a device for inputting data from an input-output channel, processing the data and storing the data in the associated shared memory so that they can be transferred to the shared memory of another processor, and a main controller (29) connected to   common line (14) of the whole and intended for trans-   put common address signals to all shared memories so that data is read into a   chosen shared memory and written in at least one   selected shared memory, the main controller 1.5 comprising a device for transmitting an authorization signal to a particular processor so that the shared memory thereof is selected,   each processor (12) having a further   station connected to the common line of the assembly and intended to maintain an authorization signal from the main control organ, a device-controlled by the -signal   memorized authorization and intended to allow the acceptance   the associated shared memory of the processor of the common address signals from the controller, and a device for reading the data written in the   shared memory associated with the main   and transmission of data to an input channel- output associated with this processor.