FR2516309B1 - - Google Patents

Info

Publication number
FR2516309B1
FR2516309B1 FR8120838A FR8120838A FR2516309B1 FR 2516309 B1 FR2516309 B1 FR 2516309B1 FR 8120838 A FR8120838 A FR 8120838A FR 8120838 A FR8120838 A FR 8120838A FR 2516309 B1 FR2516309 B1 FR 2516309B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8120838A
Other languages
French (fr)
Other versions
FR2516309A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DEMOULIN ERIC
Original Assignee
DEMOULIN ERIC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DEMOULIN ERIC filed Critical DEMOULIN ERIC
Priority to FR8120838A priority Critical patent/FR2516309A1/fr
Publication of FR2516309A1 publication Critical patent/FR2516309A1/fr
Application granted granted Critical
Publication of FR2516309B1 publication Critical patent/FR2516309B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
FR8120838A 1981-11-06 1981-11-06 Procede de fabrication d'un inverseur cmos forme de deux transistors empiles et auto-alignes par rapport a la grille de l'inverseur Granted FR2516309A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8120838A FR2516309A1 (fr) 1981-11-06 1981-11-06 Procede de fabrication d'un inverseur cmos forme de deux transistors empiles et auto-alignes par rapport a la grille de l'inverseur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8120838A FR2516309A1 (fr) 1981-11-06 1981-11-06 Procede de fabrication d'un inverseur cmos forme de deux transistors empiles et auto-alignes par rapport a la grille de l'inverseur

Publications (2)

Publication Number Publication Date
FR2516309A1 FR2516309A1 (fr) 1983-05-13
FR2516309B1 true FR2516309B1 (enExample) 1983-12-23

Family

ID=9263765

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8120838A Granted FR2516309A1 (fr) 1981-11-06 1981-11-06 Procede de fabrication d'un inverseur cmos forme de deux transistors empiles et auto-alignes par rapport a la grille de l'inverseur

Country Status (1)

Country Link
FR (1) FR2516309A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4921813A (en) * 1988-10-17 1990-05-01 Motorola, Inc. Method for making a polysilicon transistor
US6472232B1 (en) * 2000-02-22 2002-10-29 International Business Machines Corporation Semiconductor temperature monitor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142926A (en) * 1977-02-24 1979-03-06 Intel Corporation Self-aligning double polycrystalline silicon etching process

Also Published As

Publication number Publication date
FR2516309A1 (fr) 1983-05-13

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Legal Events

Date Code Title Description
ST Notification of lapse