FR2510845B1 - - Google Patents

Info

Publication number
FR2510845B1
FR2510845B1 FR8114945A FR8114945A FR2510845B1 FR 2510845 B1 FR2510845 B1 FR 2510845B1 FR 8114945 A FR8114945 A FR 8114945A FR 8114945 A FR8114945 A FR 8114945A FR 2510845 B1 FR2510845 B1 FR 2510845B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8114945A
Other languages
French (fr)
Other versions
FR2510845A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
OMERA SEGID
Original Assignee
OMERA SEGID
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by OMERA SEGID filed Critical OMERA SEGID
Priority to FR8114945A priority Critical patent/FR2510845A1/fr
Priority to DE8282200934T priority patent/DE3278612D1/de
Priority to EP19820200934 priority patent/EP0074674B1/fr
Publication of FR2510845A1 publication Critical patent/FR2510845A1/fr
Application granted granted Critical
Publication of FR2510845B1 publication Critical patent/FR2510845B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H03K19/0075—Fail-safe circuits by using two redundant chains

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
FR8114945A 1981-07-31 1981-07-31 Circuits logiques de securite utilisables notamment en signalisation ferroviaire et boite de traitement electronique, ou automatisme incorporant au moins un de ces circuits Granted FR2510845A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR8114945A FR2510845A1 (fr) 1981-07-31 1981-07-31 Circuits logiques de securite utilisables notamment en signalisation ferroviaire et boite de traitement electronique, ou automatisme incorporant au moins un de ces circuits
DE8282200934T DE3278612D1 (en) 1981-07-31 1982-07-22 Safety logic circuits, particularly usable in railway signalling
EP19820200934 EP0074674B1 (fr) 1981-07-31 1982-07-22 Circuits logiques de sécurité utilisables notamment en signalisation ferroviaire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8114945A FR2510845A1 (fr) 1981-07-31 1981-07-31 Circuits logiques de securite utilisables notamment en signalisation ferroviaire et boite de traitement electronique, ou automatisme incorporant au moins un de ces circuits

Publications (2)

Publication Number Publication Date
FR2510845A1 FR2510845A1 (fr) 1983-02-04
FR2510845B1 true FR2510845B1 (en:Method) 1983-11-10

Family

ID=9261057

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8114945A Granted FR2510845A1 (fr) 1981-07-31 1981-07-31 Circuits logiques de securite utilisables notamment en signalisation ferroviaire et boite de traitement electronique, ou automatisme incorporant au moins un de ces circuits

Country Status (3)

Country Link
EP (1) EP0074674B1 (en:Method)
DE (1) DE3278612D1 (en:Method)
FR (1) FR2510845A1 (en:Method)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2553605B1 (fr) * 1983-10-13 1988-12-02 Jeumont Schneider Circuit logique a seuil et a securite intrinseque
DE3570963D1 (en) * 1984-03-21 1989-07-13 Siemens Ag Circuit for memorizing dynamic logic signals
WO2001050604A1 (en) * 1999-12-30 2001-07-12 Ge-Harris Railway Electronics, Llc Vital 'and' gate apparatus and method
FR2808631B1 (fr) * 2000-05-03 2002-07-19 Erim S A Dispositif d'entree logique pour automate
FR2870652B1 (fr) * 2004-05-24 2007-08-03 Scle Soc De Construction De Li Dispositif de securite reproduisant une fonction logique notamment un "et" de securite

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL274016A (en:Method) * 1961-01-26
FR1391823A (fr) * 1964-01-08 1965-03-12 Westinghouse Freins & Signaux Circuit logique de sécurité du type et
FR1398923A (fr) * 1964-04-03 1965-05-14 Westinghouse Freins & Signaux Mémoire électronique de sécurité

Also Published As

Publication number Publication date
DE3278612D1 (en) 1988-07-07
FR2510845A1 (fr) 1983-02-04
EP0074674B1 (fr) 1988-06-01
EP0074674A1 (fr) 1983-03-23

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Legal Events

Date Code Title Description
CL Concession to grant licenses
TP Transmission of property
ST Notification of lapse