FR2506100A2 - Unidirectional transmission system for packet data - uses demodulator to recover synchronisation and data bit frequency for validation and error correction circuits - Google Patents

Abstract

Several data sources are multiplexed in a control unit for application to a modulator which also receives the video signals for transmission to a number of receivers. The TV receiver provides a video output for a demodulator. This comprises an impedance matching circuit to drive a sync. circuit and recovery circuit to recover the frequency of the data bits in the packet transmission. These allow the demodulator to recognise the starting octet for the data to ensure that succeeding data is transmitted to a logic circuit. This contains registers and control circuits to pass the received data to validation circuits. An error correction circuit provides signals for a cross coder followed by a formatter to output the data to a terminal.

Description

The present invention relates to a unidirectional data transmission system described in French patent 75 18319 filed
er June 6, 1975 and published under the NO 2 313 825, to the certificate of addition 77 17625 filed on June 3, 1977 and published under the NO 2 393 480 and at the request of 2nd certificate of addition 79 24570 filed the 27 September 1979.

 In the system of unidirectional transmission or broadcasting of data of the main patent, of the 1 certificate of addition and of the request for this 2nd certificate of addition mentioned above, the transmitted data are arranged in packets, each packet having, at most , the active duration of a television picture line. The packets are inserted, either in place of the image signals or of the raster return lines, between the conventional synchronization signals of the television lines.

 Each broadcast packet begins with a prefix containing, in addition to conventional bit and byte timing signals and channel identification code signals, a packet format signal indicating the length of the following data sequence the prefix. More precisely, in the packet, the useful data and the data which make up the prefix are grouped in bytes.

So the format signal is a byte that indicates the number of bytes of payload data following the prefix.

 Tests carried out on a transmission system conforming to the system defined above and using a public television network as the transmission medium have shown that it is necessary to protect the packet data against transmission errors, the same conclusion being valid for the information contained in the prefix. Since the packet is made up of bytes, it is particularly simple to provide error protection and error correction byte by byte. It is therefore natural to adopt a structure of bytes conforming to a Hamming code, that is to say a structure in which, for example, the binary elements bl, b3, b5 and b7 are reserved for the correction of errors. while the binary elements b2, b4, b6 and b8 carry the data.

 In the request for a second addition certificate, a system has been provided allowing, using a predetermined convention, to use only one format byte, in each packet prefix.

the format byte comprising four binary elements carrying information and four binary elements for correcting possible transmission errors, for useful data packets possibly comprising more than sixteen bytes and, in particular, up to fifty-one bytes useful.

 An object of the present invention is to provide a system which makes it possible, in addition to conventional teletext type data, such as the data from the ANTIOPE system, to broadcast, towards more sophisticated receivers, data streams having structures which offer possibilities. correction of errors and encryption, which, for example, are defined in the draft ISO 7498 standard relating to the architecture of interconnection networks of open data transmission systems. Of course, the transmission of this special data must be compatible with that of teletext data, that is to say that the means of transmission must remain common and that the implementation of the new system must not entail any appreciable modifications in the existing receivers.

 According to a characteristic of the present invention, there is provided a data broadcasting system in which the transmitting station broadcasts in the form of packets, digital data possibly originating from several channels, each packet comprising a prefix containing, in addition to conventional synchronization signals and channel identification code, a packet format signal normally indicating the length of the data sequence which follows the prefix, the transmitting station comprising as many couplers as channels, each coupler comprising an input circuit whose l the input is connected to the output of the channel associated with the coupler and the output of which is connected to a data memory, the output of which can be connected to a multiplexing circuit under the control of a control circuit common to all the couplers, and a counter supplied at a predetermined rate, the order of inhibition of the input circuit being given either as soon as said memory is full, or as soon as that said counter has reached a predetermined count, after which said memory is connected to the multiplexing circuit, then emptied, said counter is reset to zero and the inhibition order deleted, a register having a maximum adjustable capacity causing said order inhibition when the count of said data reaches a predetermined value, characterized in that between said memory and said input circuit is provided a small capacity buffer memory, the reading of the data from the buffer memory being controlled by a programmer, characterized in that there is provided an additional wire between each channel and its associated coupler, said additional wire being able to be brought to a level "1" (or "O"), and in that each coupler comprises first switching means for isolating said counter supplied at a predetermined rate and said small capacity buffer memory, a byte memory of zero value format and second switching means for connecting said counter e format byte memory to the data memory, at each packet transmission when said additional wire is at level "1", the first and second switching means being at rest when said additional wire is at level "O".

 According to another characteristic, there is provided an equipment for receiving the data broadcasting system, in which the signals which follow the prefix, when the latter is accepted, are seen in a buffer memory the output of which is connected to a output circuit, with a format signal register storing the format signal of the prefix of each received packet and a counter fed by a clock signal at the frequency of bytes which, when it reaches a maximum count, empties the sequence of data from the buffer memory in the output circuit, the length of the sequence being limited by the content of said format register, which is supplied by a transcoding circuit processing the broadcast format signal, characterized in that the transcoding circuit comprises means for recognizing the zero value of a format byte, means for translating this zero value into an Nmax value transmitted to said format register, and an additional output wire connected to udit output circuit.

The characteristics of the invention mentioned above, as well as others, will appear more clearly on reading the following description of an exemplary embodiment, said description being made in relation to the accompanying drawings, among which:
Fig. 1 represents the block diagram of a data dissemination system in which the improvements according to the invention are made,
Fig. 2 is a data packet diagram making it possible to illustrate the operation of the system of FIG. 1,
Fig. 3 is a block diagram of the logic part of the transmission equipment,
Fig. 4 is a diagram for illustrating the operating mode of the logic part of FIG. 3 in the case of data transmission from layer "4",
Fig. 5 is a block diagram of data reception equipment, and
Fig. 6 is a diagram of the transcoding circuit of the reception equipment of FIG. 5.

 The data dissemination system of FIG. 1 comprises a transmitting station comprising transmission equipment 41 and a television broadcasting antenna 42, as well as a plurality of subscriber receiving stations comprising a reception antenna 43, a television receiver 44 and data reception equipment 45 .

 The transmission equipment 41 comprises a so-called "manager" unit 46, which is responsible for time-division of data messages from a plurality of data sources which, in the example described, is assumed to be limited to seven sources 247 to 253, which are sources capable of transmitting conventional data as well as data offering possibilities for error correction and encryption. The equipment 41 also comprises a modulation part 54 which receives, on the one hand, the signals transmitted by the manager and, on the other hand, video signals by a link 55, and which transmits signals to a conventional transmitter, not shown, which feeds the antenna 42. By way of example, the description of a modulation part 54, which is not part of the present invention, will be found in the main patent 75 18319, already cited, and, in particular , in relation to FIG. 4 of it.

 The data transmitted by the manager 46 are arranged in packets. In the modulation part 54, the packets are inserted in place of the image signals, between the conventional synchronization signals of the television lines.

 Fig. 2 shows an example of data packets transmitted by the manager 46, then, after modulation, by the antenna 42.

 The packet has a length of N bytes numbered 1 to N and consists of two parts. The first part, called the prefix, is developed under the control of the manager 46 and consists, in the example shown, of the first eight bytes 1 to 8. The second part, consisting of bytes 9 to N, with N-9 = M , constitutes the actual data of the packet. The number N always remains less than a number Nmax which can vary, depending on the standard of the television network which provides the broadcasting, and can be determined by optimization, taking into account the length of the useful television line and the bandwidth. Thus, in the French standard with 625 lines, Nmax can reach 40, which corresponds to the L standard recommended by the CCIR.

 In the prefix, bytes 1 and 2 are reserved for the synchronization of the binary elements of the packet and each consist of the sequence of binary elements 101G1010. Byte 3 called "start" conventionally allows synchronization byte by byte and can correspond to the sequence 11100111. Bytes 4, 5 and 6 are reserved for the identification of the digital channel and are developed in coded form by the manager 46. Byte 7, called "continuity", makes it possible to count packet numbers or indices from 1 to 15 and therefore to account for packet omissions or errors in the reception equipment. Finally, byte 8 indicates the "format" of the packet, ie the number of M bytes following the prefix to form the packet.

 Referring again to FIG. 1, the television receiver 44 transmits, by its video output, the video signals to the equipment 45. The latter comprises a demodulation part 56, a logic part 124 and a reader 58 of an encoded medium 59. The demodulation part 56 delivers at 124 a binary element frequency signal (ebs) by 60 and the last (N-3) x 8 ebs of the packet of N bytes by 61. The information read by the reader 58 is permanently applied to the part logic 124. With regard to the role of coded support 59, reference may usefully be made to French patent 2 313 825. The reception part 124 delivers at 62 the bytes of the packet data to an appropriate terminal, such as 63, more a signal on a link 176 which will be described in FIG. 5.

 Fig. 3 shows an omnibus line 65, a control circuit 66 and a coupler 267, capable of connecting any of the sources 247 to 253 to the line 65. Note that there are as many couplers as there are sources. In practice, the line 65, the circuit 66 and the couplers 267 constitute the manager 46, FIG. 1. The control circuit 66 is connected to 65 and can command the couplers 267 to connect to 65. The circuit 66 will not be described in detail since it is identical to the circuit 76 in FIG. 3 of French patent 2,313,825. It will simply be recalled that the circuit 66 transmits, in the form of addresses, interrogations to the couplers in order to collect the identities of the couplers ready to transmit, then successively transmits transmission orders to these couplers.

 In the coupler 267, the interrogations from 66 enter via the link 68 connected to an address identification circuit 69 comprising the components 90, 92 and 126 of FIG. 3 of the main patent. Circuit 69 has its output connected to the first input of an AND gate 111 whose output is connected to 65.

 The data coming from the source associated with the coupler 267 are transmitted by a junction 70 of the type described in French patent 2 268 308. By junction 70 the data enter, in parallel bytes, in an input logic circuit 71 of which the output is connected, on the one hand, to an input of an AND gate 268 and, on the other hand, to an input of an AND gate 279. The output of AND gate 268 is connected to the input d an intermediate buffer memory 170 the output of which is connected to the input of an OR gate 280 the output of which is connected to the input of a buffer memory 72. The output of the AND gate 279 is connected to the other entrance to OR gate 280. At the same time, at link 70, the source is connected to coupler 267 by a wire 269 whose level "1" indicates that the source transmits layer data "4" and whose level "O" indicates that it is transmitting conventional data.

 Furthermore, the forward service wire of the link 70, which transmits a change of state for each byte transmitted by 70, is connected to the input of a byte counter 73, the output of which is connected, on the one hand, to an input of an AND gate 270, the output of which is connected to a register 74 which contains the number of bytes transmitted by 71 to the intermediate buffer memory 170. On the other hand, the output of 73 is connected to a input of an AND gate 271, the output of which is connected to an input of an OR gate 272. The register 74 has a reset input (RESET) connected to line 65, an output connected to the first input of an AND gate 75, an output connected to the second input of the OR gate 272 and an output connected to the input of a memory counter 171. The counter 171 has a control input connected, by a link 172, to the line 65 and its output connected to an input of an AND gate 272 whose output is connected to an input of an OR gate 274 whose output is connected to memory 72 by the link ison 173.

 The buffer memory 72 comprises two parts, one 75 in which the bytes of the packet prefix are stored and the other 77 in which are stored bytes of data originating from the source by 71 and 170. The part 76 has a first entry linked to a memory 78 which contains the bytes 1 to 3 for synchronization and start, a second entry linked to a memory 79 which contains the three bytes 4 to 6 for identifying each packet prefix, a third entry linked to a packet counter 80 which delivers the packet number, ie the continuity byte, and a fourth input linked to the output of the OR gate 274 which delivers, at the time of transmission, the count of the bytes contained in part 77 via the counter 171, that is to say the value "0" contained in a memory 281 the output of which is connected to an input of an AND gate 282 the output of which is connected to the second input of the OR gate 274, i.e. the format byte whatever 'be its origin.

An output of register 74 is also connected to the second input of OR gate 272 whose output is connected to the first input of a comparator 81 whose second input is connected to the output of a memory 82 containing the number Mmax = Nmax - 8, which is the maximum number of data bytes that can be transmitted in a packet. The exit of 81 is connected to an entry of a door
OR 83, to an input of a gate 275 whose output is connected to the first input of an AND gate 84, and to an input of an AND gate 276 whose output is connected to a third input of the OR gate 89.

The output of OR gate 83 is connected to an inhibition input of circuit 71.

The coupler also includes a simulation circuit 85, which receives a speed indication coming from 66 by 65 and a link 86. This indication depends on the operating speed of the reception equipment capable of receiving the data from the source. With this speed information, the simulator 85 simulates emptying of the buffer memory 72, these empties being counted in a counter 87 connected to the output of 85. The account outputs 1 to 4 of 87 are connected to the inputs of a door OR 88 whose output is connected to the second input of the gate AND 84. In addition, the output "4" of 87 is connected to an input of a gate AND 277 whose output is connected to the second input of the gate AND 75. The door exits
AND 75 and 84 are respectively connected to the first two inputs of OR gate 89, the output of which is connected to the second input of AND gate 111. The output of AND gate 75 is still connected to an input of OR gate 83.

 The output of memory 72 is connected to a logic transmission circuit 90 which receives from 65, via link 91, the frequency signal of the binary elements and, via link 92, the transmission order coming from the command 66. The output of circuit 90 is connected to line 65 by wire 93 which transmits in series, eb by eb, the packet to the modulation part of the transmission equipment. The link 92 is also connected to the input of the counter 80 which, in this way, can count the packets sent by the coupler 267.

 As mentioned above, circuit 171 has an output connected by AND gate 273, OR gate 274 and link 173 to part 76 of 72. Its second output is connected to an input of a AND gate 278, the output of which is connected, by a link 174, to the read command input of the buffer memory 170. The memory 170 is a memory whose content is emptied in part 77 of 72 at each read order from 171.

 In the coupler 267, the wire 269, parallel to the link 70, is connected, on the one hand, to the second inputs of the AND gates 271, 276, 279, and, on the other hand, to the input of an inverter 283 whose output is connected to the second inputs of AND gates 268, 270, 273, 275, 277 and 278.

 When the wire 269 is at level "O", the operation of the coupler 267 is identical to that of the second addition to the main patent, since the AND gates 268, 270, 273, 275, 277 and 278 are opened by the output signal of the inverter 283 which is at level "1". When the wire 269 is at level "1", the operation is slightly modified. Indeed, the simulation circuit 85 and its associated circuits 87 and 88 no longer intervene in the operation, any more than the register 74, the counter 171 and the intermediate buffer memory. If the AND gates are not taken into account 271, 276, 279 and OR gates 83, 89, 272, 274 and 280, which only serve as crossing points, the circuits which effectively intervene in the intelligent operation of the coupler are those which are shown in the diagram of FIG . 4.

 We know that memory 72 is emptied around 65, when the transmission of the packet is authorized and when the following condition occurs, namely that the number of bytes entered in 77 equals the maximum value stored in 82. As soon as the comparator 81 has detected equality on its two inputs, circuit 71 stops transmission on link 70 because its control input is inhibited. It is clear that, in each packet, the content of the format byte is "0".

 It should also be noted that the operator of the source associated with the coupler considered always transmits only significant data and that he does not have to be concerned with the number Mmax, nor with the frequency of transmission of the binary elements.

 The demodulation part of subscriber reception equipment is shown in FIG. 5. The video signals leaving the television receiver 44 are applied to an impedance matching circuit 95, the output signal of which is applied, on the one hand, to a circuit 96 for recovering the frequency of the binary elements and, on the other hand, to a synchronization circuit 97. The synchronization circuit 97 comprises the circuits bearing the numerical references in FIG. 5 of the main patent and is used in particular to recognize the start byte so as to transmit to the logic part 124, by the link 61 only the fourth byte of each packet and the following. The circuit 96 comprises, like the conventional circuits of recovery of the frequency of the binary elements, a tuned circuit comprising a variable impedance component 98, which can be a varicap, the impedance of which is controlled by the television channel selector 99.

The circuit 96 delivers the frequency signal of the binary elements, on the one hand, to the synchronization circuit 97 and, on the other hand, to the circuit 124 by the link 60.

 In the circuit 124, the signal at the frequency of the ebs is applied, on the one hand, to a byte register 100 and, on the other hand, to a divider by eight 101 whose output is connected to the input d '' a byte counter 102. The packet ebs are applied by 61 in series to the data entry of the byte register 100 which transmits the bytes in parallel to a routing circuit 103. The byte counter 102 has its first six outputs corresponding to the first six bytes received in 124, that is to say bytes 4 to 9, connected to control inputs of the routing circuit 103, whose inputs activated successively have the effect of orienting successively the bytes of the packet to the validation circuit 106 for bytes 4, 5, 6 and 7, to a correction circuit of '! amming 190 for byte 8, and to a data buffer 105 for the following bytes. The output of the correction circuit 190 is connected to the input of a transcoding circuit 125, the output of which is connected to the format register 104.

 The validation circuit 1C6 can include the circuits 168, 179, 166, 171, 167 shown in FIG. 6 of French patent 2,313,825 and, optionally circuits 173 and 174 of this same figure. The circuit validates the data received for their local use.

 The output of the buffer memory 105 is connected to the input of a switching circuit 107 which can be activated by a link 108 coming from 106. The output of 107 is connected to a junction 62, of the type of junction 70 of Fig. 3, which is connected to the user equipment 63. A wire from the junction 62 is connected to the input of a counter 109 counting the bytes transmitted by 107 and the output of which is connected to an input of a comparator 110, the other input of which is connected to the output of the format register 104 and the output of which is connected to an inhibition input of the circuit 107. Finally, the output of the byte counter 102 is connected to an input for validating the circuit 107.

Counter 102 activates its output when it reaches the count
Nmax. At this time, the buffer memory 105 has received Nmax bytes of which possibly only P packet bytes are valid, P representing the total length of the packet. Assuming that circuit 106 validates the packet, as soon as counter 102 validates its output, the bytes can be transferred from 105 to 62 via 107. As soon as P bytes have been thus transferred, the inputs of comparator 110 have equal values and the output of 110 prohibits any other transmission from 105 to 62, for the television line considered which is used to support the packet.

In the circuit of FIG. 5, the correction circuit for
Hamming is a conventional circuit which will not be described, while the transcoding circuit 191 makes it possible from the ebs b2, b4, b6 and b8 of the format byte to find the real length of the block, which is transmitted to 104, or to determine that it is a layer 4 data packet. By way of example, the circuit 191 may be provided in the form indicated in FIG. fi.

 In Fig. 5, the output of the television channel selector 99 is also connected to a control input of the transcoding circuit 191 which comprises, not only an output to the register 104, but a second output 126 which follows a path parallel to the link 62 .

In the circuit of FIG. 6, the input wires b2, b4, b6 and b8 transmit the four bits delivered by the correction circuit 190, in ascending order of the weights. The input wire b8 is connected, on the one hand, to the input of an inverter 192 whose output is connected to an input of a NOR gate 193 whose output
5 delivers a signal of value 2 or O on wire a5, and, on the other hand, to an input of a NAND gate 195 whose output is connected to an input of a NAND gate 198 whose output delivers a signal of
4 value 24 or 0 on wire a4. The input wire b6 is connected, on the one hand, to an input of a NOR 194 door whose output is connected to the second input of the NAND 195 door and to the second input of the NOR gate 193 and, on the other hand, to an input of a NAND gate 197 whose output is connected to the second input of the NAND gate 198.

The input wire b4 is connected, on the one hand, to an input of an AND gate 196 whose output is connected to the second input of the NOR gate 194, to the second input of the NAND gate 197 and to the first input of a NOR gate with three inputs 200, and, on the other hand, the first input of a NOR gate 199 whose output is connected to the second input of the NOR gate 200 whose output delivers a signal 3 value 2 or 0 on wire a3. The input wire b2 is connected, on the one hand, to the second input of the NAND gate 196, on the other hand, to the second input of the NAND gate 199 and, finally, to the first input
2 of a door NOR 201 which delivers a signal of value 2 or 0 on the wire a2. The input wire b4 is still connected to an input of a door
AND 202 whose output is connected to an input of an OR gate 203 which delivers a signal of value 21 or 0 on the wire al. The input wire b2 is also connected to the first input of an AND gate 205 whose output is connected to an input of an OR gate 206 which delivers a 0 signal with a value of 2 or 0 on the wire aO. The wire b6 is also connected to an input of a NOR gate 204 whose output is connected, in parallel, to the third input of the NOR gate 200, to the second input of the NOR gate, to the second input of the AND gate 202, at the second input of the AND gate 205 and at the input of an inverter 209. The output of the inverter 209 is connected to the first inputs of two AND gates 207 and 208. The output of the gate 207 is connected to the second input of OR gate 203 and the output of gate 208 is connected to the second input of OR gate -? 06. The second inputs of AND gates 207 and 208 are respectively connected to two control wires a and b.

 The values of outputs a5 to aO scnt added to the additive 210 before being applied to register 10.

 The input wires b2, b4, b6 and b8 are also connected to the four inputs of an OR gate 127 the output of which is connected to the control input of an electronic switch 128 whose first signal input is connected to the output of the adder 210 and the output of which is connected to the register 104. The second signal input of the switch 128 is connected to the output of a memory 129 in which a predetermined number is stored, which is preferably the maximum number Nmax of bytes. The link 130 between 99 and 129 makes it possible to vary the number Nmax as a function of the television channel selected. The output of the OR gate 127 is still connected to the link 126.

 When the format byte has a non-zero value, the output of the OR gate 127 is at "1" which switches the output from the adder 210 to the register 104 and the operation is that described in the 2nd certificate addition. When the format byte has a zero value, the output of the OR gate 127 is at "O", which switches the output of the memory 129 to the register 104 which therefore stores the number Nmax. Furthermore, by the link 126, the output of the OR gate 127 indicates. in parallel with link 2 that the package is not a conventional package.

Claims (3)

 1) Data broadcasting system according to one of claims 1 to 8 of the main patent in which the transmitting station broadcasts in the form of packets, digital data possibly originating from several channels, each packet comprising a prefix containing, in addition to signals of conventional synchronization and channel identification code, a packet format signal normally indicating the length of the data sequence which follows the prefix when the data transmitted is teletext data, characterized in that, when the data transmitted have structures offering possibilities for error correction and encryption, the length of the transmitted packets is always equal to the maximum length and the format signal takes a zero value.  2) System according to claim 1, wherein the transmitting station comprises as many couplers as channels, each coupler comprising an input circuit whose input is connected to the output of the channel associated with the coupler and whose output is connected to a data memory, the output of which can be connected to a multiplexing circuit under the control of a control circuit common to all the couplers, and a counter supplied at a predetermined rate, the order of inhibition of the circuit input given either as soon as said memory is full, or as soon as said counter has reached a predetermined count, after which said memory is connected to the multiplexing circuit, then emptied, said counter is reset to zero and the inhibition order deleted , a register having a maximum adjustable capacity causing said inhibition order when the count of said data reaches a predetermined value, characterized in that between said memory and said input circuit is p review a small capacity buffer memory, the reading of the data in the buffer memory being controlled by a programmer, characterized in that an additional wire is provided between each channel and its associated coupler, said additional wire being able to be brought to a level "1 "(or" O "), and in that each coupler comprises first switching means for isolating said counter supplied at a predetermined rate and said small capacity buffer memory, a byte memory of zero value format and second switching means for connecting said format byte memory to the data memory, at each packet transmission when said additional wire is at level "1", the first and second switching means being at rest when said additional wire is at "O" level.  3) Equipment for receiving the data broadcasting system, used in a system according to claim 2, in which the signals which follow the prefix, when the latter is accepted, are sent in a buffer memory the output of which is linked to an output circuit, with a format signal register storing the format signal of the prefix of each received packet and a counter fed by a clock signal at the frequency of bytes which, when it reaches a maximum count, empties the sequence data from the buffer memory in the output circuit, the length of the sequence being limited by the content of said format register, characterized in that the format register is supplied by a transcoding circuit processing the broadcast format signal, characterized in that the transcoding circuit comprises means for recognizing the zero value of a format byte, means for translating this zero value into an Nmax value transmitted to said format register, and an additional output wire connected to said output circuit.