FR2505593A1 - Multiple sound channel compression and video combining circuit - uses sampling circuits to digitise data for insertion at vertical line return period of video signal - Google Patents

Abstract

A number of sound channels are each applied to sampling and data storage circuits. Each of these circuits receives two clock signals, one of which is a square wave synchronised with the horizontal sync. pulses of the video signal. The second clock signal is at twice the frequency of the first and the sound signals are sampled at the trailing edge of this clock pulse. A sampling signal pulse identifies the sampling interval and a start conversion signal triggers an A/D converter in the sampling circuit. The digital data is stored in a memory ready for transfer to a main memory. During the vertical line return period, the compressed sound signals are read sequentially and are transmitted during the unused line period by combination in a logic circuit with the video signal.

Description

 The invention relates to a video system combined with multiple sound channels and more specifically to a system for compressing a number of sound signals to transmit them, such as a video signal, during the vertical return period of a television signal.

 Systems for transmitting compressed sound signals under part of a standard television signal are well known in the prior art. Typically these systems transmit the sound signal during the unused portion of each scan line following the timing signals and preceding the normal video interval.

 Although these systems give the expected results, the number of sound channels they allow to multiplex is limited, since only a very limited portion of the time interval of each scan line is available for sound transmission. .

 On the contrary, the system according to the invention makes it possible to have about ten full lines of video scanning for each transmitted frame.

 The system and method according to the invention make it possible to compress over time several sound signals, each consisting of a discontinuous and segmented signal, and to transmit the signals of its tablets during the vertical return interval of a standard video signal.

 Compression is achieved by digitally sampling each of the sound signals at a double rate of the horizontal scan rate of the video signal, and storing these digital samples in a memory during the horizontal synchronization interval. The stored digital samples are compressed by reading all the samples stored during a frame of the video signal, and by converting the digital samples into an analog signal. The analog signal thus obtained is transmitted during an unused line of the vertical return interval.

 The video signal containing the signals of its tablets can pass into conventional video channels.

 Likewise, the demultiplexed video signal (i.e. the video signal separated from the signals of its tablets) can be processed in standard video equipment. In the receiver, the signal of its tablet is sampled at high speed to give digital samples emitted in a memory. These digital samples are played at a lower speed to restore the initial sound signals. The demultiplexed signal may also be processed in standard sound equipment with the proviso that part of the frequency response may be lost as a result of the sampling rates used in the multiplexers and demultiplexers.

 To achieve the above aims, the invention relates to a video system comprises compression of several sound signals and their combination with a video signal to obtain a composite signal, characterized in that it comprises compression means of each of the sound signals for producing a sound signal having discontinuous portions, each having a bandwidth greater than that of the initial signal; means for sequentially inserting each of the sound signals into the video signal such that each sound signal occupies one of the normally unused scan lines of the video signal vertical return interval to produce a composite signal comprising both the normal video signal and the sound signals compress a transmission link of this composite signal; means responsive to the output signal of the transmission link for separating the composite signal into a standard video signal and a signal constituted by the signals of its tablets, and means for separating the signal from its tablet into its individual individual elements and to expand these individual elements to reconstitute the initial sound signals.

The invention is described in detail hereinafter with reference to the accompanying drawings, in which
FIG. 1 is a block diagram of a system corresponding to one embodiment of the invention.
FIG. 2 is a block diagram of the sound multiplexer
FIG. 3 is a diagram representing the waveforms of the control signals used in the system according to the invention
FIG. 4 is a block diagram of the demultiplexer of its
FIG. 5 is a diagram showing the waveforms of the control signals used to produce the high speed signals for compressing and demultiplexing the sound signals.
FIG. 4 is a diagram representing the vertical return interval of a standard television signal containing the signals of its tablets.
FIG. 7 is a block diagram of the digital part of the sound compression circuits.
FIG. 8 is a block diagram of the fast digital-to-analog converter
Fig. 9 is a block diagram of the portion of the system combining the video signal with the sound signals of its tablets, and producing the control signals of the system
FIG. 10 is a block diagram of the part of the system for separating the signals of its compressed from the video signal, and for producing the demultiplexer control signals; FIG. 1 is a block diagram of the demultiplexer of its .

 The illustrated embodiment of the invention consists of a system for compressing the sound signals and transmitting them as part of the video signal during the vertical return interval. Each sound signal is transmitted during one line of the vertical return interval. Each active line of a standard television signal lasts about 52.5 microseconds. As each frame of the television signal lasts one-eighth of a second, and since all the sound signals of a frame must be compressed into a video line, the compression ratio must be 333.1 to 1.

 Image scanning systems using different scanning rates lead to different compression ratios. The compression ratio should also change if only part of the active video line is used to transmit a sound channel. As a complete sound signal is transmitted during a single video line, the signal of its tablet is segmented and discontinuous.

 Figure 1 shows a block diagram of the system. This system includes circuitry for compressing a plurality of sound signals in the required ratio of 333 to 1 I, and combining these signals with a standard video signal to produce a composite signal including normal (video) image information and N signal channels of his tablets.

This composite signal is then transmitted, by conventional signals, to a receiver in which the signals of its tablets are extracted to give a standard video signal. The signals of his companions are 3sally demultiplexed and dilated to restore the initial sound signals.

 The sound signals to be compressed are applied to the input of a sound compression device 30. This compression circuit 30 samples each of the input sound signals to produce two digital samples per line of the video signal. For each frame of an interlaced television signal, this corresponds to 525 samples. These samples are stored in a memory constituting part of the sound compressor 30, this memory being sufficient to store 525 samples of each of the input sound signals.

 During the vertical return interval, an unused video line is assigned to each of the input sound signals. The 525 samples of each of the input sound signals are read sequentially and transformed into a signal from its tablet occupying its free line of assignment in the vertical return interval. This makes it possible to obtain, at the output of the sound compressor 30, a signal from its tablet whose duration is equal to that of a video line (ie from the video portion of a standard video line) a signal separated being produced for each of the input sound signals. In this way the signals of his tablets are segmented and discontinuous.

 The signals of his tablets and a standard video signal are applied to. The video switch 32 is co-inputted to input the signals of its tablets into the appropriate free video lines during the vertical return interval.

 The composite video signal obtained at the output of the video switch 32 is connected to a transmission system 34. This transponder system 74 may be a standard television transmitter, a video cable, or any other conventional means of transmitting video signals. television. The only function of the transmission system 34 is to provide a suitable means for transmitting the composite signal between its point of formation and its point of use.

 At the point of use, the composite video signal is applied to the input of a second video switch 39 pass to the on-off position appropriately so that only the image portions or video portions of the composite signal are applied to the output terminal of this switch. A signal formed by the initial video portion is thus obtained, and this initial video signal appearing at the output of the video switch 39 is used in a conventional manner.

 The composite video signal comprising the video signal and the signal of its tablet is also applied to the inputs of a sound demultiplexer 38 (FIG. 4). The signal from its tablet is separated from the video signal by the video switch 39. During the video line and when each of its tablet signals are present, a fast digital analog converter 41 samples the sound signal to give 525 samples which are stored in a video recorder. digital memory as part of a sound processing circuit. An identical sound processing circuit is associated with six typical circuits identified by the references 43 to 49. One of these samples corresponding to each sound channel is read at each scanning line of the video signal and converted into its analogical equivelent.

The circuit for performing this function will be described in detail later.

 Figure 2 shows a more detailed block diagram of the coding or compression part of the system.

This system illustrated in FIG. 2 receives N sound channels and a standard video signal. Each of the sound signals is applied to a sound sampling and storage block. For example, the first sound signal is applied to the input of a sound sampling and storage block 40. From the m8m2 way, the second to fourth sound input signals are applied to blocks of sound. sampling and storing its identical 42 to 46.

 Each of the sample and sound storage blocks 40-46 receives two input clock signals.

One of these signals, called the clock H (reference 48 in FIG. 3), is a square signal whose frequency is synchronized with the horizontal synchronization pulses of the signal.
video. A second clock called clock 2H (reference 150 in Figure 2) is also constituted by a square sigral.

has a frequency twice that of the horizontal synchronization pulses.

 The sound input signal is sampled on the trailing edge of each pulse of the clock signal 2H and converted to form a digital data representing the sound signal amplitude during the sampling interval, each time interval. sampling being identified by a pulse of the sampling signal 51. An analog-to-digital converter constituting part of the sampling and sound storage blocks (FIG. 2) is triggered by the conversion start signal 53, so as to provide two digital data. These digital data are temporarily stored in a memory and followed by an end-of-conversion signal pulse 58. Sufficient memory is provided to store two samples.

 On the leading edge of each pulse of the clock signal H of the next video line, two pulses constituting the write trigger signal 55 and the sound clock signal 57 are generated to transfer the two main memories into the main memory. temporarily stored samples. Sufficient memory space is provided in the main memory to store 538 samples. During each of the unused lines, a fast clock signal 59 is generated. This signal is released by the read inhibition signal 61 and combined with the sound clock signal 57 to produce a multiplexed clock signal 63 specific to each memory. Thus, during each frame of the video signal, the memory is loaded with 538 samples, all of which are read during one line of the television signal to produce a signal from its tablet.

 During each vertical return interval, the vertical synchronization of the pulses is detected and indicated generally by reference 52 in Fig. 5. The leading edge of the vertical sync pulse is used to indicate the start of an interval. of time identifying the unused video lines in which the sound signals need to be multiplexed. In the system currently produced, eight free video lines are used to transmit the signal of his tablet. This time interval is identified by the low value of the decoding counter trigger signal, indicated by reference 54 in Fig. 5. Likewise, additional sound channels may be added.

The decoding trigger signal resets a counter. This counter is then increased step by step by the horizontal synchronization pulses, to produce line identification signals called Q0 to Q8 and generally indicated by reference 56 in FIG. 5. The high level of each of the signals <0 to w8 identifies a video line during which a channel of its tablet must be transmitted. For example, the high level of the signal
Qo triggers the connection of the fast clock signal to the first sound sampling and storage block 40, which causes the 535 stored samples to be sequentially read under the control of the fast clock signal 59 (this signal also being shown in FIG. in Fig. 3) and the low value of the playback trigger signal 71 of the channel>h; 1.

 Each of the samples is applied to a fast analog-to-digital converter 58 whose output constitutes the signal of its tablet and is connected to a video switching and control logic circuit 60. This video switching circuit 60 combines the output signal of its tablet of the analog-to-digital converter 58, with the video input signal, so as to produce the composite signal.

 The signal of its tablet of the first channel is illustrated, for the odd and even fields, by the respective references 62a and 62b of FIG. 6. The signal of its tablet of the other sound channels is combined in the same manner with the signals of FIG. normal synchronization, the read trigger signals for ss channels 2 and 46 being marked respectively by the references j and 75. The intervals for the transmission of other channels are referenced 64a and 64b in Figure 6.

 It will be noted that in fact, due to the pairwise pairing of the samples during the horizontal return period, 524 samples are processed during the odd field and 526 samples during the even field.

 If the signal from its tablet were sent directly to the encoder in the sequence in which the samples were produced, it would be necessary to resample the signals with absolute precision so as not to produce one or more incorrect samples either at the beginning or at the end of each signal. This characteristic is a very severe constraint for the design of a decoder and can be avoided if the sound signal packets are overlapped. To obtain this result, standard 1024 kilobyte memories are used to store 538 digital signal samples representing the signals of its tablets and it is considered that these memories are arbitrarily divided into three sections.

 The first section comprises the addresses 513 to 1024, this memory storing 512 samples being considered as the main memory. Addresses 245 to 256 constitute what is considered the odd field auxiliary memory and store the remaining 12 samples of the odd field. The addresses 115 to 128 constitute what is considered the paired frame auxiliary memory and store the remaining 14 samples of the even frame. These addresses are chosen from among many possible combinations in order to facilitate and simplify the implementation of the system, given that the available memories are modular-in groups of 1024 addresses.

Starting at the beginning of an odd field, the random access memories are programmed according to the following sequence
Mode 1 - write to main memory
Mode 2 - write to odd frame auxiliary memory
Mode 3 - reading in paired frame auxiliary memory
Mode 4 - reading in main memory
Mode 5 - reading in odd frame auxiliary memory
Mode 6 - write to main memory;
Mode 7 - write to paired frame auxiliary memory
Mode 8 - reading in odd frame auxiliary memory
Mode 9 - reading in main memory
Mode 10 - reading in auxiliary memory of even frame.

 FIG. 7 is a block diagram of the hardware constituting the sampling circuits of the input sound signals making it possible to obtain a signal of its tablet in digital form. The input sound signal is first connected to a low pass filter 66 whose role is to limit the frequency of the input signal to avoid harmonic problems due to sampling.

 A sound signal limited to the desired frequency range is obtained at the output terminal of the low-pass filter 66.

This signal is applied to the input terminal of a sampling and storage circuit 68. The clock signals 2H and H (48 and 50 in FIG. 3) described above are applied to the input of a write logic circuit 70.

 This logic write control circuit 70 produces the sampling signal (51 Fig. 3) applied to the sampling and storage logic 68 to identify the time interval during which the sample is to be sampled.

 The output of the sampling and storage circuit 68 is connected to the input of an analog-to-digital converter 72. The write logic control circuit 70 produces the conversion start signal (53 FIG. 3) indicating that the output signal of the sampling and storage circuit 68 is stable and this output signal of the circuit 68 must be converted into its digital equivalent.

 when the analog to digital converter 72 has finished converting its input analog signal to its digital equivalent, the end of conversion signal (58 Fig. 3) is triggered and applied to the write and control logic 70. In response at this end of conversion signal 58, the write and control logic 70 generates a write trigger signal applied to a random access memory 74 to indicate that the digital equivalent of the analog sample is available at the same time. memory input for 8trie stored in it.

 the addresses of the storage and read data in random access memory 74 are provided by a random access memory address counter 76 stepped up by the multiplex clock signal (shown in Fig. 3) provided by the clock multiplexer circuit 78.

This circuit 78 also receives at the input the fast clock signal, the retrigger signals 71, 73 and 75 previously indicated, and the write trigger signal provided by the write and control logic 70 through the delay circuit 80.

 The random access memory address counter 76 is intended to count up to the maximum value of 102. At this time, this counter is preset to a new value by the signals from the read-only read only 86 controlled by the counter. This counter 82 is in fact a mode counter for indicating in which of the ten modes described above the random access memory is to operate. The counter 82 is incremented step by step by the output signal of a count detector circuit 84 detecting the current status of the random access memory counter 76 and comparing this state with a count selection signal from the memory 86. When the combination of these two signals indicates that the end of one operating mode has been reached, the read-only memory counter 88 is increased to indicate the next mode.

 If the read-only memory address counter 82 is in the wrong mode, simply do not increase it to the next frame of the video signal and therefore the system will automatically be synchronized. During the time interval corresponding to the video line which is to be used to transmit the signals of its tablets, the fast clock signal is multiplexed in the random access memory counter 76, which causes the reading, with the a good sequence of all the memory positions of the random access memory 74. This allows to obtain at the output of the random access memory 74 the digitized version of the channels deson cimprimés. This process and the implementation of the hardware illustrated in Figure 7 are repeated for each of the sound channels.

 During the write cycle of the random access memory 74, the write trigger signal from the write control logic 70 is delayed by the delay circuit 80. This signal dst applied to the clock multiplexer 78 then to the random access memory address counter 76, which stepwise increments this counter according to the appropriate mode to produce the required addresses for the random access memory 74.

 Fig. 8 is a block diagram of the analog-to-digital converter 92 used to convert the available digital samples to the output of random access memory 74 into a signal of its tablet. An input buffer register 88 stores the digital samples of the random access memory 74. The output signals of the buffer register 88 are applied via a synchronization module 90, so as to produce digital signals at the same time. The analog output signal of the digital to analog converter 92 is sampled by a sampling circuit 94 to provide an analog input signal to an amplifier 96. The output signal of the amplifier 96 is filtered to give the signal of his tablet.

 Fig. 9 is a block diagram of the circuit used to generate the clock and trigger signals as well as to combine the signal of its compact with the video signal to provide the composite signal. The conventional video signal is applied to the input of an amplifier 98 whose output signal is applied to a second amplifier 100, to a low-pass filter 102, to a DC component rendering device and to a synchronization separator. 104. The sync pulses of the video input signal are available at the output terminal of the dc component and the sync separator circuit 104. The sync signals are applied to a phase lock loop 106 to give the clock signals H and 2H. The output of the DC component reproducing device and synchronization separator 104 is also applied to a vertical synchronization pulse generator 108, these vertical synchronization pulses being used to increase stepwise a decoding counter 110.

 The output signal of the input amplifier 98 is also applied to the input terminal of a black level stabilization circuit 112. The stabilized video signal obtained at the output of this circuit 112 is applied to the input of a second synchronization pulse separator 114 whose output signal is applied to a pulse inhibition device 2H for eliminating the stabilization pulses present in the restored synchronization signal. The output signal of the pulse inhibition circuit 116 is applied to the frequency control input of a phase lock loop 118. The horizontal synchronization pulses available at the output of the synchronization pulse separator 114, are applied to the input of a monostable delay latch 120 whose output signal is applied, via a fast clock trigger pulse generator 122, to the justification flip-flop 124. The output signals of the justification oscillator 124 and the fast phase lock loop 118 combine in a fast clock gate 125 to provide the fast clock signal.

 The synchronization pulses available at the output terminal of the second synchronization pulse separator 114 are applied to the input of a second monostable oscillator 126. The output signal of this flip-flop is applied to the input of a read trigger generator 128 for producing the read trigger signals shown in Fig. 4.The output signals of the delay monostable flip-flop 126 and the decode counter 110 are combined in a gate pulse generator 130 to produce a signal controlling a video switch 132 such that the video input signal of the amplifier 98 is applied to the output terminal at all times, except during the period of presence of the signal of its tablet coming from the This results in the production of the composite video signal at the output terminal of the output amplifier 134.

 Fig. 10 is a block diagram of the circuit for providing the demultiplexer synchronization signals and for separating the video signal from the signals of its tablets. This circuit is similar to the circuit used in the encoder, however for the purpose of complete homogeneity, this circuit will be described hereinafter in detail.

 The composite video signal comprising the video signal and the signal of its tablet, is applied to the input of an input amplifier 136 whose output signal is connected, via a second amplifier 138, of a low-pass filter 140 and a DC component and synchronization separation component 142, so as to reproduce the synchronization pulses of the composite video signal.

The horizontal synchronization pulses available at the output of the continuous composite rendering and synchronization separation device 142 are applied to the input of a phase lock loop 144 to produce the clock signal H. The signal of output of the DC component and synchronization splitter 142 is also applied to the input terminal of a vertical pulse generator 146 to output the vertical sync pulses. The decode counter 148 receives the vertical sync pulses of the vertical pulse generator 146 and the clock signal X so as to produce write inhibit signals for the memory used in the demultiplexer.

 A lock pulse generator 150 also receives the output signal from a DC component and synchronization separation 148, so as to produce a black level stabilization control signal 152 which the output signal is the initial video input signal, with the DC component level restored.

 A restored black level composite video signal available at the output of the black level stabilization circuit 152 is applied to the input of a second synchronization pulse separator circuit 154 whose output signal is applied to a pulse inhibition circuit 156 to separate the standard television equalization pulse from the synchronization signal. This produces at the output of the pulse inhibition circuit 156 a square signal synchronized with the horizontal synchronization pulses of the video signal. These pulses are applied to the input of a phase lock loop 158 to produce a locked signal in place with the horizontal sync pulses.

 A monostable delay latch 160 also receives, as an input signal, the output signal of the synchronization pulse separator 154. A fast clock gate pulse generator 162 receives at the input the output signal of the monostable latch of delay 1t0. the output signal of the fast clock pulse generator 162 is justified by resetting the fast clock by the flip-flop 164.

A fast clock gate receives at input the output signal of the justification latch 164, the output signal of the phase lock loop 158 and a read trigger signal from the decode counter 148.

This allows to obtain at the output of the circuit of the fast clock gate 166, a clock signal used to sample the compressed sound signal.

 A monostable flip-flop 1t8 also receives at the input the output signal of the synchronization pulse separator 154. The output signal of this circuit is combined with the output signal of the decoder counter 148 to produce a signal opening and closing a switch. This signal is used in such a way that the video switch 170 is closed at all times, except during the video lines, when the signal of its tablet is present. During these intervals a continuous level of zero is applied to the input of an output amplifier 172, instead of the signal of its tablet. As a result, a video signal whose compressed signal has been suppressed is output at the output terminal of the output amplifier 172.

 As shown in Fig. 10, the composite video signal comprising the normal video signal and a compressed sound signal is also applied to the input of an analog-to-digital converter 176 (Fig. 11). A clock multiplexer 178 receives, at the input of the clock H, the write inhibit signals and the fast clock signal. An output signal from the clock multiplexer 178 is constituted by a signal triggering the analog-to-digital converter 176 to put the signal of its tablet in digital form so as to regenerate the samples of each line of the signal of its tablet.

 The samples of the signal of its tablet are written in a random access memory 180 using only four modes, namely the mode 1): writing in the odd memory frame; 2): reading in the odd field memory, 3): writing to the even field memory; 4): read in the even frame memory. Specifically, a random access memory address counter 184 stores digital data specifying the mode in which the memory operates. This signal is applied as an address to a read-only memory 186, so as to read a digital data setting the address counter 182 to the correct value. The read only memory 196 also provides the count detector 188 with a signal indicating which should be the top address of the mode. The clock signals for increasing the address counter 182 are provided by the clock multiplexer 118.

When the digital data stored in the address counter 182 reaches its maximum value, the counting detector 188 generates a pulse that increments the read only memory address counter 184 by one step to put the system into the mode. following.

 The fast clock signals H are applied to the input of the clock multiplexer 178 to produce the clock signals for the analog-to-digital converter 176 and to the address counter 182. The write inhibit signals trigger the clock multiplexer 178 for controlling the fast analog-to-digital counter 176 so that the latter samples, scans and stores the samples in random access memory 180. The clock signal H is used to advance step by step the address counter 182 so that the latter reads the stored samples at the correct speed. In addition, the clock signal H is applied to the input of a delay circuit 190 so as to produce a pulse moving the 8-bit output signal of the random access memory 180 in a latch circuit 192 of which the output signals are applied to the input of a digital-to-analog converter 191. The output signal of this digital-to-analog converter 191 constitutes the signal of its demultiplexed. This signal is filtered by a low-pass filter 194 to reproduce the initial sound signal.

 The demultiplexing circuits described in FIG. 11 are reproduced for each sound channel to be processed. The low-pass filter 194 is intended to suppress the sampling harmonics. In the system described here, this filter is a pass filter. down 7.5 kilohertz.

Identification of references used in the drawings
Legend N0 ref. figure
Compressor sound 30
Video switch 32 1
Transmission system 34
Demultiplexer sound 38 1
Video switch 39 1
Video switch 39 4
Sound Sampling and Storage 40 2
Analog to digital converter 41 4 fast
Sound Sampling and Storage 42 2
His 43 4
Sound Sampling and Storage 44 2
His 45 4
Sound Sampling and Storage 46 2
His 47 4
His 49 4
58 fast digital to analog converter
Video and logic switch 60 2 command
Low pass filter 66 7
Sampling and storage 68 7
Logic write command 70 7
Analog to digital converter 72 7
Access Memory Address Counter 76 7 random
Clock Multiplexer 78 7
Delay 80 7
Read memory address counter 82 7
Count Detector 84 7
Read-Only Memory 86 7
Entry register 88 8
Input register and clock module 90 8
Analog Digital Converter Module 92 8
Sampling circuit 94 8
Amplifier 96 8
Input amplifier i 98 9
Legend N0 of ref Figure
Input amplifier pt 2 99 9
Amplifier 100 9
Low-pass filter 102 9
Disposit. continuous component feedback and sync separator 104 9
Phase locked loop 9 106 9
Vertical pulse generator 108 9
Decode counter 110 9
Black Level Stabilizer 112 9
Sync pulse separator 9 114 9
Disposit. impulse inhibition 2 H 116 9
Quick phase locked loop 118 9
Monostable delay latch $ t 2 120 9
Clock pulse generator 122 9
Justify toggle 124 9
Fast clock door 125 9 Monostable delay latch # 1 126 9
Read trigger generator 128 9
Switch Door Pulse Generator 130 9
Video switch 132 9
Output amplifier 134 9 Input amplifier tt 1 136 10
Amplifier 138 10
Low pass filter 140 10
Disposit. Continuous component feedback and synchro separator 142 10
Locked lock ring tt 1 144 10
Vertical pulse generator 146 10
Decode counter 148 10
Lock pulse generator 150 10
Black Level Stabilizer 152 10
Sequencing Pulse Separator 3SL2 154 10
Pulse-inhibiting device 2 H 156 10
Quick phase locked loop 4; 2,158 10
Monostable delay rocker * 2 160 10
Fast Clock Door Pulse Generator 162 10
Legend N of ref. figure
Justify toggle 164 10
Fast clock door 166 10
Monostable latch delay to 168
Video switch 170 10
Output amplifier 172 10
Fast analog-to-digital converter 17b 1
Clock Multiplexer 178 11
Random access memory 180 11
Address counter 182 11
Read only memory address counter 184 11
Read only memory 186 11
Counting detective 188 11
Delay 190 11
Digital-to-analog converter 191 11
Lock 192 11
Low-pass pillow 194 he

Claims (4)

 10) Video system comprising the compression of a plurality of sound signals and their combination with a video signal, to obtain a composite signal, characterized in that it comprises means for compressing sound signals to produce a signal of its having discontinuous parts, each having a bandwidth greater than that of the initial signal; means for sequentially inserting each of the sound signals in the video signal such that each sound signal occupies one of the normally unused scan lines of the vertical return interval of the video signal to produce a signal composite comprising both the normal video signal and the signals of its tablets; a transmission link of this composite signal; means responsive to the output signal of the transmission link for separating the composite signal into a standard video signal and a signal consisting of the signals of its tablets; and means for separating the signal from its tablet into its individual elements and expanding these individual elements to reconstruct the initial sound signals.  20) System according to claim 1, characterized in that the compression means of each of the sound signals comprise means for periodically sampling each of these sound signals to produce a digital data representing the amplitude of the signal of its sampled in the sampling interval; digital data storage means at a first rate; reading means of these samples stored at a second rate, the latter being higher than the first; and circuit elements responsive to the stored samples read at high rate, to form a plurality of signals of its discontinuous each representing one of the sound signals.  30) System according to any one of claims 1 and 2, characterized in that the reading means stored samples comprise clock means for synchronizing the speed at which the stored samples are read, so that each of the sound signals has a duration substantially equal to the duration of the video portion of a line of the video signal.  40) System according to any one of claims 1 to 3, characterized in that the means for separating the signal of its tablet into individual elements, comprise means for detecting the vertical synchronization pulse of the television video signal, means for generating sequential pulses each identifying the video portion of a line of the vertical return interval of the television signal and fast sampling and scanning means for sampling the signals of its tablets during the intervals of sequential pulses.