FR2493085A1 - TV frame synchronising digital circuit - has output pulses of count circuit connected to resetting inputs of JK flip=flop, counter and control input of pulse forming circuit - Google Patents

Abstract

The circuit provides synchronising and blanking signals. A first counter receives clock return-line pulses and is coupled to a window generator controlling a first JK switch whose output connects with a validation or count circuit of the synchronising pulses separated from the composite video signal. Output pulses of the count circuit are fed to one of its inputs and also to zero resetting input of the JK switch and first counter as well as the control input of a pulse forming circuit for the synchronising and blanking signals, to close the window. The window generator applies to the switch a control pulse, following the first counter zero resetting, of a preset whole number of line periods less than the frame line number. The generator also applies to the count circuit a control pulse following a zero resetting of the first counter, of a preset whole number of line periods greater than the frame line number, to control zero resetting of the counter and switch, in the absence of synchronising pulses received by the count circuit, as well as the initiation of pulses from the pulse forming circuit.

Description

 The present invention relates to a frame (or vertical) synchronization circuit composed of logic elements such as counters, "AND" and "OR" gates, bistable inverters and rockers of the "JK" and "D" type, for example, and intended, in particular, to control an integrated frame-scanning circuit for a television receiver.

By television receiver is understood here an apparatus which receives, in particular, a video-composite signal comprising, during active line and frame periods, the video signal itself or the luminance signal with, optionally, at least one sub -carrier modulated by two chrominance signals simultaneously (NTSC, PAL) or alternately (5SECAM) and, during periods of erasure (or suppression called "blanking" in Anglo-American literature) of line and frame , the reference levels (black) to which are superimposed line-and-frame synchronization pulses respectively with color bursts (called "bursts" in Anglo-American literature), these synchronization pulses having a polarity opposite to that of the video signal. The composite signal can modulate (in amplitude) a high-frequency CVHF carrier wave or
UHF) or can be received in clear.

 In the vast majority of television receivers currently sold, conventional frame oscillators are generally used, self-daring on an adjustable independent oscillation frequency to be made lower than the frame frequency. This frame oscillator is synchronized using frame synchronization signals extracted from the composite video signal and for this purpose it has a large synchronization window (which may correspond to 3/5 of its autonomous oscillation period).

Due to the dispersion of the components used, this autonomous frequency must be adjustable, preferably, in a way that is accessible at least to the personnel responsible for the installation or maintenance of the receiver, and, in the United States of America, even to the viewer ("vertical hold").

In a more recent period, so-called "digital" type frame synchronization circuits have appeared, comprising, in particular, logic elements and therefore exhibiting very high stability. These circuits generally use as clock the double of the line frequency (2 FH) obtained by dividing by 16 the frequency of a signal generated by an oscillator whose oscillation frequency controlled by a phase lock loop is equal at 32 times the line frequency. These circuits are in the form of integrated circuits obtained using the technology known as 12 L (which is an abbreviation of the Anglo-American expression "Integrated Injection Logic"), to allow the inclusion of linear integrated circuits ( operational amplifiers, for example) on the same substrate. Such digital (or logical) synchronization or scanning circuits have been described, for example, in the article by COX, HENDRICKSON and MERREL entitled '| DIGITAL
VERTICAL SYNC SYSTEM "published in the American magazine IEEE
Transactions on Consumer Electronics, Vol. CE-23, NO 3, from August 1977, in the WILCOX article entitled "A HIGHLY STABLE
INTEGRATED SYNC SYSTEM "published in Vol.CE-24, NO 3, from the month of 1978 of the aforementioned review and in the application note published in June 1979, called" Linear Integrated Circuits Application Note ICAN-6802 "from the American company RCA, Solid State
Division, whose author is AUSTIN and which is entitled "A HIGH
STABILITY SYNC-AGC AND HORIZONTAL-VERTICAL COUNT
DOWN SYSTEM FOR 525-LINE COLOR TELEVISION RECEIVER
APPLICATIONS USING THE RCA CA 3154G AND CA 3157G INTE
GRATED CIRCUITS ". These circuits include, in addition to the oscillator at 32 times the line frequency, a counter whose division factor is equal to the number of lines per image (525 or 625) and use the phase comparison between the pulse of synchronization succeeding the last line of an image (525 or 625-th) and the synchronization-frame pulse extracted from the composite video signal and then formatted.

 The circuit according to the present invention makes it possible to avoid the drawbacks of the aforementioned known circuits, in particular by - being controlled by a clock at the line frequency and by not using, apart from shaping or adaptation stages upstream of its inputs, only integrated logic elements (counters, doors and flip-flops) which may be produced using less expensive technologies, such as circuits of the TTL or CMOS type, for example, due to the lower clock frequency. It may also be advantageous to use the I L technology compatible with the linear to allow the realization of a complete synchronization- and scanning-frame circuit.

 According to the invention, a digital frame synchronization circuit for television receiver, intended to supply respectively on its outputs synchronization and frame erasure pulses in the presence or in the absence of a received signal as well as during the change thereof, comprising a first divider counter with several stages of bistable rockers arranged in cascade, counting pulses applied to its clock input H, reset to zero using a signal controlling the setting circuits form of synchronization- and erase-frame pulses, is mainly characterized in that the first counter receiving on its clock input formatted return-line pulses, supplies by its parallel outputs a window generator which comprises a first set of logic doors combining these parallel outputs in order to control the opening of a window by controlling the tilting of a first JK rocker whose output feeds an input of a circuit for validating or taking into account the frame synchronization pulses separated from the composite video signal and shaped that it receives on its other input, the pulses supplied on its output being applied to the reset inputs. zero C and R and respective of the first rocker JK and the first counter as well as at the control input of the circuit for shaping the pulses at the frame frequency, so as to close the window for taking into account, that the first set of doors provides the rocker with a control pulse following a previous reset of the first counter, of a first predetermined whole number of line periods, less than the number of lines contained in a frame, and in that the first set of doors also provides another input to the input circuit with another control pulse, also following a previous reset of the first counter, of a second integer r predetermined line periods, significantly greater than the number of lines contained in a frame, in order to control, in the absence of frame synchronization pulses received on the input of the taking into account circuit, the respective resets to zero of the first counter and of the first JK rocker, as well as the initialization of the pulses supplied by the shaping circuit.

The invention will be better understood and other of its characteristics and advantages will appear from the following description and the attached drawings relating thereto, given by way of example, in which:
FIG. 1 represents a block diagram of a television receiver comprising a frame synchronization circuit according to the invention,
- Figure 2 is a more detailed block diagram of the frame synchronization circuit according to the invention;
- Figure 3 is the block diagram of an embodiment of the first set of logic gates 21 supplied by the first counter 10, of Figure 2;
- Figure 4 shows an embodiment of the circuit for shaping the synchronization and frame erasure pulses 40 of Figures 1 and 2; and
FIG. 5 schematically represents an embodiment of the resynchronization circuit 50 comprising the three detector circuits 51, 52 and 54 of FIG. 2.

 In all these figures, the same elements have been designated by the same references.

 FIG. 1 is the partial block diagram of a television receiver comprising a digital frame synchronization circuit according to the invention.

The receiver of FIG. 1 is supplied by an antenna A which, through a shielded cable C, supplies the input of a tunable high-frequency amplification stage R which with a heterodyne mixer M of which it supplies an input, and with a local oscillator L with variable frequency, which feeds the other input of the mixer M, forms the high-frequency head T or "tuner" of the receiver. The output of the mixer M feeds an intermediate frequency bandpass amplifier F which in turn feeds an amplitude detector or demodulator D whose output provides the composite video signal, on the one hand, to a video frequency amplifier Y or luminance and, on the other hand, to a circuit separating synchronization signals S. The synchronization separating circuit S receives the composite video signal in order to extract, on the one hand, line synchronization signals in the form of 'recurrent pulses at the line frequency H (15.625 or 15.750 Hz), which it supplies at its output H, and on the other hand, frame synchronization signals in the form of recurrent pulses at the frame frequency f (50 or
v 60 Hz), which it provides on its other output V. The video frequency amplifier Y supplies one of the input electrodes (cathode or grid
Wehnelt) of a CRT cathode ray tube.

 The output H of the separator circuit S supplies a first input B of a phase comparator G, a second input E of which receives other pulses at the line frequency fH coming from the line-scanning circuit and which supplies signals at its output. error as a function of the phase difference between its two input pulses. The output of comparator G feeds through an integrator J supplying the average value of the error signals, in the form of a DC error voltage, to the frequency control input of an oscillator R with frequency controllable by a voltage (called "voltage-controlled oscillator" or "VCO" in Anglo-American literature). The output of oscillator R, also called "line oscillator", feeds the attack stage N of the line scan which controls the output stage Q of the line scan.

 The cathode ray tube TRC, the screen of which provides the television image, is here of the type with electromagnetic deflection and it comprises for this purpose, mounted on its neck, line deflection coils BL and frame deflection coils BT , arranged orthogonally.

The output-line stage Q supplies, on the one hand, a circuit composed of the line-scanning coils BL and, in series with them, of a capacitor K, called "go" or "of effect S ", and, on the other hand, the primary winding of a TL transformer, called a line transformer, intended to supply using a secondary winding and a rectifier (not shown), the very high voltage at the anode of the tube
TRC. Another secondary winding U of the transformer-line
TL supplies so-called line-return pulses from which, using a first shaping circuit W, the other rectangular pulses at line-frequency are applied which are applied to the other input E of the comparator phase G.

 These pulses supplied by the circuit W also supply the first input 1 of the digital frame synchronization circuit 100 according to the invention. A second input 2 of the circuit 100 receives, via a second shaping circuit X and / or a noise gate (not shown), which can be a threshold analog voltage comparator, a positive pulse signal whose phase and frequency corresponds to the frame synchronization signal present at the output V of the separator circuit S and whose amplitude is adapted to be processed by logic circuits of the type used in circuit 100. input 3 of circuit 100, preferably also preceded by another threshold comparator Z, receives signals at two suitable logic (binary) levels indicating the switching of the integration time constant of integrator circuit J of the locking loop of phase consisting of the elements G, J, R, N, Q, TL, U and W, when changing the channel or when receiving a signal from a video recorder, for example.

 Input 1 of circuit 100 receiving the line feedback pulses shaped by circuit W, supplies the clock input 11 of a first binary counter 10, for example, in nine cascaded stages which allow it to count up to 'to 511. Its parallel outputs 13 supply the parallel inputs 204 of a circuit 20 combining the output states of the first counter 10 and composed of a set of "AND" and "OR" logic gates and a JK type bistable rocker which will be described later. This logic combination circuit 20 forms a window generator of variable width according to the desired mode of operation of circuit 100. The output 200 of the rocker JK supplies one of the inputs of a coincidence door of the "AND" type or "NGN-ET" which forms, with an "OR" or "NON-OR" gate, a circuit for taking into account or validating the synchronization-frame signals 30. To this end, the second input 32 of the circuit 30, constituting the other input of the "NAND" gate, is connected to the second input 2 of circuit 100. When no signal is received and the oscillator-line R operates autonomously, the circuit for taking into account or validation 30 would not - provide any signal on its output 342 if it did not include a third input 33 supplied by the logical combination of some of the parallel outputs 13 of the first counter 10, obtained using an "AND" gate; part of the window generator 20 which will be described in more detail later. This "AND" gate supplies the output 2û1 of the window generator 20, which is connected to a third input 33 of the circuit 30.

 This third input 33 being connected to the other input of the “OR” or “NO-YES gate of the circuit 30, the output of which constitutes that 34 of this circuit, which feeds respectively the reset inputs 12 and 202 of the counter 10 and of the 3K rocker of circuit 20 as well as one of the inputs 41 of the shaping circuit 40 of the synchronization- and erasure (suppression) pulses -frame, which makes it possible to control the tilting (towards the high state ) of two other asynchronous JK rockers which compose it.

 Consequently, the reset of the first counter 10 and of the rocker 3K of the window generator 20 as well as the switching of those of the shaping circuit 40 are controlled, silk when the synchronization-frame pulse falls inside. a window determined by the state of the output 200, or, in the opposite case, during the 340th return-line pulse counted (from the previous reset) by the counter 10 which makes appear a suitable pulse or transition on output 201 of generator 20.

 The respective durations of the synchronization and frame erasure pulses generated by the rockers 3K of the circuit 40 and respectively supplied by the outputs 43 and 44 thereof, are determined using "AND" gates controlling their reset. zero, which are also each supplied by two parallel outputs of the counter 10. These four parallel outputs represented by the reference 14, are therefore connected to four parallel inputs 42 of the shaping circuit 40.

 The modifications to the width of the windows for the various operating modes of the circuit 100 are carried out using a so-called resynchronization or catch-up circuit of the transits 50 which is relatively complex and which will be described later.

It has a first input 5 (31 connected to input 2 of the frame synchronization pulse of circuit 100, a second input 502 connected to input 3 of circuit 100 which indicates the modification of the time constant via a level Z adapter, a third input 503 connected to the output 201 of the window generator 20 supplying the 340th clock pulses and an output 504 connected to a control input 203 of the width of the window generated by this 2Q generator.

 The outputs 43 and 44 of the circuit for shaping the synchronization and frame erase pulses 40 are respectively connected to the outputs 5 and 6 6 of the digital type frame synchronization circuit 100, in accordance with the invention. Ea output 3 supplying the frame synchronization pulses generated by the latter, feeds by rectangular signals a frame (or vertical) scanning circuit 7 composed in cascade of a generator of recurring waveforms in a serrated form (corrected) at the frame frequency 8 and an output amplifier (power) 9, the two outputs of which are respectively joined to the two terminals of the LV deflection-frame coils. When the circuit 100 is produced by the aforementioned I2 L technology, the circuit scanning frame 7 comprising linear elements, can be integrated on the same substrate as the first.

 FIG. 2 represents a somewhat more detailed block diagram of an embodiment of the digital (or logic) frame synchronization circuit 100, according to the invention.

 In FIG. 2, the clock input 11 (H) of the first counter 10 is supplied by pulses at the line frequency shortly after the receiver is powered up, even in the absence of a composite video signal received, because then the line oscillator (R in FIG. 1) operates autonomously (not controlled). The parallel outputs i3 of the first counter 10 respectively supply the parallel inputs 204 of the window generator 20, which constitute those 210 of a first set of logic gates ("AND" and "OR") 21 making it possible to develop various rectangular signals whose beginnings correspond respectively, in the case of European standards (such as the CCIR variant B or G, French or L, Belgian or C , British or I, OIRT or D) which are at 625 lines per image, to those of the 200th, 3 (10th, 340th lines consecutive to a reset pulse applied to its input 12 reset zero (li), for example. Obviously other choices can be made by as regards the different widths of the synchronization windows, which would lead to different arrangements of the doors and / or their interconnections with one another and with the outputs 13 of the first counter 10, accessible to those skilled in the art.

 Thus, in normal operation in the presence of the frame synchronization pulses and with the line oscillator (R in FIG. 1) slaved to the line synchronization pulses by the phase locking loop (G, J, R, N, Q, TL, W of FIG. 1), the output 211 of the first set of doors 21 provides the high state input 220 (S) of the JK type bistable rocker 22 with a pulse whose start corresponds to that of the 300th clock pulse (line return) following the reset of the first counter 10. The Q output 222 of the rocker 22 then provides a logic "high" state which, applied through the output 200 and the input 31 of the validation circuit of the synchronization-frame signals 30, feeds one of the inputs of an "AND" gate 35 of which the other input receives the synchronization-frame pulses 7 through the second inputs 2 and 32 respectively of circuits 100 and 30. The output of the door "ET'2 35 is connected to one of the inputs of a door" OR " 36 whose output constitutes that 34 of circuit 30 which is connected in parallel, via input 202 of window generator 20, to reset input 221 (C) of rocker 22, to that 12 (R) of the first counter 10 and at the control input 41 of the circuit 40.

Consequently, the counter 10 and the rocker 22 are reset to zero each time a frame synchronization pulse is present following the opening of the window during each 300th th line-return pulse following the pulse of synchronization previous frame. This reset causes the window to close by applying the low state which causes the output 222 (Q) of the rocker 22 to appear at one of the inputs of the "AND" gate 35, half a period of line after the start of the 312th line pulse, that is to say that its normal duration is 12.5 line periods (0.8 milliseconds), so that no subsequent pulse or transition (parasitic) can be transmitted by the recognition circuit 30 at its output 34, until the next 300th return line pulse which will reopen the window.

 When the frame synchronization pulse is no longer received on input 2 of the circuit 100, the taking into account circuit 30 must obligatorily supply recurrent pulses commanding the reset of the first counter 10 and of the rocker 22 and the circuits of shaping of the synchronization- and erasure-frame pulses 40 so that the spot does not permanently scan the same line which could damage the screen of the TRC tube composed of one or more phosphors.

 To this end, the set of logic gates 21 of the window generator has a second output 212 which, by combining several of the parallel outputs 13 of the first counter 10, provides a pulse corresponding to the 340th line following the reset. previous counter 10 and rocker 22. This second output 212 is connected, via the second output 201 of the window generator 20 and the third input 33 of the validation circuit 30, to! 'other input of the door "OR" 36. We thus obtain that the opening of the window (narrow) provided for normal operation lengthens from the 300th to the 340th return pulse line (that is to say, it then extends over 40 lines whose duration is approximately 2.6 milliseconds). In the event of untimely loss of frame synchronization, such a "narrow" window would require a high number of frames to find it. It is therefore necessary in this case to widen the window to speed up the catching up with frame synchronization in a few frame intervals (less than 10). This is the role of the resynchronization circuit 50.

 Certain current television receivers, in particular those at the top of the deck, provided with a device for modifying the integration time constant of the integrator circuit J of FIG. 1, inserted between the output of the phase comparator G of FIG. 1 and the frequency input of the frequency adjustable oscillator ("VCO") R of Figure 1. This modlficatlnn (reduction) of the time constant can be done temporarily, on the one hand, automatically when a program change (channel or received channel) on the "tuner" T of FIG. 1 and, on the other hand, during the periods of frame erasure, when receiving a video signal composite provided by a VCR where line-and-frame synchronization signals can be disturbed due to the transition from one read head to another. Besides, when switching from receiving a broadcast signal to that of a signal from a VCR, it is common to switch (by manual control, for example) the response curve of the integrating circuit permanently, which implies not only a modification (reduction) of the time constant, but also that (increase) of the gain of the locking loop phase so that the line oscillator can better follow the irregularities (frequency modulation of line synchronization) inherent in the reproduction of a signal recorded on magnetic tape. Such a process has been described, for example, in French patent application NO E.N. 80 00612 of January 11, 1980 of the applicant.

The digital frame synchronization circuit 100 of the present invention comprises for this purpose an input 3 receiving from the time-line base integrated circuit, for example, of the type
TBA 920, through an adapter stage Z (of FIG. 1), a transition between two logic states indicating the switching of the time constant. This transition can possibly be provided by means of the signal which controls this switching. These different transitions between a high state and a low state (or the reverse) are applied to the input 502 called 9 'of time constant' of the circuit for catching up or resynchronizing the transients 50, from which they are transmitted to an input 510 (here constituted by the data input D of a type D rocker) of a first circuit for recognizing or detecting the switching of the time constant 51 which will be described later and whose other input 511 (constituted by the clock input H of the same rocker D) is connected to the output 15 of the first counter 10 (which is constituted by the QO output of the first bistable rocker of type D, for example, of which it comprises several, combined in cascade) which supplies square signals at the line half-frequency.

 The high logic state representing, for example, the synchronized operating mode (continuous reception of a broadcast or cable transmitted program) and the low state then representing the non-synchronized and "VCR" operating modes, the first circuit for detecting the change of the time constant 51 is arranged so as to provide a pulse on its output 512 when it receives a transition between two states on its input 502 and to provide no signal when there is no no change of state.

When there is a change of program chosen by the viewer (channel or channel switching), there is also a transient desynchronization which temporarily involves the autonomous oscillation of the line oscillator (R in Figure 1) by l opening of the phase locking loop and the absence of a frame synchronization signal at input 32 of the validation circuit 30. The first circuit for detecting the switching of the time constant 51 then does not provide any signal, it is necessary to provide another circuit for detecting or recognizing the absence or loss of synchronization on a received broadcast signal. This is done using a second loss of synchronization detection circuit 52, one of which first input 520 which is constituted by the input for controlling the tilting (S) of a bistable rocker of the JK type and which is preceded by an "AND" gate 53, one input of which receives input 502 from circuit 50 ' information of the change of the time constant and the other input of which receives from the second output 212 of the set of logic gates 21, through the output 2û1 of the generator 20 and the third input 503 of the circuit 50, pulses corresponding to each 340th return line pulse. These pulses are not transmitted to the input 520 (S) of the second circuit for detecting the loss of synchronization 52 until the input for changing the time constant 3 provides a high state indicating that one is operating in synchronized mode. . A second input 521 (formed by two clock inputs H, one of which is complemented by two rockers D cascaded with the rocker JK whose output
Q supplies input D of the first) of circuit 52 is also connected to output 15 (QO) of first counter 10 to receive clock pulses at the line half-frequency. Circuit 52 is arranged so as to supplying a pulse at its output 522, when simultaneously the frame synchronization pulse is absent and the indication corresponding to the time constant is constituted by a high state, because in the presence of frame synchronization pulses, the first counter 10 is reset to zero by the latter before it can produce a 340th pulse on the output 201 of the generator 20.

 A third circuit for detecting or recognizing the source of the signals from a video recorder 54 is arranged in a similar manner to the circuit for detecting loss of synchronization 52, except for the nature of the information applied to the input of another "AND" gate 55 which supplies the first input 540 (S) of this circuit 54. In the event of reception of signals coming from a video recorder, one of the inputs of the other "AND" gate 55 is coupled, via the first input 501 of the resynchronization or catch-up circuit 54, to the second input 2 of the frame synchronization circuit 100, which receives the separate synchronization-frame pulses (by the separator circuit S of FIG. 1 ) and shaped (by the level adapter circuit or threshold comparator X in FIG. 1).

 The other input of this other "AND" gate 55 is joined, via a fifth input 506 of the circuit 50, to a fourth input 4 of the frame synchronization circuit 100, which receives a high state when the signal received from a VCR and low for all other sources. The outside input 541 (H) of circuit 54 is connected to those 511 and 521 of the other two detection circuits 51 and 52 to receive square line frequency half-frequency signals from output 15 (QO) of the first counter 10.The output 542 of the third detection circuit 54 then supplies, when the other input of the other "AND" gate 55 receives a high state (+ 12 V, for example), a pulse corresponding to the first frame synchronization pulse from the video recorder, which follows the appearance of a high state - on input 4 of circuit 100.

The outputs 512, 522, 542 of the three detector circuits respectively supply three inputs of an "OR" gate 56 which transmits the pulses respectively supplied by one or the other of these, to the reset input 570 ( R) a second binary counter 57 of four stages ("bits") composed of four rockers (of the
D, for example) in cascade. The clock input 571 (H) of the second counter 57 is supplied, through a sixth input 507 of the circuit 50 and a third output 204 of the window generator 20 by a rectangular signal whose start corresponds to that of the 300th return line pulse following the resetting to zero of the first counter 10 taken from a third output 213 of the first set of logic gates 21, for example, or, possibly, from the first input 220 (S) or the output 222 (Q) of the rocker JK 22 of the generator 20.

 The parallel outputs 572 (po, Q1 'Q2 Q3) of the second binary counter 57 are combined by means of a second circuit of logic gates 58 which is arranged so as to provide on its first output 580 a binary signal whose high level has a duration equal to an integer N of frame periods which can be chosen equal to seven. This first output 580 of the second gate circuit 58 provides a low level before the first pulse applied after the reset of the second counter 57 and after the expiration of the N = 7 frame periods, or even when none of the three detector circuits 51, 52 and 53 provides a reset pulse at its reset 570 (R) input, through the "OR" door 56.

The setting 580 is joined, via the output 504 of the circuit 50 and the second input 203 of the generator 20, to the input 214 of the first set of doors 21 which is, moreover, arranged so as to provide, when it receives a high state on its aforementioned input 214, on its output 211 connected to input 220 (S) of the rocker JK 22 and controlling the opening of the window, pulses corresponding to each 200th return pulse line following the resetting of the first counter 10. In this way, in the event of absence of synchronization, modification of the time constant or reception of a signal from a video recorder respectively detected using of the three detector circuits 51, 52 and 54, a temporary widening of the window for capturing the frame synchronization signal applied to the input 32 of the circuit 30 is taken into account for N = 7 consecutive frame periods. enlarged, called catch-up, spans 140 periods of line (64 microseconds each) going from the 2QQ-th to the 340-th line-return pulse, that is to say that it lasts approximately 9 milliseconds during these N = 7 frame periods (the number of which is determined by the division factor produced by the combination of the second counter 57 with the second circuit of doors 58). In the absence of frame synchronization pulses at input 2, the duration of a frame is 340 line periods which are themselves, in the absence of line synchronization signals, generally at least slightly longer than in the mode slaved (64 microseconds). We can then estimate that a frame period during catch-up or in non-slaved mode (non-synchronized) has a duration of approximately 22 milliseconds (against 20 milliseconds in slaved mode). Because the widened catch-up window represents a large proportion of the frame period (40 percent) and the frequency of the frame synchronization pulses of 50 Hz is greater than the autonomous frame frequency generated by circuit 100 which is about 45 Hz, the probability is high that a first frame synchronization pulse will occur during one of the widened catch-up windows of a low N (integer) number of frames
Experience has shown that seven frames give a sufficient probability, especially since the second circuit 52 intended to recognize the loss of frame synchronization, has a third input 523 of its reset (C) enabling it to be reactivated. so as to be able to start again by supplying a reset pulse to the second counter 57, a new catch-up period of N = 7 frames, if the frame synchronization pulses have not yet been found inside an enlarged window from a previous catch-up period. To this end, the second door circuit 58 includes a second output 581 which supplies this reset input 523 (C) of the second detector circuit 52, to reset it at the end of each catch-up period of N = 7 frames.

 With regard to operation in "video recorder" mode, it should be noted here that the third reset input 543 (C) of the third circuit for detecting the source of the signal from a video recorder 54, is supplied, for example , through the third input 503 of the circuit 50 and the output 201 of the generator 20, by the output 212 of the set of logic gates 21, providing the 340th pulse following the previous reset to zero of the first counter 10 so as to be able to be reactivated whenever the frame synchronization pulse is absent or occurs after the 340-line. This can occur, for example, when switching from one program recorded to another on the same VCR or when '' a passage, even chained, from one VCR to another already running, without synchronization with the first, but without significant interruption of the arrival of the composite video signal.

In Figure 3, there is shown schematically the first set of logic gates 21 intended to cooperate with the first counter 10 whose clock pulses applied to its clock input 11 (H), are constituted by the return pulses- line shaped by the circuit W of FIG. 1. Of the set of parallel outputs 13 which are those of the nine stages in cascade (QO to Q) three QOs Q1 and Q4 are connected only to the parallel inputs 42 of the circuit 40 with a fourth Q2, to make it possible to determine the respective durations of the synchronization- (4 TH = 256 microseconds) and frame erase (22 TH = 1.4 milliseconds) pulses from the start of the synchronization pulse -frame validated by circuit 30 or of the 340th return-line pulse succeeding the previous reset pulse of the first counter 10, also applied to
The control input 41 of the shaping circuit 40, which will be explained later.

This set of logic gates 21 comprises a first "AND" gate 215 with three inputs which are respectively connected to the outputs Q2, Q5 and Q8 of the counter 10 to supply on its output pulses whose beginnings coincide with those of the 3c0-th pulses of line return and the duration of which is that of the signals supplied by the Q2 output, that is to say four line periods (256-s). The output of the first "AND" gate 215 supplies, on the one hand, one of the inputs of an "OR" gate 216 with two inputs, the output of which is connected through the first output 211 of circuit 21, to the trigger input 220 (S) of the 3K rocker switch 22 of the window generator 20 which controls the start of the latter. The other input of the door '! OR "216 is supplied by a second door" AND "217 å four inputs three of which are respectively connected to the outputs
Q6 and Q7 of the first counter 10 and, via the input 203 of the generator 20 and the output 504 of the resynchronization or catch-up circuit 50, to the output 580 of the second door circuit 58 of FIG. 2, which provides a high state during N = 7 frame periods to allow the second "AND" gate 217 to supply during this catch-up time interval pulses (seven) whose start coincides with that of the 200th return-line pulse and whose duration is also four line periods (Q2).

 The output 211 of the assembly 21 connected to that of the "OR" door 216, therefore supplies pulses controlling the opening of the window supplied by the output 222 (Q) of the rocker JK 22, that is to say every 300th return pulse. line, or in addition every 200th, after one of the three detectors 51, 52 and 54 of FIG. 2 has commanded the resetting of the second binary counter 57 of FIG. 2.

 The first set of doors 21 further comprises a third "AND" door 218 with three inputs which are respectively connected to the outputs Q2, Q6 and Q8 of the first counter 10. It is this third "AND" door which supplies pulses of duration equal to four line periods (thanks to Q2) and the beginnings of which coincide with each 340th return-line pulse following resets of the first counter 10, which they control themselves in the absence of pulses frame synchronization for the duration of the high state at the output (Q) 222 of the rocker 22, which constitutes the window.

 In Figure 4, there is shown schematically an embodiment of the circuit 40 for shaping the synchronization- and erase-frame pulses. This circuit 40 includes two JK type rockers 45 and 46, the respective Q outputs of which supply the pulses at the above-mentioned frame frequency.

Their control inputs S (switching from the low state to the high state) are connected in parallel to the first input 41 of the circuit 40 from which they receive either, in synchronized mode, the validated frame synchronization pulses, either in non-synchronized mode, the pulses the start of which coincides with that of each 340th return-line pulse following the resetting to zero of the first counter 10. The pulses controlling the tilting of the two rockers JK 45 and 46 determine the start of the synchronization- and erase-frame pulses which they supply respectively to the outputs 43 and 44 of the shaping circuit 40.

 The second parallel inputs 42 consist of four inputs 421 to 424, the first two of which 421 and 422 are connected to the first two 140 and 141 between the four derivative outputs 14 of the counter 10. These two derivative outputs 141 and 140 are respectively joined to outputs QO and Q1 of the first counter 10 and the first two inputs 421, 422 are respectively connected to the two inputs of a first AND gate "47" whose output is connected to the reset input C of the first rocker 45 for obtain a duration of the frame synchronization pulse equal to four line periods. The other two second inputs 423 and 424 respectively bring together the two inputs of a second "AND" gate 48 with two inputs, via two second derivative outputs 142, 143, at the outputs Q2 and Q4 of the first counter 10, in order that the duration of the frame erase pulses is twenty-two line periods.

 FIG. 5 is the more detailed block diagram of an embodiment of the resynchronization or catch-up circuit 50 forming part of the digital frame synchronization circuit 1011 according to the invention and making it possible to modify the width of the window, when the integration time constant is modified, when the frame synchronization pulse has just failed, when going from a broadcast program to a program recorded on a video recorder or when there is a change of program recorded in " video recorder ". The three detection circuits 51, 52 and 54 as well as the second door circuit 58 have been shown in detail therein in order to enable an advantageous embodiment to be described.

The first time constant switching detector 51 has its two inputs 510 and 511 respectively supplied by a two-level signal from input 3 (a transition between two levels corresponding, for example, to a change of channel) and a square line half-frequency signal from output 15 (QO) of the first counter îC, respectively connected to the D and clock H data inputs of a first bistable D 513 type rocker The output Q of the first rocker D 513 is connected in parallel to input D of a second rocker D 514 and to one of the inputs of a first "AND" door 515 with two inputs, the other input of which is connected to the co-output second bed of the second rocker
D 514. The clock input H of the latter is connected to the output of a logic inverter 516 whose input is connected to the second input 511 of the circuit 51. The complementary output Q of the first rocker D 513 and the output Q of the second 514 are respectively connected to the two inputs of a second "AND" door 517 The outputs of the two "AND" doors 515 and 517 are respectively connected to the two inputs of an "OR" door 518 whose output is connected to that 512 of circuit 51.

 When the first input 510 receives a transition between two logic states (levels), the positive transition of the square signal provided by the output 15 of the counter 10 which follows it switches the first rocker 513 whose Q output will then be in the same state as its input D. This output Q supplying the input D of the second rocker 514 whose input H receives the complementary square signal, this will switch to the same state as the first 513 with a delay of a line period .The two "AND" doors 515 and 517 being respectively supplied by the output Q of one and the complementary output Q of the other of the two rockers 513, 514, it follows that one of them provides a pulse a line period at each change of state at input 510 (or 502 or 3), which is transmitted by the "OR" gate 518 at output 512.

 The second circuit for detecting loss of synchronization 52 and the third circuit for detecting the switching of the program to a video recorder or between two of the latter 54 are respectively arranged in an analogous manner but receive different signals on some of their inputs.

 One of the inputs 520 of the second circuit 52 is preceded by the third "AND" gate 53 mentioned above, one input of which is connected to the input 502 receiving the switching signal of the time constant indicating by a high level an operation in synchronized mode and the other input of which receives from the input 503 connected to the output 201 of the window generator 20 (FIGS. 1, 2 and 3), the 34th pulse at the line frequency. If the latter coincides with a high state on the other input of the "AND" gate 53, the latter transmits at its output this 340th pulse. The output of this "AND" gate 53 is connected to the control input 520 for switching to its high state (S) of a first rocker of the JK 524 type, the Q output of which feeds the D input of a third rocker. D 525.

The clock input 521 H of the latter is connected to the input 505 of the circuit 50 receiving the square signals at the line half-frequency.

The output Q of the third rocker D 525 is connected in parallel to the input D of a fourth rocker D 526 and to one of the two inputs of a fourth "AND" gate 527. The clock input H at fourth rocker D 526 is connected through the input 528 of the circuit 52 to the output of the inverter 516 to receive the complementary square signals. The other input of the fourth "AND" gate 527 is connected to the complementary output Q of the fourth rocker D 526 and its output to that 522 of the circuit 52.

 When the third "AND" gate 53 transmits the 340th pulse to the input S of the first rocker JK 524, the latter switches to its high state if it was not there before. The output Q of the first rocker JK 524 then supplies the input D of the third rocker D 525 with a high state in order to make it switch from its low state to its high state upon arrival of the next positive transition of the square signal applied to its clock input H. Its output Q then provides a high state to one of the inputs of the fourth "AND" gate 527 and to the input D of the fourth rocker D 526. As the latter receives on its input H the complementary square signals to switch from its low state to its high state a line period later, its complementary output Q continues to provide a high state during a line period after the switching of the third 525.

The fourth gate 527 will then supply a pulse of duration of a line period at the output 522. The reset 9 zero of the first JK rocker 524 is effected by the input 523 of the circuit 52 connected to its input C, using of the other door circuit 58 which combines the states of the second counter 57, so that it can be switched back after the end of the catch-up period of N = 7 frames.

This reset subsequently leads to those of the third and fourth rockers D 525 and 526, during the first respective positive transitions of the square clock signals, one of which is complementary to the other.

 One of the inputs 540 of the third VCR switching detection circuit 54 is preceded, likewise by a fifth "AND" gate 55 connected to the input S of a second rocker JK 544, a fifth and a sixth rocker D 545 and 546, a sixth "AND" gate 547. These two D rockers 545 and 546 also receive the same complementary square clock signals respectively applied to the inputs 541 and 548 of the circuit 54.

One of the inputs of the fifth "AND" gate 55 is connected to the input 501 of the circuit 50, which receives the frame synchronization pulses directly from the input 2 of the circuit 100 (FIG. 1). The other input of the fifth "AND" gate 55, connected to input 506 of the SU circuit, receives by input 4 a high level (state), when the signal comes from a video recorder. The third 3K rocker 544 is reset to zero by means of the 340th pulses through inputs 543 and 503, connected to its input C. These reset pulses are only supplied in the absence of pulses synchronization frame which normally control the resets to zero of the first counter 10 after the 312th pulses.

 The pulses supplied by the three detector circuits 51, 52 and 54 are added by the "OR" gate 56 to serve for resetting the second counter 57 which counts the 300th pulses supplied to its clock input 571 (Ho ) at the frame frequency by the output 204 of the window generator 20 (Figures 1, 2 and 3).

 Three Q1 'Q2' Q3 of the four parallel outputs 572 of the second counter 57 are respectively connected to three inputs of a seventh "AND" gate 582 forming part of the second gate circuit 57 and the output of which is directly connected to the output 581 and , via a second inverter 583, at the output 580 of the circuit 58, which connected to that 504 of the circuit 50, supplies the input 203 of the window generator 20 (i.e. one inputs of the second "AND" door 217 of the first set of doors 21 in FIG. 3, which makes it possible to supply the 200th pulses in order to obtain the enlarged catch-up window).

It can be envisaged to use pulses other than 300ths for the opening of the narrow window, the 200ths for
that of the enlarged window and the 340ths for its closure and for the autonomous frame synchronization, in the absence of received signals and another number N of frame periods for catching up.

For this it would be necessary to use different connections between the doors of the assembly 21 of Figures 1, 2, 3 and the parallel outputs 13 of the first counter 10 and another arrangement of the second counter 57 in conjunction with that of the second circuit of doors 58.

However, such variants as well as the adaptation of the circuit 100 to other standards, are accessible to those skilled in the art and, therefore, do not depart from the field of the present invention.

 To produce such a frame synchronization circuit, commercially available integrated circuits can be used, such as for the first counter 10, the 12-stage binary counter of type 4040 B, for the second counter 57, the binary counter at 4 bits of type 4520 B and for JK rockers type 4027 B produced in CMOS technology by the American company FAIRCHILD, for example.

 By using these logic gates otherwise and / or other types of logic gates to combine the output signals from the first counter 10, it is possible to obtain sampling control signals in a sampling frame-scanning circuit or in switched mode.

Claims (12)

 1. Digital frame synchronization circuit (100) for television receiver, intended to supply respectively on its outputs (5, 6) synchronization- and blanking-frame pulses in the presence or absence of a signal thus received that during the change thereof, comprising a first divider counter (11) with several (P) stages of bistable rockers arranged in cascade, counting pulses applied to its clock input H (11), reset to zero using a signal controlling the circuits for shaping the synchronization and frame erasure pulses (40), characterized in that the first counter (10) receiving at its input clock of the return-line pulses shaped, feeds by its (P) outputs (13) parallel (QO to Qp 1) a window generator (20) which comprises a first set of logic gates (21) combining these parallel outputs in order to control the opening of a window by controlling the tilting of a first 3K rocker (22) whose Q output (220) feeds an input (31) of a validation or taking into account circuit frame synchronization pulses (30) separated from the composite video signal and shaped that it receives on its other input (32), the pulses supplied on its output (34) being applied to the zero reset inputs R (221 and 12) respective of the first JK rocker (22) and the first counter (19) as well as at the control input (41) of the circuit for shaping the pulses at the frame frequency (40), so as to close the window for taking into account, in that the first set of doors (21) provides the rocker (22) with a control pulse succeeding a previous reset of the first counter (10), of a first predetermined whole number (n) of line periods, less than the number of lines contained in a frame, and in that the first set of doors (21) provides , in addition, at another input (33) of the taking into account circuit (30) another control pulse also succeeding a previous reset to zero of the first counter (10), of a second predetermined whole number (p) line periods, significantly greater than the number of lines contained in a frame, in order to control, in the absence of frame synchronization pulses received on the input (32) of the taking into account circuit (30), the respective resets of the first counter (10) and of the first 3K 22 rocker, as well as the initialization of the pulses supplied by the shaping circuit (40).  2. frame synchronization circuit according to claim 1, characterized in that it further comprises a resynchronization or catch-up circuit during a loss of synchronization (50) comprising at least one detector circuit (51, 52 and 54) intended to detect either a switching of the time constant of the integration into the phase lock loop of the oscillator-line, or a loss of synchronization-frame, in particular, on television programs, or the source of the signal from a video recorder, this detector circuit (51, 51, 54) receiving from one (15) parallel outputs (13) of the first counter (10) square clock signals whose frequency is a sub- multiple of the line frequency, in order to provide an output pulse, when the phenomenon which it is supposed to detect occurs, in that the resynchronization circuit (50) further comprises a second binary counter with several (M, integer) stages (5) including the reset input R (570 ) receives the pulses supplied by the detector circuit (51, 52, 54), whose clock input H (571) receives counting pulses at the frame frequency supplied by one of the outputs (213) of the first set of logic gates (21) supplied by the parallel outputs (13) of the first counter (10), and whose parallel outputs (572 or Q to Q4) respectively supply the inputs of a second circuit of doors (58) combining the signals provided by the second counter (57) so as to provide, from the resetting of the latter, a slot whose duration is equal to a predetermined number (N) of frame periods, and in that this slot is applied to the input of one of the "AND" doors (217) contained in the first set of doors (21) so as to supply control pulses to the input S (220) of the first rocker JK 22 which follow the resetting to zero of the first counter (10) of a third number (q) of line periods less than the first (n), fa Lesson to widen the window during the N periods of catch-up frame.  3. frame synchronization circuit according to claim 2, characterized in that the re-synchronization circuit comprises three detector circuits (51, 52 and 54), the first of which (51) detects the switching of the time constant, the second of which ( 52) detects the loss of synchronization, in particular, on broadcast signals and the third (54) of which detects the source of the signal from a video recorder and provides a pulse triggered by the first synchronization-frame pulse contained in this signal, the output signals of three detector circuits (51, 52, 54) being added using an "OR" gate (56) and applied to the reset input R (570) of the second counter (57) to initialize the catch-up slot of N frame periods.  4. Frame synchronization circuit according to one of the preceding claims, adapted to the standard of 625 lines per image and 50 frames per second, characterized in that the first number of line periods (n) elapsed following a reset of the first counter (10) to initialize the opening of the narrow window in synchronized mode, is equal to 300, in that the second number of line periods (p) elapsed following this same reset to control, in the absence of frame synchronization signals, the closing of the window by resetting the first 3K rocker (22), that of the first counter (10) and the initialization of the synchronization pulses -and d 'eraseframe, is equal to 340.  5. frame synchronization circuit according to one of claims 2 to 4, characterized in that the third number (2) of line periods elapsed from a previous reset to the first counter (10) to initialize l The opening of the widened window for catching up or resynchronization is equal to 200.  6. frame synchronization circuit according to one of claims 2 to 5, characterized in that the duration of the catch-up slot is chosen equal to seven frame periods.  7. Frame synchronization circuit according to one of claims 2, 3, 5 and 6, characterized in that each of the three detector circuits (51, 52 and 54) comprises a circuit for detecting a transition between two logic states composed of two D-type rockers (513 and 514 525 and 526, 545 and 546) the first of which (513, 525, 545) has its data input (D) connected to an output (502, Q) providing this transition and its clock input (H) supplied by a first square signal supplied by one of the outputs (15) of the first counter (10), the frequency of which is a submultiple of the line frequency, and the second of which ( 514, 526, 546) has its data input (D) connected to the output (Q) of the first (513, 525, 545) and its clock input (H) supplied by a second square signal complementary to the first, and a first door "ET1, (515, 527, 547) supplied respectively on its two inputs by the output (of the first rocker (513, 525, 545) and by the complementary output (i) of the second (514, 526, 546) and providing on its output a first pulse whose duration is equal to half a psriode of the two square clock signals and whose start coincides with the first positive transition of the first square signal, consecutive to a positive transition applied to the data input CD) of the first rocker (513, 524, 544).  8. frame synchronization circuit according to claim 7, characterized in that, in the circuit for detecting a transition of the first circuit detecting the change in the time constant (51), the complementary output (Q) of the first rocker D (513) supplies, in addition, one of the inputs of a second nET "gate (517), the other input of which is supplied by the output (Q) of the second (514) and the output of which provides a second pulse the duration of which is equal to half a period of the two square clock signals and the start of which coincides with the first positive transition of the first square signal, following a negative transition applied to the data input (D) of the first rocker (513) and in that it further comprises an "OR" door (518), the two inputs of which are supplied respectively by the outputs of the two "AND" doors (515 and 517) and the output of which provides either a first, or a second pulse of analogous forms in response to a transition p ositive or negative applied to the data input (D) of the first D rocker (512).  9. Synchronization circuit according to claim 7, characterized in that the second and the third detector circuit (52, 54) further comprises a JK type asynchronous bistable rocker (524, 544) whose control input ( 520, 540) of the switching from a low state to a high state (S) is supplied with control pulses determining the respective detection criteria and the output (Q) of which constitutes that providing the positive transition to the data input ( D) of the first rocker D (525, 545).  1U. Synchronization circuit according to claim 9, characterized in that the control pulse of the 3K rocker (524, 544) is supplied by means of another "AND" gate (53, 55) with two inputs.  11. Synchronization circuit according to claim 10, characterized in that the other "AND" gate (53) of the second loss of synchronization detector circuit (52) is supplied to one of its inputs by pulses whose beginnings correspond to those of the commanding pulses, in the absence of frame synchronization pulses received, in particular the closing of the window by resetting the 3K rocker switch (22) of the window generator (20), and on its other input by a first two-level signal indicating the change in the time constant, the high level of which indicates that the line oscillator (R) is operating in synchronized mode, in particular, when receiving a broadcast signal, the reset input to zero (C) of the JK rocker (524) of this circuit (52) being supplied by one (581) of the outputs of the second door circuit (58) to control its reset at the end of each interval of catching up of N frames.  12. Frame synchronization circuit according to claim 10, characterized in that the other "AND" gate (55) of the third circuit detecting the source of the video signal received from a video recorder (54) is supplied on one of its inputs by the frame synchronization signal separated by a separator circuit, its other input being supplied by a high level, when the video signal comes from a video recorder and by a low state for any other source, resetting the 3K rocker (544) of this circuit (54) being controlled by pulses whose beginnings correspond to those of the commanding pulses, in the absence of synchronization-frame pulses received, in particular the closing of the window by resetting to zero of the 3K rocker (22) of the window generator (20) in order to provide on its output (542) a single pulse, during the first synchronization-frame pulse originating from the reading of a magnetic tape carrying a video signal recorded composite , provided by a video recorder, after the application of a high state on the other entrance of the other door (55).  13. Television receiver, characterized in that it comprises a digital frame synchronization circuit according to one of the preceding claims, which supplies it with frame synchronization pulses controlling its frame scanning circuit (7, 8, 9 and BT) and frame erase pulses applied to its cathode ray tube (CRT).