FR2480531B1 - - Google Patents
Info
- Publication number
- FR2480531B1 FR2480531B1 FR8008391A FR8008391A FR2480531B1 FR 2480531 B1 FR2480531 B1 FR 2480531B1 FR 8008391 A FR8008391 A FR 8008391A FR 8008391 A FR8008391 A FR 8008391A FR 2480531 B1 FR2480531 B1 FR 2480531B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
- H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8008391A FR2480531A1 (fr) | 1980-04-15 | 1980-04-15 | Dispositif d'adaptation de niveau de signal d'entree, et circuit logique comportant un tel dispositif |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8008391A FR2480531A1 (fr) | 1980-04-15 | 1980-04-15 | Dispositif d'adaptation de niveau de signal d'entree, et circuit logique comportant un tel dispositif |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2480531A1 FR2480531A1 (fr) | 1981-10-16 |
| FR2480531B1 true FR2480531B1 (enExample) | 1984-02-17 |
Family
ID=9240882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR8008391A Granted FR2480531A1 (fr) | 1980-04-15 | 1980-04-15 | Dispositif d'adaptation de niveau de signal d'entree, et circuit logique comportant un tel dispositif |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2480531A1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8301711A (nl) * | 1983-05-13 | 1984-12-03 | Philips Nv | Complementaire igfet schakeling. |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3749936A (en) * | 1971-08-19 | 1973-07-31 | Texas Instruments Inc | Fault protected output buffer |
| US4039862A (en) * | 1976-01-19 | 1977-08-02 | Rca Corporation | Level shift circuit |
| JPS5516539A (en) * | 1978-07-20 | 1980-02-05 | Nec Corp | Level shifter circuit |
-
1980
- 1980-04-15 FR FR8008391A patent/FR2480531A1/fr active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2480531A1 (fr) | 1981-10-16 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |