FR2435758B1 - TWO-PHASE MICROCALCULATOR COMMUNICATION LOGIC - Google Patents

TWO-PHASE MICROCALCULATOR COMMUNICATION LOGIC

Info

Publication number
FR2435758B1
FR2435758B1 FR7918967A FR7918967A FR2435758B1 FR 2435758 B1 FR2435758 B1 FR 2435758B1 FR 7918967 A FR7918967 A FR 7918967A FR 7918967 A FR7918967 A FR 7918967A FR 2435758 B1 FR2435758 B1 FR 2435758B1
Authority
FR
France
Prior art keywords
microcalculator
phase
communication logic
logic
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7918967A
Other languages
French (fr)
Other versions
FR2435758A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/939,742 external-priority patent/US4361876A/en
Priority claimed from US05/939,743 external-priority patent/US4346452A/en
Priority claimed from US05/939,744 external-priority patent/US4222116A/en
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of FR2435758A1 publication Critical patent/FR2435758A1/en
Application granted granted Critical
Publication of FR2435758B1 publication Critical patent/FR2435758B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
FR7918967A 1978-09-05 1979-07-23 TWO-PHASE MICROCALCULATOR COMMUNICATION LOGIC Expired FR2435758B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US05/939,742 US4361876A (en) 1978-09-05 1978-09-05 Microcomputer with logic for selectively disabling serial communications
US05/939,743 US4346452A (en) 1978-09-05 1978-09-05 NRZ/Biphase microcomputer serial communication logic
US05/939,744 US4222116A (en) 1978-09-05 1978-09-05 Digital logic for separating data and clock in Manchester-encoded data

Publications (2)

Publication Number Publication Date
FR2435758A1 FR2435758A1 (en) 1980-04-04
FR2435758B1 true FR2435758B1 (en) 1986-08-22

Family

ID=27420694

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7918967A Expired FR2435758B1 (en) 1978-09-05 1979-07-23 TWO-PHASE MICROCALCULATOR COMMUNICATION LOGIC

Country Status (5)

Country Link
DE (1) DE2935847A1 (en)
FR (1) FR2435758B1 (en)
GB (1) GB2029172B (en)
MY (1) MY8500476A (en)
SG (1) SG16684G (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216674A (en) * 1989-02-17 1993-06-01 Robert Bosch Gmbh Method of and device for bringing a network interface out of a sleep mode into a wake-up state
FR2706650B1 (en) * 1993-06-11 1995-08-04 Renault Method for decoding the header of a communication message.
JP7070496B2 (en) * 2019-04-24 2022-05-18 オムロン株式会社 Serial data communication equipment

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699525A (en) * 1970-11-27 1972-10-17 Honeywell Inf Systems Use of control words to change configuration and operating mode of a data communication system
US4071887A (en) * 1975-10-30 1978-01-31 Motorola, Inc. Synchronous serial data adaptor

Also Published As

Publication number Publication date
GB2029172A (en) 1980-03-12
GB2029172B (en) 1982-12-22
FR2435758A1 (en) 1980-04-04
DE2935847A1 (en) 1980-03-13
DE2935847C2 (en) 1987-02-05
SG16684G (en) 1985-02-15
MY8500476A (en) 1985-12-31

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Legal Events

Date Code Title Description
ST Notification of lapse