FR2432737A1 - METHOD FOR PERFORMING A DELETE AND HOLD INSTRUCTION - Google Patents

METHOD FOR PERFORMING A DELETE AND HOLD INSTRUCTION

Info

Publication number
FR2432737A1
FR2432737A1 FR7919355A FR7919355A FR2432737A1 FR 2432737 A1 FR2432737 A1 FR 2432737A1 FR 7919355 A FR7919355 A FR 7919355A FR 7919355 A FR7919355 A FR 7919355A FR 2432737 A1 FR2432737 A1 FR 2432737A1
Authority
FR
France
Prior art keywords
delete
hold instruction
interrupt
waited
erase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7919355A
Other languages
French (fr)
Other versions
FR2432737B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of FR2432737A1 publication Critical patent/FR2432737A1/en
Application granted granted Critical
Publication of FR2432737B1 publication Critical patent/FR2432737B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

a. Procédé pour effectuer une instruction d'effacement et d'attente. b. Procédé caractérisé en ce qu'on combine suivant la fonction ET, un octet immédiat avec le contenu du registre de code de condition, on interdit une interruption non masquable pendant cette combinaison, on empile les registres programmables et on attend une interruption pour la traiter sans avoir à conserver d'autres données.at. Method for performing an erase and wait instruction. b. Method characterized in that, according to the AND function, an immediate byte is combined with the contents of the condition code register, a non-maskable interrupt is prohibited during this combination, the programmable registers are stacked and an interrupt is waited to process it without have to keep other data.

FR7919355A 1978-07-31 1979-07-26 METHOD FOR PERFORMING A DELETE AND HOLD INSTRUCTION Granted FR2432737A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US92962978A 1978-07-31 1978-07-31

Publications (2)

Publication Number Publication Date
FR2432737A1 true FR2432737A1 (en) 1980-02-29
FR2432737B1 FR2432737B1 (en) 1984-02-10

Family

ID=25458184

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7919355A Granted FR2432737A1 (en) 1978-07-31 1979-07-26 METHOD FOR PERFORMING A DELETE AND HOLD INSTRUCTION

Country Status (6)

Country Link
JP (1) JPS5523598A (en)
DE (1) DE2931121A1 (en)
FR (1) FR2432737A1 (en)
GB (1) GB2027238B (en)
MY (1) MY8500477A (en)
SG (1) SG16584G (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1217310A (en) * 1981-09-14 1987-02-03 George B. Park Heat recoverable article
JP2602198B2 (en) * 1984-10-15 1997-04-23 三井東圧化学株式会社 Heat-resistant adhesive made of polyimide resin powder
JP2596536B2 (en) * 1984-10-15 1997-04-02 三井東圧化学株式会社 Heat-resistant adhesive made of polyimide resin powder
JPH0545366Y2 (en) * 1988-03-14 1993-11-19
GB2506169A (en) * 2012-09-24 2014-03-26 Imagination Tech Ltd Limiting task context restore if a flag indicates task processing is disabled

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970998A (en) * 1974-10-15 1976-07-20 Rca Corporation Microprocessor architecture

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003028A (en) * 1974-10-30 1977-01-11 Motorola, Inc. Interrupt circuitry for microprocessor chip

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970998A (en) * 1974-10-15 1976-07-20 Rca Corporation Microprocessor architecture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/73 *

Also Published As

Publication number Publication date
GB2027238B (en) 1982-12-01
SG16584G (en) 1985-03-08
DE2931121A1 (en) 1980-02-21
JPS6313213B2 (en) 1988-03-24
DE2931121C2 (en) 1988-09-01
MY8500477A (en) 1985-12-31
GB2027238A (en) 1980-02-13
JPS5523598A (en) 1980-02-20
FR2432737B1 (en) 1984-02-10

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