FR2426333A1 - HOUSING FOR SEMICONDUCTOR DEVICE - Google Patents
HOUSING FOR SEMICONDUCTOR DEVICEInfo
- Publication number
- FR2426333A1 FR2426333A1 FR7912275A FR7912275A FR2426333A1 FR 2426333 A1 FR2426333 A1 FR 2426333A1 FR 7912275 A FR7912275 A FR 7912275A FR 7912275 A FR7912275 A FR 7912275A FR 2426333 A1 FR2426333 A1 FR 2426333A1
- Authority
- FR
- France
- Prior art keywords
- housing
- semiconductor device
- electronics
- package
- fact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Casings For Electric Apparatus (AREA)
Abstract
La présente invention concerne un boîtier pour dispositif semi-conducteur. Ce boîtier est caractérisé par le fait qu'il comporte une lame métallique présentant, sur une grande partie de sa surface, une rainure aux parois en creux, dans laquelle pénètre un corps en résine. L'invention s'applique en électronique.The present invention relates to a package for a semiconductor device. This housing is characterized by the fact that it comprises a metal blade having, over a large part of its surface, a groove with recessed walls, into which a resin body penetrates. The invention applies to electronics.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT23432/78A IT1095885B (en) | 1978-05-16 | 1978-05-16 | HIGH HERMETICITY METAL AND RESIN CONTAINER FOR SEMICONDUCTOR DEVICE |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2426333A1 true FR2426333A1 (en) | 1979-12-14 |
FR2426333B3 FR2426333B3 (en) | 1982-03-19 |
Family
ID=11207026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7912275A Granted FR2426333A1 (en) | 1978-05-16 | 1979-05-15 | HOUSING FOR SEMICONDUCTOR DEVICE |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS553692A (en) |
DE (2) | DE7914024U1 (en) |
FR (1) | FR2426333A1 (en) |
GB (1) | GB2021315A (en) |
IT (1) | IT1095885B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT8224533A0 (en) * | 1982-12-01 | 1982-12-01 | Ora Sgs Microelettronica Spa S | HIGH RELIABILITY METAL AND RESIN ENCLOSURE FOR SEMICONDUCTOR DEVICE. |
DE4401588C2 (en) * | 1994-01-20 | 2003-02-20 | Gemplus Gmbh | Method for capping a chip card module and chip card module |
DE102010005771B4 (en) * | 2010-01-25 | 2012-12-13 | Heraeus Materials Technology Gmbh & Co. Kg | Modular metal strip, process for its manufacture and component with improved flatness |
-
1978
- 1978-05-16 IT IT23432/78A patent/IT1095885B/en active
-
1979
- 1979-05-10 GB GB7916238A patent/GB2021315A/en not_active Withdrawn
- 1979-05-15 DE DE19797914024U patent/DE7914024U1/en not_active Expired
- 1979-05-15 DE DE19792919540 patent/DE2919540A1/en not_active Withdrawn
- 1979-05-15 FR FR7912275A patent/FR2426333A1/en active Granted
- 1979-05-15 JP JP5874579A patent/JPS553692A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
DE2919540A1 (en) | 1979-11-22 |
GB2021315A (en) | 1979-11-28 |
DE7914024U1 (en) | 1983-04-07 |
JPS553692A (en) | 1980-01-11 |
IT1095885B (en) | 1985-08-17 |
FR2426333B3 (en) | 1982-03-19 |
IT7823432A0 (en) | 1978-05-16 |
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