FR2340622B1 - - Google Patents

Info

Publication number
FR2340622B1
FR2340622B1 FR7700642A FR7700642A FR2340622B1 FR 2340622 B1 FR2340622 B1 FR 2340622B1 FR 7700642 A FR7700642 A FR 7700642A FR 7700642 A FR7700642 A FR 7700642A FR 2340622 B1 FR2340622 B1 FR 2340622B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7700642A
Other languages
French (fr)
Other versions
FR2340622A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/656,756 external-priority patent/US4075045A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2340622A1 publication Critical patent/FR2340622A1/en
Application granted granted Critical
Publication of FR2340622B1 publication Critical patent/FR2340622B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
FR7700642A 1976-02-09 1977-01-05 Silicon gate FET mfr. - proceeds through preliminary formation of capacitor to five lithographic masking stages Granted FR2340622A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/656,756 US4075045A (en) 1976-02-09 1976-02-09 Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps
US05/702,247 US4085498A (en) 1976-02-09 1976-07-02 Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps

Publications (2)

Publication Number Publication Date
FR2340622A1 FR2340622A1 (en) 1977-09-02
FR2340622B1 true FR2340622B1 (en) 1980-10-24

Family

ID=27097257

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7700642A Granted FR2340622A1 (en) 1976-02-09 1977-01-05 Silicon gate FET mfr. - proceeds through preliminary formation of capacitor to five lithographic masking stages

Country Status (1)

Country Link
FR (1) FR2340622A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2842545C2 (en) * 1978-09-29 1980-07-31 Siemens Ag, 1000 Berlin Und 8000 Muenchen Semiconductor memory with depletion varactors as storage capacitors

Also Published As

Publication number Publication date
FR2340622A1 (en) 1977-09-02

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Legal Events

Date Code Title Description
ST Notification of lapse