FR2336009A1 - Synchronisation of distant digital equipment - employs returned clock pulses to block clock counter unless pulses are coincident - Google Patents

Synchronisation of distant digital equipment - employs returned clock pulses to block clock counter unless pulses are coincident

Info

Publication number
FR2336009A1
FR2336009A1 FR7539071A FR7539071A FR2336009A1 FR 2336009 A1 FR2336009 A1 FR 2336009A1 FR 7539071 A FR7539071 A FR 7539071A FR 7539071 A FR7539071 A FR 7539071A FR 2336009 A1 FR2336009 A1 FR 2336009A1
Authority
FR
France
Prior art keywords
pulses
clock
signals
returned
synchronisation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7539071A
Other languages
French (fr)
Other versions
FR2336009B1 (en
Inventor
Jacques Vernezy
Michel Monteagud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Priority to FR7539071A priority Critical patent/FR2336009A1/en
Publication of FR2336009A1 publication Critical patent/FR2336009A1/en
Application granted granted Critical
Publication of FR2336009B1 publication Critical patent/FR2336009B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Synchronisation of digital equipment located some distance from the principal equipment is obtained by compensating for transmission time delay. Clock signals are returned by the remote equipment to block the clock counter except when there is coincidence. Clock pulses are applied through a gate (7) to a binary counter (8) for application to a bipolar pulse generator (10). These signals are gated (26) with signals from a logic gating circuit (25) for transmission to the remote equipment via a two way cable. Returned signals enter an integrity detector (17) whose output is applied to a coincidence gate (23) with sync. frame signals (2). A bistable (24) ensures that the counter is blocked when non-coincidence occurs.
FR7539071A 1975-12-19 1975-12-19 Synchronisation of distant digital equipment - employs returned clock pulses to block clock counter unless pulses are coincident Granted FR2336009A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7539071A FR2336009A1 (en) 1975-12-19 1975-12-19 Synchronisation of distant digital equipment - employs returned clock pulses to block clock counter unless pulses are coincident

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7539071A FR2336009A1 (en) 1975-12-19 1975-12-19 Synchronisation of distant digital equipment - employs returned clock pulses to block clock counter unless pulses are coincident

Publications (2)

Publication Number Publication Date
FR2336009A1 true FR2336009A1 (en) 1977-07-15
FR2336009B1 FR2336009B1 (en) 1978-08-18

Family

ID=9163962

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7539071A Granted FR2336009A1 (en) 1975-12-19 1975-12-19 Synchronisation of distant digital equipment - employs returned clock pulses to block clock counter unless pulses are coincident

Country Status (1)

Country Link
FR (1) FR2336009A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4691294A (en) * 1984-09-21 1987-09-01 International Computers Limited Clock/data synchronization interface apparatus and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4691294A (en) * 1984-09-21 1987-09-01 International Computers Limited Clock/data synchronization interface apparatus and method

Also Published As

Publication number Publication date
FR2336009B1 (en) 1978-08-18

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Legal Events

Date Code Title Description
ST Notification of lapse