FR2331209A1 - Structure d'un decodeur modifiable pour un reseau logique - Google Patents

Structure d'un decodeur modifiable pour un reseau logique

Info

Publication number
FR2331209A1
FR2331209A1 FR7629484A FR7629484A FR2331209A1 FR 2331209 A1 FR2331209 A1 FR 2331209A1 FR 7629484 A FR7629484 A FR 7629484A FR 7629484 A FR7629484 A FR 7629484A FR 2331209 A1 FR2331209 A1 FR 2331209A1
Authority
FR
France
Prior art keywords
modifiable
decoder
logic network
logic
network
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7629484A
Other languages
English (en)
Other versions
FR2331209B1 (fr
Inventor
Se J Hong
Daniel L Ostapko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2331209A1 publication Critical patent/FR2331209A1/fr
Application granted granted Critical
Publication of FR2331209B1 publication Critical patent/FR2331209B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/001—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
FR7629484A 1975-11-06 1976-09-22 Structure d'un decodeur modifiable pour un reseau logique Granted FR2331209A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/629,259 US4029970A (en) 1975-11-06 1975-11-06 Changeable decoder structure for a folded logic array

Publications (2)

Publication Number Publication Date
FR2331209A1 true FR2331209A1 (fr) 1977-06-03
FR2331209B1 FR2331209B1 (fr) 1979-06-22

Family

ID=24522244

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7629484A Granted FR2331209A1 (fr) 1975-11-06 1976-09-22 Structure d'un decodeur modifiable pour un reseau logique

Country Status (3)

Country Link
US (1) US4029970A (fr)
JP (1) JPS5258435A (fr)
FR (1) FR2331209A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967107A (en) * 1989-05-12 1990-10-30 Plus Logic, Inc. Programmable logic expander
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2166231A1 (fr) * 1971-12-30 1973-08-10 Ibm
FR2296967A1 (fr) * 1974-12-30 1976-07-30 Ibm Reseau logique de grande densite
FR2296968A1 (fr) * 1974-12-30 1976-07-30 Ibm Reseaux de circuits logiques

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3816725A (en) * 1972-04-28 1974-06-11 Gen Electric Multiple level associative logic circuits
US3829846A (en) * 1972-11-15 1974-08-13 Honeywell Inc Multi-function logic module employing read-only associative memory arrays
JPS5224002B2 (fr) * 1973-06-29 1977-06-28
US3849638A (en) * 1973-07-18 1974-11-19 Gen Electric Segmented associative logic circuits
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2166231A1 (fr) * 1971-12-30 1973-08-10 Ibm
FR2296967A1 (fr) * 1974-12-30 1976-07-30 Ibm Reseau logique de grande densite
FR2296968A1 (fr) * 1974-12-30 1976-07-30 Ibm Reseaux de circuits logiques

Also Published As

Publication number Publication date
US4029970A (en) 1977-06-14
JPS5258435A (en) 1977-05-13
FR2331209B1 (fr) 1979-06-22

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Legal Events

Date Code Title Description
ST Notification of lapse