FR2296263A1 - FET mfr. with vertical channels - by epitaxial deposn. of doped layers with intermediate diffusion in grid pattern - Google Patents
FET mfr. with vertical channels - by epitaxial deposn. of doped layers with intermediate diffusion in grid patternInfo
- Publication number
- FR2296263A1 FR2296263A1 FR7442665A FR7442665A FR2296263A1 FR 2296263 A1 FR2296263 A1 FR 2296263A1 FR 7442665 A FR7442665 A FR 7442665A FR 7442665 A FR7442665 A FR 7442665A FR 2296263 A1 FR2296263 A1 FR 2296263A1
- Authority
- FR
- France
- Prior art keywords
- grid
- vertical channels
- epitaxial
- oxide layer
- deposn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 title abstract 3
- 230000008021 deposition Effects 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66416—Static induction transistors [SIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
- H01L29/66909—Vertical transistors, e.g. tecnetrons
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Method of making a field effect semiconductor device with vertical channels comprising a first epitaxial deposition on a monocrystalline wafer of semiconductor material of first conductivity type, a localised diffusion in one region of opposite conductivity type donant, constituting the grid of the device, and a second epitaxial deposition of first type conductivity, is characterised in that after the first deposition a localised prediffusion deposit is effected in the form of the said grid and this deposit is selectively covered with an oxide layer prior to effecting the second epitaxial deposition step, the material grown on the oxide layer being polycrystalline. The device is then subjected to a deep oxidn. step, reaching the grid, and the oxide layer formed from the monocrystal is removed and a surface diffusion giving first type conductivity is effected in those parts based of monocrystal. The cross sections of the vertical channels are maximised, their lengths minimised and the capacity between the grid and source is minimised while the breakdown voltage between the grid and source is maximised.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7442665A FR2296263A1 (en) | 1974-12-24 | 1974-12-24 | FET mfr. with vertical channels - by epitaxial deposn. of doped layers with intermediate diffusion in grid pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7442665A FR2296263A1 (en) | 1974-12-24 | 1974-12-24 | FET mfr. with vertical channels - by epitaxial deposn. of doped layers with intermediate diffusion in grid pattern |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2296263A1 true FR2296263A1 (en) | 1976-07-23 |
FR2296263B1 FR2296263B1 (en) | 1978-04-28 |
Family
ID=9146571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7442665A Granted FR2296263A1 (en) | 1974-12-24 | 1974-12-24 | FET mfr. with vertical channels - by epitaxial deposn. of doped layers with intermediate diffusion in grid pattern |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2296263A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2452784A1 (en) * | 1979-03-30 | 1980-10-24 | Hitachi Ltd | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND PARTICULARLY A THYRISTOR |
US4586239A (en) * | 1983-06-30 | 1986-05-06 | Thomson-Csf | Process of manufacturing a high-frequency vertical junction field-effect transistor |
-
1974
- 1974-12-24 FR FR7442665A patent/FR2296263A1/en active Granted
Non-Patent Citations (1)
Title |
---|
NEANT * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2452784A1 (en) * | 1979-03-30 | 1980-10-24 | Hitachi Ltd | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND PARTICULARLY A THYRISTOR |
US4586239A (en) * | 1983-06-30 | 1986-05-06 | Thomson-Csf | Process of manufacturing a high-frequency vertical junction field-effect transistor |
Also Published As
Publication number | Publication date |
---|---|
FR2296263B1 (en) | 1978-04-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4554570A (en) | Vertically integrated IGFET device | |
US4476622A (en) | Recessed gate static induction transistor fabrication | |
US3149395A (en) | Method of making a varactor diode by epitaxial growth and diffusion | |
US3913124A (en) | Integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector including fabrication method therefor | |
Schubert et al. | Confined lateral selective epitaxial growth of silicon for device fabrication | |
US3461360A (en) | Semiconductor devices with cup-shaped regions | |
US3440503A (en) | Integrated complementary mos-type transistor structure and method of making same | |
US3126505A (en) | Field effect transistor having grain boundary therein | |
GB1089098A (en) | Semiconductor device | |
US3703420A (en) | Lateral transistor structure and process for forming the same | |
US3041213A (en) | Diffused junction semiconductor device and method of making | |
US3787253A (en) | Emitter diffusion isolated semiconductor structure | |
US3730787A (en) | Method of fabricating semiconductor integrated circuits using deposited doped oxides as a source of dopant impurities | |
US3660732A (en) | Semiconductor structure with dielectric and air isolation and method | |
FR2296263A1 (en) | FET mfr. with vertical channels - by epitaxial deposn. of doped layers with intermediate diffusion in grid pattern | |
US3442723A (en) | Method of making a semiconductor junction by diffusion | |
US3455748A (en) | Method of making a narrow base transistor | |
GB1279588A (en) | Improvements in or relating to the production of insulated semi-conductor regions in a composite body | |
IE33385B1 (en) | Semiconductor device and fabrication of same | |
JPH0523054B2 (en) | ||
van Nielen et al. | MOS transistors in thin monocrystalline silicon layers | |
US3187241A (en) | Transistor with emitter at bottom of groove extending crosswise the base | |
KR0149435B1 (en) | The isolation method of bipolar transistor | |
KR0144353B1 (en) | Method of manufacturing bipolar device | |
FR2284189A1 (en) | Forming polycrystalline areas on substrate - using laser or electron beam preparing areas for epitaxial deposition |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |