FR2233779A1 - Fault detection in addressing units - is effected by generating combinations and memorising faulty addresses in fault detector - Google Patents

Fault detection in addressing units - is effected by generating combinations and memorising faulty addresses in fault detector

Info

Publication number
FR2233779A1
FR2233779A1 FR7321418A FR7321418A FR2233779A1 FR 2233779 A1 FR2233779 A1 FR 2233779A1 FR 7321418 A FR7321418 A FR 7321418A FR 7321418 A FR7321418 A FR 7321418A FR 2233779 A1 FR2233779 A1 FR 2233779A1
Authority
FR
France
Prior art keywords
fault detector
effected
address
fault
memorising
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7321418A
Other languages
French (fr)
Other versions
FR2233779B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Le Materiel Telephonique Thomson CSF
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Le Materiel Telephonique Thomson CSF filed Critical Le Materiel Telephonique Thomson CSF
Priority to FR7321418A priority Critical patent/FR2233779A1/en
Priority to AU69657/74A priority patent/AU6965774A/en
Publication of FR2233779A1 publication Critical patent/FR2233779A1/en
Application granted granted Critical
Publication of FR2233779B1 publication Critical patent/FR2233779B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

Binary addressing units are employed in computer controlled telephone systems where there are a large number of repetitive equipments. Satisfactory operation of the address memory is effected by using a fault detector connected between the outputs of decoding circuits and the address inputs of the addressable memories. A fault detector (1) is connected to associated switching circuits and to the spacial address memory (2) whose output is controlled by the fault detector through the control unit (4) of the switching system. This unit contains the clock pulse generator (5) and control computer (6). Binary elements are transmitted via a register (7) to the inputs of multiplexers (8) in a matrix (3) with associated decoders (9). This enables a number of address combinations to be made, any faults are memorised in an addressable memory (10).
FR7321418A 1973-06-13 1973-06-13 Fault detection in addressing units - is effected by generating combinations and memorising faulty addresses in fault detector Granted FR2233779A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR7321418A FR2233779A1 (en) 1973-06-13 1973-06-13 Fault detection in addressing units - is effected by generating combinations and memorising faulty addresses in fault detector
AU69657/74A AU6965774A (en) 1973-06-13 1974-05-31 Fault detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7321418A FR2233779A1 (en) 1973-06-13 1973-06-13 Fault detection in addressing units - is effected by generating combinations and memorising faulty addresses in fault detector

Publications (2)

Publication Number Publication Date
FR2233779A1 true FR2233779A1 (en) 1975-01-10
FR2233779B1 FR2233779B1 (en) 1977-02-18

Family

ID=9120858

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7321418A Granted FR2233779A1 (en) 1973-06-13 1973-06-13 Fault detection in addressing units - is effected by generating combinations and memorising faulty addresses in fault detector

Country Status (2)

Country Link
AU (1) AU6965774A (en)
FR (1) FR2233779A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2305085A1 (en) * 1975-03-21 1976-10-15 Thomson Csf TELEPHONE SWITCHING SYSTEM
EP0162270A1 (en) * 1984-04-19 1985-11-27 Siemens Aktiengesellschaft Method for testing switched connexions of a multiplex space division switching network

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NEANT *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2305085A1 (en) * 1975-03-21 1976-10-15 Thomson Csf TELEPHONE SWITCHING SYSTEM
EP0162270A1 (en) * 1984-04-19 1985-11-27 Siemens Aktiengesellschaft Method for testing switched connexions of a multiplex space division switching network

Also Published As

Publication number Publication date
AU6965774A (en) 1975-12-04
FR2233779B1 (en) 1977-02-18

Similar Documents

Publication Publication Date Title
GB8719936D0 (en) Column redundancy circuit
US4047008A (en) Pseudo-random number sequence generator
US3852723A (en) Programmable signal distribution system
KR920010618A (en) Synchronous Dynamic RAM
GB1531528A (en) Apparatus for providing valid information for invalid information in unalterable memory means
GB1423698A (en) Computer storage systems
KR930022383A (en) Memory chip refresh address test circuit
KR970051090A (en) Pumping Voltage Generator of Semiconductor Memory Device
KR870003431A (en) Data processing device
KR930022371A (en) Multi-port memory system
JPH07169265A (en) Synchronous random-access memory device
KR940020415A (en) COLUMN REDUNDANCE CIRCUIT CONFIGURATION FOR A MEMORY
US3761882A (en) Process control computer
US3824562A (en) High speed random access memory shift register
KR910002191A (en) Dial signal generator for dial pulse signal and dual tone multi-frequency signal generation
US3221310A (en) Parity bit indicator
FR2233779A1 (en) Fault detection in addressing units - is effected by generating combinations and memorising faulty addresses in fault detector
US3745533A (en) Digital data storage register modules
KR940007873A (en) Flash write circuit of semiconductor memory device
US3866061A (en) Overlap timing control circuit for conditioning signals in a semiconductor memory
US4603235A (en) Dynamic event selection network
US3208053A (en) Split-array core memory system
SU877538A1 (en) Memory unit control device
KR970012709A (en) Semiconductor Memory Using Block Writing System
SU926619A1 (en) Device for technical equipment program control

Legal Events

Date Code Title Description
ST Notification of lapse