FR2201786A5 - - Google Patents

Info

Publication number
FR2201786A5
FR2201786A5 FR7334644A FR7334644A FR2201786A5 FR 2201786 A5 FR2201786 A5 FR 2201786A5 FR 7334644 A FR7334644 A FR 7334644A FR 7334644 A FR7334644 A FR 7334644A FR 2201786 A5 FR2201786 A5 FR 2201786A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7334644A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of FR2201786A5 publication Critical patent/FR2201786A5/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1673Details of memory controller using buffers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR7334644A 1972-09-29 1973-09-27 Expired FR2201786A5 (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19722247780 DE2247780A1 (de) 1972-09-29 1972-09-29 Anordnung zum erhoehen der trefferrate in einem speichersystem

Publications (1)

Publication Number Publication Date
FR2201786A5 true FR2201786A5 (enExample) 1974-04-26

Family

ID=5857730

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7334644A Expired FR2201786A5 (enExample) 1972-09-29 1973-09-27

Country Status (5)

Country Link
BE (1) BE805469A (enExample)
DE (1) DE2247780A1 (enExample)
FR (1) FR2201786A5 (enExample)
IT (1) IT993475B (enExample)
NL (1) NL7313196A (enExample)

Also Published As

Publication number Publication date
DE2247780A1 (de) 1974-05-16
BE805469A (fr) 1974-03-28
NL7313196A (enExample) 1974-04-02
IT993475B (it) 1975-09-30

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Legal Events

Date Code Title Description
ST Notification of lapse