FR2199231A1 - - Google Patents
Info
- Publication number
- FR2199231A1 FR2199231A1 FR7328909A FR7328909A FR2199231A1 FR 2199231 A1 FR2199231 A1 FR 2199231A1 FR 7328909 A FR7328909 A FR 7328909A FR 7328909 A FR7328909 A FR 7328909A FR 2199231 A1 FR2199231 A1 FR 2199231A1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
- H03K9/06—Demodulating pulses which have been modulated with a continuously-variable signal of frequency- or rate-modulated pulses
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4902—Pulse width modulation; Pulse position modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US28713272A | 1972-09-07 | 1972-09-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2199231A1 true FR2199231A1 (de) | 1974-04-05 |
FR2199231B1 FR2199231B1 (de) | 1976-05-07 |
Family
ID=23101591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7328909A Expired FR2199231B1 (de) | 1972-09-07 | 1973-07-30 |
Country Status (9)
Country | Link |
---|---|
JP (1) | JPS4966116A (de) |
BE (1) | BE804062A (de) |
CA (1) | CA1037570A (de) |
CH (1) | CH573691A5 (de) |
FR (1) | FR2199231B1 (de) |
GB (1) | GB1442444A (de) |
IT (1) | IT992697B (de) |
NL (1) | NL7311473A (de) |
SE (1) | SE392551B (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5789769A (en) * | 1980-11-26 | 1982-06-04 | Nippon Denso Co Ltd | Controller for copying machine group |
CN114090482A (zh) * | 2021-09-28 | 2022-02-25 | 荣湃半导体(上海)有限公司 | 一种传输数据的延迟抵消方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2092464A5 (de) * | 1970-04-27 | 1972-01-21 | Ibm | |
NL7115729A (de) * | 1971-01-25 | 1972-07-27 | ||
FR2136906A1 (de) * | 1971-05-07 | 1972-12-29 | Automatisme Cie Gle |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3631422A (en) * | 1969-02-03 | 1971-12-28 | Ibm | System for detection of data time interval measurement |
US3711843A (en) * | 1970-04-27 | 1973-01-16 | Olivetti & Co Spa | Self-adapting synchronization system for reading information from a moving support |
JPS4861122A (de) * | 1971-12-02 | 1973-08-27 |
-
1973
- 1973-07-26 IT IT2709873A patent/IT992697B/it active
- 1973-07-30 FR FR7328909A patent/FR2199231B1/fr not_active Expired
- 1973-07-31 SE SE7310516A patent/SE392551B/xx unknown
- 1973-08-16 CA CA179,117A patent/CA1037570A/en not_active Expired
- 1973-08-21 NL NL7311473A patent/NL7311473A/xx not_active Application Discontinuation
- 1973-08-27 BE BE134972A patent/BE804062A/xx unknown
- 1973-08-29 JP JP48096252A patent/JPS4966116A/ja active Pending
- 1973-08-30 GB GB4077673A patent/GB1442444A/en not_active Expired
- 1973-08-30 CH CH1242073A patent/CH573691A5/xx not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2092464A5 (de) * | 1970-04-27 | 1972-01-21 | Ibm | |
NL7115729A (de) * | 1971-01-25 | 1972-07-27 | ||
FR2136906A1 (de) * | 1971-05-07 | 1972-12-29 | Automatisme Cie Gle |
Non-Patent Citations (1)
Title |
---|
REVUE US : IBM TECHNICAL DISCLOSURE BULLETIN, VOLUME 14, N 6, NOVEMBRE 1971. ARTICLE DE NICCORE : "PHASE-LOCK LOOP WITH CONSTANT DUTY CYCLE" PAGES 1838 ET 1839. * |
Also Published As
Publication number | Publication date |
---|---|
NL7311473A (de) | 1974-03-11 |
FR2199231B1 (de) | 1976-05-07 |
DE2343472A1 (de) | 1974-03-28 |
SE392551B (sv) | 1977-03-28 |
DE2343472B2 (de) | 1975-08-21 |
BE804062A (fr) | 1973-12-17 |
GB1442444A (en) | 1976-07-14 |
CH573691A5 (de) | 1976-03-15 |
CA1037570A (en) | 1978-08-29 |
IT992697B (it) | 1975-09-30 |
JPS4966116A (de) | 1974-06-26 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |